Pruna, R.; Palacio, F.; Baraket, A.; Bausells, J.; Errachid, A.; López, M.
Low-Cost Impedance Measurements for Lab-on-a-Chip Architectures: Towards Potentiostat Miniaturization. Proceedings 2017, 1, 604.
https://doi.org/10.3390/proceedings1040604
AMA Style
Pruna R, Palacio F, Baraket A, Bausells J, Errachid A, López M.
Low-Cost Impedance Measurements for Lab-on-a-Chip Architectures: Towards Potentiostat Miniaturization. Proceedings. 2017; 1(4):604.
https://doi.org/10.3390/proceedings1040604
Chicago/Turabian Style
Pruna, Raquel, Francisco Palacio, Abdoullatif Baraket, Joan Bausells, Abdelhamid Errachid, and Manel López.
2017. "Low-Cost Impedance Measurements for Lab-on-a-Chip Architectures: Towards Potentiostat Miniaturization" Proceedings 1, no. 4: 604.
https://doi.org/10.3390/proceedings1040604
APA Style
Pruna, R., Palacio, F., Baraket, A., Bausells, J., Errachid, A., & López, M.
(2017). Low-Cost Impedance Measurements for Lab-on-a-Chip Architectures: Towards Potentiostat Miniaturization. Proceedings, 1(4), 604.
https://doi.org/10.3390/proceedings1040604