Open and Collaborative Dataset for the Classification of Operational Transconductance Amplifiers for Switched-Capacitor Applications

Abstract

This study introduces a collaborative and open dataset designed to classify operational transconductance amplifiers (OTAs) in switched-capacitor applications. The dataset comprises a diverse collection of OTA designs sourced from the literature, facilitating benchmarking, analysis and innovation in analog and mixed-signal integrated circuit design. Various evaluation methodologies, implemented through a companion Python notebook script, are discussed to assess OTA performances across different operating conditions and specifications. Several Figures of Merit (FoMs) are utilized as performance metrics to achieve significant performance classification. This study also uncovers intriguing behaviors and correlations among FoMs, providing valuable insights into OTA design considerations. By making the dataset openly available on platforms like GitHub, this work encourages collaboration and knowledge sharing within the integrated circuit design community, thereby enhancing transparency, reproducibility and innovation in OTA design research.

Dataset: https://github.com/michele-dei/OTA-settling-survey.

Dataset License: Dataset available under the GNU General Public License (GPL) version 3.

1. Introduction

In the context of analog integrated circuit design, operational transconductance amplifiers (OTAs) play a crucial role in various electronic systems, including switched-capacitor (SC) applications. OTAs serve as fundamental building blocks in modern communication, sensing, driving and signal-processing systems [1,2,3].

The performance and efficiency of OTAs greatly influence the overall functionality of integrated circuits [4,5]. Therefore, the classification of OTAs is essential to optimize circuit design, enhancing performances, and to meet application-specific requirements such as settling time, slew rate, bandwidth at specific conditions of capacitive loading and settling accuracy [6].

Existing research concerning OTA design has primarily focused on the analysis of OTA circuits based on their circuital topology [7,8], design methodology [9,10,11,12] or CMOS technological node [13,14].

The design process of OTAs continues to demand significant technical expertise. Presently, this process is predominantly facilitated by Electronic Design Automation (EDA) tools; nevertheless, designers are often confronted with the challenging responsibility of meticulously selecting the appropriate circuit topology based on given requirements (e.g., process, power consumption, accuracy). Furthermore, reaching state-of-art performances still implies complex optimization procedures, stemming from an in-depth understanding of specific circuit topologies and related design trade-offs. Insofar, fully automated design procedures are still far from being available.

In pursuit of cost reduction and accelerated project timelines, future iterations of EDA tools are poised to integrate Artificial Intelligence (AI) to a greater extent [15,16]. AI algorithms will progressively assume responsibility for an expanding range of tasks, beginning with repetitive duties such as layout drawing. Subsequently, AI will advance to tasks involving the optimization of circuit parameters by exploring the design space, culminating in abstract endeavors such as synthesizing circuit sub-topologies to devise novel architectural solutions [17,18].

Nevertheless, the absence of high-quality datasets for training and evaluating classification models remains a significant challenge, with sparse information scattered throughout the scientific literature. This limitation impedes the progress of developing and bench-marking classification techniques.

In response to this challenge, this study presents a collaborative and open dataset for OTA classification in switched-capacitor applications. By leveraging contributions from multiple sources and fostering collaboration within the research community, this dataset aims to facilitate advancements in OTA classification and supports the optimization of the design process. Equally crucial is the necessity for this dataset to be openly accessible, fostering a democratic transition of society into the digital age [19].

2. Dataset Description

In the following, we provide comprehensive information about the various attributes of the proposed dataset, including its context, its structure and its contents.

The database title “OTA Settling Survey” conveys the focus and purpose of the dataset, drawing inspiration from the renowned “ADC Performance Survey” by Murmann [20]. The term “settling” pertains to the OTA performance, which is usually of greatest interest in switched-capacitor applications. With settling performance, we refer to the speed of the OTA output voltage in recovering from abrupt variations, up to settling to a desired voltage level (under specified accuracy requirements). SC circuits are discrete-time systems whose operations are based on charge transfers among capacitors, assisted by OTAs in closed-loop configurations. OTAs configured with negative feedback provide low-impedance nodes, allowing for almost ideal charge transfer processes. However, correct functionality is achieved as long as OTAs are able to charge/discharge their load capacitors quickly enough as to make transient duration substantially smaller than the clock period. In light of this, bandwidth, slew rate and, most importantly, settling time serve as cornerstone characteristics of such circuits in the above-mentioned applications [21].

2.1. Data Source

The dataset is built starting from sourcing the scientific literature accessible through various online search engines and platforms for the scientific and technical literature, including IEEE Xplore, MDPI, Springer, Elsevier and Wiley, among others. These platforms serve as valuable repositories of scholarly articles, research papers and publications, providing a rich pool of data for analysis and exploration.

An exhaustive search is conducted across these search engines, utilizing key phrases such as ‘OTA’, ‘settling time’ and ‘switched capacitors’. Each article retrieved in the search results undergoes meticulous manual extraction of quantitative information. This method ensures thoroughness and accuracy in capturing relevant data from the scientific literature, filtering out data of questionable quality.

At this juncture, it is essential to distinguish between two fundamental types of data obtained through electrical simulations performed with EDA tools: measured performances and simulated data. Measured results are deemed of higher quality as they demonstrate actual metrics obtained in real-world scenarios, thereby overcoming any potential inaccuracies inherent in electrical models of the devices and/or other non-idealities not accounted for during simulations. However, direct measurements may not always be feasible, especially for very fast operational transconductance amplifiers (OTAs) or those loaded with very small capacitance values (e.g., <1 pF). Moreover, several research works also only report simulated results because of the relatively high fabrication costs and long turn-around times of integrated circuit prototypes. However, simulated results can still be relevant if sufficiently accurate analyses are included (e.g., process–voltage–temperature corner simulations, Monte Carlo statistical simulations, post-layout simulations). Consequently, articles describing both experimental and simulation approaches are considered in the dataset compilation process. The nature of the results, however, is reported in the dataset as a specific data field (EXPM).

2.2. Data Structure

The dataset is structured in a tabular format within a spreadsheet (.xlsx), incorporating the fields outlined in

Table 1. Spreadsheet headings of the “OTA Settling Survey” dataset (field, variable, units) and the corresponding entry type.

Field	Variable	Units	Entry Type
Digital Object Identifier	DOI		Alphanumeric
Title	TITL		Text
First author	AU1		Text
Year	YEAR		Numeric (YYYY)
CMOS technological node	CMOS	[nm]	Numeric
Number of gain stages	NS		Numeric
Signal Configuration	SCFG		Either ‘Single-ended’ or ‘Fully-differential’
Test setup	TEST		Possible choices: ‘Not specified’, ‘RC-beta’, ‘Switched-cap configuration’, ‘Unity-gain buffer’, ‘Unity-gain R-beta’
Feedback factor ($\beta$)	BETA		Numeric
Experimental method	EXPM		Either ‘Measured’ or ‘Simulated’
Effective capacitive load	CLE	[pF]	Numeric
Overall supply $V_{DD}-V_{SS}$	SUP	[V]	Numeric
Input Voltage Step	DVS	[V]	Numeric
Positive Slew Rate	SRP	[V/µs]	Numeric
Negative Slew Rate	SRN	[V/µs]	Numeric
Unity-gain frequency	UGF	[MHz]	Numeric
Settling Time (positive step)	TSP	[ns]	Numeric
Settling Time (negative step)	TSN	[ns]	Numeric
Settling Error	SERR	[%]	Numeric
Power	PWR	[µW]	Numeric
Area	AREA	[mm2]	Numeric
Open-loop DC gain	A0	[dB]	Numeric
Phase Margin	PM	[degree]	Numeric
Offset	OS	[mV]	Numeric
Spot Noise	SNOI	[nVrms/$\sqrt{\mathrm{Hz}}$@kHz]	Numeric
Integrated Noise	INOI	[µVrms@kHz]	Numeric

. For each field, a short-named variable is associated, referenced for numerical calculations to assess the performance metrics described in Section 3. Units are also specified whenever pertinent. For better clarity, the data entry type is also indicated.

The Digital Object Identifier, title, first author, and year fields (denoted as DOI, TITL, AU1, YEAR, respectively) enable the unique identification of the research work. While the data are graphically represented in scatter plots, the design instances are labeled by combining the first author’s name and the year of publication (author + year format).

The CMOS technological node (CMOS) is relevant for investigating the impact of adopting different technology nodes on the performance.

The number of gain stages (NS) is related to the circuit topology of the OTA. Typically, the choice is limited to three major architectures: single-stage, two-stage or three-stage (i.e., NS $\in (1,2,3)$).

The signal configuration (SCFG), either single-ended or fully differential, is mainly determined by the application and is relevant in determining the intended use of the OTA

The test setup (TEST) is identified among the following possible choices: ‘Not specified’, ‘RC-beta’, ‘Switched-cap configuration’, ‘Unity-gain buffer’, and ‘Unity-gain R-beta’, as illustrated in Figure 1. Configurations (a) and (d) are used, respectively, for single-ended and fully differential setups to characterize the OTA in unity-gain configuration [22]. Configurations (b) and (e) are often used for very high-speed designs to resemble a switched-capacitor amplifier, applying a pulsed input as in the previous configuration case [23]. For these configurations, $Z_1=R_1+{\left(j\omega C_1\right)}^{-1}$ and $Z_2=R_2+{\left(j\omega C_2\right)}^{-1}$. It is important to set $Z_2=G·Z_1$, where G is the desired voltage gain. This condition imposes the compensation conditions: $R_2=G·R_1$ and $C_2=C_1/G$. Configurations (c) and (f) represent the actual switched-capacitor amplifier/integrator configuration [24]. Direct measurements of these latter configurations are less straightforward.

The feedback factor, BETA, is derived from specific test setup configurations (see

Table 2. Correspondence between the circuital parameters relative to the configurations shown in Figure 1 and BETA and CLE.

	(a) and (d)	(b) and (e) 1	(c) and (f)
BETA	1	${\displaystyle \frac{C_2}{C_1+C_2}}$	${\displaystyle \frac{C_2}{C_1+C_2}}$
CLE	$C_L$	$C_L+{\displaystyle \frac{C_1{C}_2}{C_1+C_2}}$	$C_L+{\displaystyle \frac{C_1{C}_2}{C_1+C_2}}$

¹ Compensation condition is assumed: $R_1/R_2=C_2/C_1$.

). As discussed in [6], this factor inherently impacts the evaluation of performance metrics and could potentially be utilized for additional normalizations of the Figures of Merit (FoMs) when comparing different OTA designs. However, for simplicity, the incorporation of BETA into the FoMs of Section 3 is not addressed in this context.

The experimental method, denoted as EXPM, indicates whether the metrics are derived from measurements (‘Measured’) or electrical simulations (‘Simulated’).

The effective capacitive load, CLE, indicates the loading condition, considering also the feedback network (see Table 2).

The input voltage step, DVS, refers to the amplitude of the stimulus step used in the measurement of the settling parameters (specifically for what concerns SRP, SRN, TSP and TSN).

The overall supply voltage, SUP, refers to the supply configuration, which can either be a single supply ($V_{DD}$) or a dual supply (with $V_{DD}$ representing the highest supply voltage and $V_{SS}$ representing the lowest supply voltage). For all data analyses, only the term $V_{DD}-V_{SS}$ is relevant (or $V_{DD}$, in the case of a single supply).

The remaining fields (SRP, SRN, UGF, TSP, TSN, SERR, PWR, AREA, A0, PM, OS, SNOI, INOI) pertain to characteristic performance metrics of OTAs, namely positive and negative slew rates, unity-gain frequency, low-to-high and high-to-low settling times, settling accuracy, power consumption, area occupation, phase margin, input referred offset (standard deviation), root-mean-squared noise density given at a specific frequency spot, and root-mean-squared noise integrated in the bandwidth from DC to the given frequency value, respectively.

2.3. Data Usage

The intended usage of the collected data should serve two primary purposes, listed as follows:

• Expanding the Reference Pool: Continuously updating the spreadsheet to encompass future research works, as well as incorporating previously published works not currently included in the database, thereby enriching the perspective on the state of the art of OTA designs.
• Data Analysis: Employing simple Python scripts (or equivalent script tools) to visualize, rank, or classify the design instances using the methods outlined and described in Section 3. Additionally, there is the possibility of introducing new methods tailored to more specific analyses.

The GNU General Public License (GPL) version 3 is applied to both the spreadsheet and the Python notebook associated with the ‘OTA Settling Survey’ dataset. This choice ensures that the dataset remains openly accessible and can be freely used, modified, and shared by all, while also guaranteeing that derivative works remain open. Interested readers are encouraged to make use of the proposed dataset according to these principles to foster novel widespread awareness in the subject of fast-settling OTA design.

3. Methodology

Perfromances of the designs are measured through the following set of FoMs [6]:

$$\begin{array}{ccc}\hfill & \mathrm{FOMS}={\displaystyle \frac{\mathtt{UGF}\times \mathtt{CLE}}{\mathtt{PWR}}}& (\text{small-signal}\mathrm{FoM}),\hfill \end{array}$$

(1)

$$\begin{array}{ccc}\hfill & \mathrm{FOML}={\displaystyle \frac{\mathrm{SR}\times \mathtt{CLE}}{\mathtt{PWR}}}& (\text{large-signal}\mathrm{FoM}),\hfill \end{array}$$

(2)

$$\begin{array}{ccc}\hfill & \mathrm{FOMT}={\displaystyle \frac{\mathtt{CLE}}{t_{\mathrm{SET}}\times \mathtt{PWR}}}& (\text{settling-time}\mathrm{FoM}),\hfill \end{array}$$

(3)

$$\begin{array}{ccc}\hfill & \mathrm{FOMN}={\displaystyle \frac{\mathtt{CLE}\times \mathtt{DVS}}{t_{\mathrm{SET}}\times I_{DD}}}& (\text{input-step normalized}\mathrm{FoM}).\hfill \end{array}$$

(4)

To calculate these quantities, the worst-case slew rate, SR, and the worst-case settling time, $t_{\mathrm{SET}}$, are extracted from the parameters of Table 1 as follows:

$$\begin{array}{ccc}\hfill \mathrm{SR}& =& \mathrm{fmin}\left(\mathtt{SRN},\mathtt{SRP}\right),\hfill \end{array}$$

(5)

$$\begin{array}{ccc}\hfill t_{\mathrm{SET}}& =& \mathrm{fmax}\left(\mathtt{TSN},\mathtt{TSP}\right).\hfill \end{array}$$

(6)

The functions ‘fmin()’ and ‘fmax()’ correspond to element-wise max and min functions, respectively, between two arrays, taking care of NaN (not-a-number) cases. If one of the elements being compared is a NaN, the non-NaN element is returned [25,26]. A NaN value is present whenever the corresponding spreadsheet field is left blank. This could happen, for example, if only one value between SRP and SRN is annotated.

Finally, in Equation (4), $I_{DD}$ indicates the static current drawn from the supply, derived from the dataset as follows:   

$$I_{DD}={\displaystyle \frac{\mathtt{PWR}}{\mathtt{SUP}}}.$$

(7)

The FoMs of Equations (1)–(4) are focused on classifying OTA performances in terms of settling speed vs. power efficiency at a given loading condition. In this respect, FOMN is the most descriptive since it also accounts for the amplitude of the input voltage step (DVS). A detailed discussion on the differences between the FoMs is developed in [6].

Clearly, new FoMs can be introduced to account for other design aspects as well, such as open-loop DC gain (A0), phase margin (PM) or silicon area occupation (AREA). This is left for possible future explorations of the dataset.

In this work, we explore the state-of-the-art literature using the FoMs of Equations (1)–(4), employing the following classification methods:

• Ranking the top-10 designs in terms of each FoM;
• Ranking the top-10 designs in terms of FOMN/CLE;
• Mapping the best FoM against the OTA architecture (NS);
• Placing each design case in a FoM vs. CLE scatter plot;
• Visualizing each design case in an FoM vs. technological node (CMOS) scatter plot;
• Analyzing the correlations between the four FoMs.

Data-elaboration functions used in the Python notebook script are described in Appendix A.

4. Results and Discussion

The results in both tabular and graphical formats are obtained by running the Python notebook script. A straightforward classification of each design with respect to each FoM is exhibited in Figure 2. The tabular output serves as a valuable tool for identifying specific publications by displaying key information such as the DOI (Digital Object Identifier) and other significant fields (AU1, YEAR).

Classification by simple ranking, however, is not sufficient to deduce the best OTA design. It is worth noting that OTA design with fast-settling targets encompasses both topological choices and slew-rate-enhancing mechanisms [6]. The effectiveness of each solution is benchmarked against specific operating conditions and specifications (CLE, SUP, DVS, BETA, SERR). Therefore, a holistic evaluation of OTA designs requires considering a range of factors beyond just performance metrics. Further exploration of the dataset involves comprehensive benchmarking and analysis to identify optimal designs tailored to specific requirements and operating conditions. These considerations led us to explore 2D design spaces represented by the FoM vs. CLE axes of Figure 3.

As discussed in [6], a trend line can be observed, which is particularly evident in the FOMN–CLE space. The tabular output shown in Figure 4 presents the ranking based on the trend-line slope coefficient, R_FOMN_CLE [ppm/pF], defined by

$$\mathtt{R}\_\mathtt{FOMN}\_\mathtt{CLE}={\displaystyle \frac{\mathtt{FOMN}}{\mathtt{CLE}}}.$$

(8)

The measured results report a lower maximum R_FOMN_CLE (292 ppm/pF) compared to simulation results (420 ppm/pF). As anticipated, this discrepancy can be attributed to the intrinsic difficulties of reproducing the operating conditions of a switched-capacitor stage in a test setup where the probe loading cannot be neglected. Additionally, it is worth mentioning that high-speed switched-capacitor stages are typically intended for uses in larger systems such as filters, $\Delta \Sigma$ modulators or pipeline analog-to-digital converters, where the stage under test is typically loaded by similar sub-circuits presenting an equivalent load capacitance well below the 10 pF level.

Figure 5 illustrates a potential classification based on the number of stages (NS) to evaluate the impact of architectural choices. A general trend of superiority for single-stage designs over multistage ones is observed. Multistage topologies are often utilized in low-voltage designs to address DC gain limitations resulting from the inability to employ cascode configurations. While the results presented in Figure 5 offer valuable insights, it is evident that further refinement is necessary to draw more robust conclusions. Enriching the dataset with additional references dedicated to this aspect would be advantageous and is earmarked for future developments.

Regarding the impact of the CMOS technological node on performances, it is evident from Figure 6a that, currently, the 180 nm CMOS node collects the greatest number of designs, followed by the 500 nm CMOS and the 130 nm CMOS nodes. Apparently, implementations in 180 nm CMOS show superior performances in terms of FoMs. However, concerning absolute settling speed, the best result is obtained with the 40 nm CMOS node, as shown in the tabular output of Figure 6b.

Interdependences among the FoMs represent a crucial aspect in evaluating OTA performances. As previously introduced, transitioning to the unified FOMN seems to offer several advantages, leading to higher correlations in performance classification between designs featuring similar architectures, as proven by the clusters emerging in Figure 3d. These considerations were already discussed in [6] and are partially confirmed by the general trends shown in plots in Figure 7. However, a closer examination reveals the emergence of the following behaviors:

• In the FOMT–FOMN plot of Figure 7a, a high degree of correlation is evident. This can be easily understood by directly elaborating Equations (3), (4) and (7), resulting in the following relation:

  $$\mathrm{FOMN}=\mathtt{DVS}\times \mathtt{SUP}\times \mathrm{FOMT}.$$

  (9)
  Moreover, the maximum input range DVS is related to the supply range SUP: $\mathtt{DVS}=\alpha \mathtt{SUP}$, where $\alpha \in (0,1]$ is determined by specific design choices (e.g., stage gain, employment of cascode configurations or complementary input pairs). Hence,

  $$s_{N,T}={\displaystyle \frac{\mathrm{FOMN}}{\mathrm{FOMT}}}=\alpha {\mathtt{SUP}}^2.$$

  (10)
  Equation (10) linearly relates FOMN and FOMT for a given SUP, through a coefficient equal to $\alpha {\mathtt{SUP}}^2$. However, since SUP may vary from design to design, a band appears in the bilogarithmic plot of Figure 7a. Under the same FOMT performance, a better FOMN is achieved for larger supplies and larger input steps. The upper limit of this band is clearly determined by the interpolation of (10) to the design case with the highest $\alpha {\mathtt{SUP}}^2$, whereas the lower limit of the band corresponds to the design case with the smaller $\alpha {\mathtt{SUP}}^2$ value. This phenomenon suggests that a specific design with a given FOMN scales with ${\mathtt{SUP}}^2$ law, when FOMT is considered. Clearly, this argument has some practical limitations: excessively up-scaling SUP may incur a violation of devices’ safe operating region, whereas excessive down-scaling SUP may cause the devices to exit the usual saturation region, degrading the gain of the amplification stages and finally heavily affecting the settling precision, as well as other OTA functionalities based on feedback action (e.g., bandwidth and/or slew-rate-enhancing). The two design points determining the total width of the dispersion band have been marked with APA-style labels: “Gagliardi2023” [22] and “Naderi2018” [23]. For the latter, we have the following specifications: $\mathtt{SUP}=1.1\mathrm{V}$ and $\mathtt{DVS}=62.5\mathrm{mV}$ ($\alpha =56.82\times {10}^{-3}$). For “Gagliardi2023”, $\mathtt{SUP}=3.3\mathrm{V}$ and $\mathtt{DVS}=2.64\mathrm{V}$ ($\alpha =0.8$). Consequently, $min\left(s_{N,T}\right)=0.06875{\mathrm{V}}^2$ and $max\left(s_{N,T}\right)=8.712{\mathrm{V}}^2$.
• The FOML–FOMN plot in Figure 7b follows a similar trend as that of Figure 7a. In [6], it has been demonstrated that, if the asymptotic condition of settling time dominated by slew-rate settling holds, then the following simple relationship can be considered:

  $$\mathrm{FOMN}\approx k{\displaystyle \frac{I_{omax}}{I_{DD}}},$$

  (11)

  where $I_{omax}$ is the maximum output current of the OTA and k is a constant related to the capacitive feedback network. On the other hand, since $\mathrm{SR}=I_{omax}/\mathtt{CLE}$, we can relate Equations (2) and (11) to find the following:

  $$s_{N,L}={\displaystyle \frac{\mathrm{FOMN}}{\mathrm{FOML}}}\approx k\mathtt{SUP}.$$

  (12)
  Both k and SUP are specific to each design point. Hence, a band-like dispersion similar to that in Figure 7a is observed. In this case, the band dispersion is determined by the “Hong2016” [27] and the “Gagliardi2023” [22] designs. The observed maximum and minimum values of $s_{N,L}$ are $3.17\times {10}^{-5}$ V and $2.47\times {10}^{-3}$ V, respectively.

  Figure 7. Annotated scatter plots for FoM interdependence analysis: Dots represent design entries in the dataset, while areas determined by dotted lines are meant to group and/or cluster design points with similar characteristics. (a) FOMT–FOMN plot; (b) FOML–FOMN plot; (c) FOMS–FOMN plot; (d) FOML–FOMS plot. The following references have been indicated in the plots: Gagliardi2023 [22], Naderi2018 [23], Gagliardi2024 [24], Hong2016 [27], Lopez2005 [28], Galan2007 [29], Lee2005 [30].

  Figure 7. Annotated scatter plots for FoM interdependence analysis: Dots represent design entries in the dataset, while areas determined by dotted lines are meant to group and/or cluster design points with similar characteristics. (a) FOMT–FOMN plot; (b) FOML–FOMN plot; (c) FOMS–FOMN plot; (d) FOML–FOMS plot. The following references have been indicated in the plots: Gagliardi2023 [22], Naderi2018 [23], Gagliardi2024 [24], Hong2016 [27], Lopez2005 [28], Galan2007 [29], Lee2005 [30].
• A different behavior is observed in the FOMS–FOMN plot of Figure 7c, where subgroups A and B have been encircled for easier visual identification. These groups demonstrate the existence of sub-optimal designs in terms of bandwidth (UGF), which, however, are marked by high FOMN scores due to more efficient large-signal characteristics, such as input range and slew rate. Depending on the intended application, it may be reasonable to opt for such OTA solutions, but it should be considered that enhanced large-signal performance is achieved at the expense of small-signal characteristics. This is a typical design situation where a low-power operation is achieved by reducing the static OTA power consumption and relying on efficient class AB operation, which temporarily and on demand increases the instantaneous current in the OTA internal branches [31]. Designs labeled “Lopez2005” [28] and “Galan2007” [29] follow this trend with specific circuit implementations based on Super-Class AB OTAs.
• In the FOML–FOMS plot of Figure 7d, a distinct disposition of the design instances is evident. There is no strong correlation between FOML and FOMS. This plot has been annotated with a square to highlight the partial orthogonality of FOML with respect to FOMS, exhibiting complementary characteristics as for what concerns small-signal and large-signal behaviors. This aspect is intriguing as it challenges the generally accepted rule of thumb that unequivocally correlates slew rate to unity-gain bandwidth for basic OTA topologies [32], and it helps identifying optimal solutions for different application cases (e.g., standard-voltage vs. low-voltage contexts [33]). This consideration could potentially stimulate the creation of new OTA topologies with the aim of combining different characteristics for enhanced performance as for both small-signal and large-signal features.

5. Conclusions

This work offers the following contributions.

• Dataset Development: The creation of a collaborative and open dataset for the classification of OTAs represents a significant contribution to the field of analog and mixed-signal integrated circuit design. This dataset provides researchers with access to a comprehensive collection of OTA designs, facilitating benchmarking, analysis and innovation in OTA design methodologies.
• Evaluation Methodologies: The article discusses various evaluation methodologies, including the use of FoMs to assess OTA performances across different operating conditions and specifications. These methodologies enable researchers to systematically analyze and compare OTA designs, yielding a clearer picture of the state of the art and leading to insights into design trade-offs and performance optimization alternatives.
• Interdependence of FoMs: The study highlights the interdependence of FoMs and related implications for OTA design. Transitioning to a unified FoM, such as FOMN, offers advantages in terms of performance classification and correlation between performances and circuit architecture categories. Additionally, the proposed analysis reveals intriguing behaviors and correlations among FoMs, providing insights into design considerations.
• Open Access and Collaboration: By making the dataset openly available on platforms such as GitHub, the article promotes collaboration and knowledge sharing within the research community. This open access approach fosters transparency, reproducibility and innovation in OTA design research.