Simulations and Experiments on Activation of Doped Silicon Wafers Based on Dual Beam of 785 nm Semiconductor Laser and 10.6 μm CO₂ Laser

Abstract

In this study, we analyzed the spatiotemporal distribution of annealing temperature using a dual-beam dynamic scanning annealing technique based on a CO₂ laser (10.6 μm) and a 785 nm laser, and the effects of laser energy density, scanning speed, and preheating temperature on the resulting temperature. We systematically examined the influence of key process parameters, including laser energy density, scanning speed, and preheating temperature, on the annealing temperature. Our aim was to optimize annealing conditions to enhance the electrical properties of the materials, as indicated by reduced sheet resistance, controlled diffusion depth of doped ions, and higher activation rates. This approach ensured high activation rates of doped ions while limiting dopant re-diffusion to merely 3.6 nm in the depth direction, as confirmed by concentration profile analysis. Furthermore, based on temperature distribution, deformation of the wafer surface was analyzed. The results indicate that under the employed process parameters, no significant adverse effects on wafer flatness or structural integrity were observed.

1. Introduction

With the optimization of semiconductor manufacturing processes, the size of semiconductor devices continues to shrink, leading to a reduction in junction depth within components. As semiconductor manufacturing nodes advance toward 5 nm and below, the depth control of Ultra-Shallow Junctions (USJ) has become one of the critical factors limiting the improvement of device performance [1,2,3]. According to the requirements of the International Technology Roadmap for Semiconductors (ITRS), the junction depth of source/drain extension regions in advanced processes needs to be controlled within the range of 10–20 nm while maintaining a dopant activation rate exceeding 95% [4]. The annealing process is a key step in controlling dopant activation. Generally, the activation level of dopants is significantly influenced by annealing time and temperature [2]. However, the annealing process inevitably causes dopant diffusion, and exceeding the designed junction depth can lead to a surge in leakage current, the formation of short-channel effects, and an increase in contact resistance [5,6,7]. This technical requirement poses a significant challenge to traditional thermal annealing processes: conventional Rapid Thermal Processing (RTP) typically has an annealing time of several tens of seconds and is widely used in power devices such as SiC/GaN for high-concentration dopant activation [7,8]. However, due to its high thermal budget, it results in significant impurity diffusion effects [9], and the thermal penetration effect in the deeper layers of the device limits the further formation of USJ [10,11,12]. The annealing time of RTP was reduced to the limit of one second in 2000, forming spike annealing, which significantly reduced the thermal budget but still could not meet the process requirements for nanoscale nodes in advanced logic devices (<14 nm) [13]. In silicon-based logic devices, the prolonged annealing time of RTP results in dopant diffusion exceeding 15 nanometers, violating the junction depth constraints for technology nodes below 14 nm [9,10]. Although RTP remains applicable to wide-bandgap semiconductors (SiC and GaN), its inability to control thermal budget renders it unsuitable for advanced CMOS integration. To reduce the thermal budget and control dopant diffusion depth, the annealing time for advanced logic devices has entered the millisecond range. Millisecond annealing (MSA) technologies, such as flash lamp annealing (FLA) and laser thermal annealing (LTA), have been developed [14].

MSA technology offers the distinct advantage of completing the entire annealing process within 1–20 milliseconds, during which only the shallow surface layer of the wafer (<100 nm) is heated to the required annealing temperature (1270–1670 K) [15]. This ultra-shallow annealing depth allows excess heat to be rapidly dissipated into the environment and annealing boundaries (thermal diffusion time constant approximately 100–1000 ns) [16], thereby limiting substrate temperature rise to below 50 K. This characteristic achieves both a >99% dopant activation rate and confines junction depth diffusion to within 10 nm [17]. John Foggiato et al. employed RTP-assisted FLA technology to complete 1600 K annealing on the surface of arsenic-implanted silicon wafers (dose 1 × 10¹⁵ cm⁻²) within 2 ms, successfully fabricating ultra-shallow junctions with a depth of 28 nm. Compared to devices processed with conventional RTP techniques, results showed a reduction in sheet resistance from 450 Ω/sq to 220 Ω/sq. The results demonstrate that FLA reduces the diffusion effect at the junction depth by approximately 75% compared to conventional RTP, while achieving high dopant activation [18]. Although FLA has achieved success in fabricating 28 nm ultra-shallow junctions, its scalability to sub-10 nm nodes is limited by pattern-induced temperature non-uniformity and insufficient thermal budget control; as semiconductor device sizes shrink and the need for varying degrees of annealing in different regions arises, FLA can no longer meet the requirements when reaching the nanometer scale [19].

Against this backdrop, LTA technology has garnered widespread attention due to its unique advantages [20]. Unlike FLA’s method of heating the entire surface, laser annealing achieves selective heating by spatially shaping the light source to enable precise localized energy irradiation [15,21,22], offering several distinctive features: (1) the processing time of 0.1–10 ms can control the re-diffusion length of impurity ions within 10 nm [23]; (2) the annealing region with a spatial resolution of <5 μm enables selective localized annealing in micro-regions for specific device structures [24]; and (3) independent adjustment of laser energy density and pulse-modulated annealing time allows precise control of junction depth (deviation < ±2 nm) while ensuring high activation rates of doped ions. These characteristics make laser annealing the preferred solution for ultra-shallow junction fabrication at 28 nm and below technology nodes. H.T. Wang et al. [25] investigated the effects of combining 248 nm excimer laser annealing with RTP (energy density 0.2 J/cm², repetition frequency 1 Hz, pulse width 25 ns) on the material properties of beryllium-implanted GaN (dose 5 × 10¹⁴ cm⁻²). They found that conventional RTP alone could no longer achieve p-type conversion of Be-implanted GaN films. However, after pulsed laser annealing (PLA) treatment, a hole concentration of 7.79 × 10¹² cm⁻² was achieved, representing a 28.2-fold increase in carrier concentration compared to the original sample’s electron concentration of 2.67 × 10¹¹ cm⁻². The sheet resistance decreased from 6.51 × 10⁵ Ω/sq to 8.38 × 10⁴ Ω/sq, a reduction of 87.12%. Atomic force microscopy observations showed that LTA reduced the root mean square (RMS) surface roughness from 1.678 nm to 0.516 nm (a 70.5% reduction), which is highly beneficial for interface quality control in subsequent device fabrication.

Although single-beam annealing technology has achieved millisecond-level annealing processes, it still faces technical bottlenecks in certain aspects: firstly, the shallow penetration characteristics (approximately 100 nm) of short-wavelength lasers such as 248 nm KrF excimer lasers in silicon materials lead to significant pattern effects, resulting in temperature non-uniformity as high as 15% in dense pattern areas, which affects device performance consistency [26]; secondly, the steep temperature gradient caused by instantaneous energy deposition is prone to induce lattice slip defects, leading to wafer warpage. To address these technical challenges, the dual-beam laser spike annealing (DB-LSA) technology has made improvements in practical applications [27,28,29]. The technology first adopts a low-energy-density laser beam to preheat the wafer to a medium temperature range of 670–900 K, and then completes the annealing process through the intervention of a second high-energy-density laser beam. Yun Wang et al. [30] found in comparative experiments with traditional single-beam laser spike annealing (LSA) that adding a preheating beam to the conventional CO₂ laser beam used in LSA could reduce thermal stress by lowering the thermal gradient, thereby achieving higher annealing temperatures without generating slip lines. Experiments have shown that the spatiotemporal distribution of annealing temperature is a key factor reflecting the activation level of doped ions and the effectiveness of junction depth control, making it necessary to reasonably predict the annealing temperature distribution during the LTA process.

Existing research primarily focuses on static annealing modes, analyzing the temperature field distribution under fixed laser irradiation positions and limited processing time conditions [31,32,33]. However, such simplified models struggle to accurately reflect the dynamic thermal effects during actual scanning annealing processes [34]. Based on this, this study combines experimental validation, using a CO₂ laser as the primary annealing light source, with Brewster angle incidence to mitigate pattern effects during the annealing process [10]. Additionally, it innovatively introduces a 785 nm wavelength laser as a preheating beam in the DB-LSA process. This selection is grounded in the following theoretical analysis and experimental findings: (1) Optimization of preheating beam penetration depth and absorption effect: the optical penetration depth of 785 nm laser in silicon is (10.2 ± 1.5) μm [35], which allows the wafer to effectively absorb energy and be heated while avoiding the risk of amorphization caused by surface overheating (surface temperature gradient < 50 K/μm). (2) Wavelength synergy effect: By working in conjunction with the main annealing 10.6 μm CO₂ laser, the absorption efficiency of silicon for the CO₂ laser is enhanced based on the free carrier absorption mechanism [36,37]. Experimental verification shows that at normal room temperature (300 K), the absorption efficiency can be increased from 15% to a maximum of 85.6%. (3) Thermal stress suppression: The temperature field (600–900 K) generated by preheating can reduce the transverse thermal gradient in the annealing zone from ~10⁵ K/m in conventional single-beam processes to (2.5 ± 0.3) × 10⁴ K/m, corresponding to an approximately 75% reduction in thermal stress [33]. This will significantly improve the deformation of the wafer surface during the annealing process.

Through multi-physics coupled simulation (COMSOL 6.2) and ion diffusion characterization, it was verified that this dual-wavelength cooperative annealing method achieves an impurity activation rate of (92.3 ± 1.8)% within a processing time of 0.55–1.2 ms, while limiting junction depth redistribution to 3.6 nm. This dynamic regulation approach provides a novel strategy for ultra-shallow junction fabrication at 5 nm and below technology nodes, particularly suitable for selective area annealing in 3D integrated devices. This study integrates multiphysics simulation with experimental validation using a dual-beam laser annealing platform. Through sheet resistance measurements and junction depth analysis, the simulated temperature fields and dopant diffusion profiles were experimentally verified, thereby establishing a collaborative simulation-validation framework.

2. Theory and Model

2.1. Theoretical Principles

The physical essence of wafer annealing using CO₂ lasers mainly lies in the photothermal energy conversion process between laser energy and the material [38]. The core mechanism is that the laser energy is selectively absorbed by the silicon lattice mixed with doped ions, and the lattice defects caused by ion implantation are repaired during the material heating process, thereby improving its electrical properties. In this process, multi-physical field interactions are designed: laser energy heats the material in the form of surface heat flow, relying on the thermal conductivity k(T) of temperature to regulate heat conduction in the depth direction, while forming a dynamic balance with surface thermal radiation and atmospheric convective heat transfer coefficient. At the microscopic scale, when the local area of annealing approaches the melting point of silicon (1684 K), atoms gain sufficient activation energy to achieve lattice reconstruction, enabling the non-equilibrium defect states caused by ion implantation to be ordered. This structural change will directly manifest as a decrease in thin-layer resistance and an increase in carrier activation mobility [39].

2.2. Selection of Computational Domain and Parameter Settings

In the simulation, precise control of beam parameters is achieved, including spot size, incident power density, spatial energy distribution, and temporal waveform (pulse/continuous modulation). To reduce computational load, the selection of the computational domain is based on heat-affected zone analysis, when the temperature gradient at the periphery of the annealing zone decays to the ambient temperature (300 K). This area can be considered as the periphery, being in a quasi-steady thermal state, effectively approximating an adiabatic boundary. At this point, the boundary heat flux density is below 1.0 W/m³, satisfying the adiabatic boundary condition assumption, thereby significantly reducing model degrees of freedom and computation time.

For the requirement of ultra-shallow junction activation, a non-uniform mesh refinement strategy is employed in the simulation. In the depth direction, the ion implantation layer (≤2 μm) serves as the core region, where adaptive mesh refinement captures temperature gradients with an element size of 1.0 nm. The wafer surface that directly absorbs the heat source undergoes refinement treatment in the scanning area, as shown in Figure 1, and the lateral range dynamically adjusts mesh density based on the thermal diffusion length to balance computational efficiency and accuracy. During the annealing process, the temperature within the annealing zone undergoes significant variations, leading to substantial jumps in corresponding thermophysical properties. Therefore, a nonlinear interpolation model is adopted for the thermal conductivity (k(T)) of the silicon wafer in the modeling process to avoid numerical instability caused by phase transitions. This model is implemented through COMSOL’s Material Property Functions module, achieving a 95.0% agreement (R² = 0.95) with experimental data.

2.3. Model Establishment and Simulation Analysis

2.3.1. Physical Process

In order to make the simulation data reproduce the experimental results as much as possible, some scientific parameter settings and assumptions are made during the model establishment process:

The initial material properties of silicon wafers are isotropic. As the temperature rises, the thermal conductivity of silicon decreases, which inhibits the diffusion and conduction of heat to the surrounding areas, making it easier for energy to accumulate in the irradiated region. As the annealing temperature is strictly limited below the melting point (1684 K), the solid-phase properties of the material remain unchanged. Therefore, the influence of temperature on the coefficient of thermal expansion, density, and the coefficient of thermal convection heat transfer with the atmosphere is ignored. The influence of the laser incident angle on the material absorption effect is simulated by regulating the laser energy absorption coefficient.

Compared with shorter-wavelength lasers, the CO₂ laser has a longer wavelength and lower photon energy. The resulting absorption mechanism in silicon can mitigate the pattern effects that occur during the annealing process. This is primarily due to the reduced diffraction effects and deeper penetration of the longer wavelength. Additionally, it enables a relatively uniform temperature distribution in the shallow surface region of the wafer during annealing, which helps control temperature variations and ensures consistent annealing outcomes across the wafer surface. Therefore, the CO₂ laser is regarded as an ideal light source for wafer annealing. In this study, the laser wavelength used for annealing is 10.6 μm. CO₂ laser–silicon interaction mainly involves free carrier absorption, transferring photon energy to conduction band electrons. This absorption depends heavily on free carrier concentration, adjustable via doping and thermal pre-treatment. Therefore, the simulation adopted a dual-beam annealing mechanism, using a 785 nm wavelength light source for preheating and then applying a CO₂ laser for annealing treatment.

Figure 2a demonstrates the physical processes that occur during annealing. Under laser irradiation, silicon materials convert photon energy into lattice thermal energy through mechanisms such as intrinsic absorption and free carrier absorption. This leads to the formation of a non-uniform temperature field within the material via thermal conduction. The transient distribution of this temperature field is simultaneously influenced by surface thermal radiation and convective heat exchange with the surrounding environment. As shown in Figure 2b, after the laser energy is absorbed in the “annealing zone” on the surface, the heat spreads laterally across the silicon wafer’s surface through thermal conduction, forming a “heat-affected zone,” while also transferring vertically into the wafer to control the junction depth. Simultaneously, surface heat dissipates into the surrounding environment through radiation and convection.

2.3.2. Thermal Control Equation

When the laser irradiates the silicon wafer, a portion of the energy is absorbed, and the absorbed laser intensity varies both spatially and temporally within the material. The governing partial differential equation for temperature distribution is:

$$\rho C_p{\displaystyle \frac{\partial T}{\partial t}}+\nabla \cdot \left(q\right)=Q_{x,y,z}+Q_{ted}$$

(1)

where ρ is the density (kg/cm³), $C_p$ is the specific heat capacity (J/kg⋅K), and the $\nabla \cdot \left(q\right)$ is the divergence of the heat flux q, reflecting the process of heat diffusion in space. $Q_{x,y,z}+Q_{ted}$ is the heat source term. The $Q_{ted}$ represents the hot electron dissipation term, a process primarily arising from carrier–phonon interactions, particularly evident in the high-concentration doping regions near the wafer surface. $Q_{x,y,z}$ denotes the laser heat source term. According to the Beer–Lambert law, the $Q_{x,y,z}$ is given by:

$$Q_{x,y,z}={\alpha Pe}^{-\alpha \left(T\right)z}$$

(2)

where $\alpha$ is the absorption coefficient (mm⁻¹), which varies with temperature; P is the incident laser power density at the surface (W/m²); this expression demonstrates how the material’s absorption of laser energy changes with depth. According to Fourier’s law of heat conduction, the heat flux q is expressed as:

$$q=-k\left(T\right)\nabla T$$

(3)

The $k\left(T\right)$ represents the thermal conductivity of silicon (W/cm·K), which varies nonlinearly with temperature. This parameter plays a crucial role in the wafer annealing process and is redefined in the model using an interpolation function. The thermal conductivity values on silicon surfaces at different temperatures used in this study were obtained from the literature [11], with smooth transitions applied to the interval sections, as shown in

Table 1. Thermal conductivity of silicon.

Temperature (K)	$\mathit{k}\left(\mathit{T}\right)$ (W/cm·K)
300	1.422
400	0.974
500	0.692
600	0.577
700	0.483
800	0.400
900	0.337
1000	0.298
1100	0.290
1200	0.289
1300	0.288
1400	0.287

.

To ensure the temperature uniformity in the annealing zone, this study employs a flat-top beam as the light source model, with its spatial energy distribution homogenized. Simulation results demonstrate that this light source model eliminates the edge attenuation effect of Gaussian beams, reducing the temperature field simulation error to within 1.2%.

Figure 2b also illustrates the form of boundary conditions. To accurately solve the heat transfer equation, reasonable boundary conditions are defined based on practical circumstances, including convective heat transfer between the upper surface and the air medium, as well as energy loss due to radiative heat transfer to the air.

Other physical quantities employed in the simulation are listed in

Table 2. Optical and thermo-physical properties of silicon.

Parameters	Value	Reference
Cp (J/g·K)	0.695 × exp(2.375 × 10−4 Tx,y,z)	[35]
p (g/cm2)	2.3	[35]
R	0.25 for λ = 10.6 μm	[35]

.

2.3.3. Laser Scanning Motion and Model Boundaries

Since the research objective of the simulation is to study the variation in surface annealing temperature during dynamic scanning, it is also necessary to configure a reciprocating scanning motion for the laser source. This step is accomplished by setting a periodic trigonometric function for the x-coordinate of the heat source center, denoted as x. The function is configured as follows:

$$\mathrm{T}\mathrm{r}(x)=\{\begin{array}{cc}2x& 0\le x<0.5\\ 2\left(1-x\right)& 0.5\le x<1\end{array}$$

(4)

The $Tr\left(x\right)$ represents a function with the independent variable x. The waveform exhibits a symmetrical sawtooth shape with a period of 1 and an amplitude in the range of [0, 1]. The central coordinate $x\left(t\right)$ of the heat source is coupled with the shadow t in the function:

$$x\left(t\right)=A\cdot Tr\left({\displaystyle \frac{t}{P_e}}\right)$$

(5)

A is the scanning amplitude, which is the maximum displacement of the heat source center, set according to the wafer size. For example, in this simulation, a 2-inch wafer is used, and here, A is set to 5.08 cm; $P_e$ is the duration of a movement cycle, controlling the speed v of the heat source by adjusting the cycle length.

The boundary simplification condition adopted in this study neglects edge effects, with the model boundary set beyond the isothermal layer where the temperature drops to room temperature (300 K) during the annealing process, as illustrated in Figure 3.

2.3.4. Modeling of the Material Absorption Coefficient

According to Green et al. [40], the 785 nm laser exhibits significant optical absorption characteristics in silicon, with an absorption coefficient as high as 8.2 × 10³ cm⁻¹, corresponding to a penetration depth of only about 12.2 μm. This strong absorption characteristic stems from the enhanced direct bandgap transition of silicon at this wavelength, resulting in approximately 80.0% of the incident laser energy being absorbed within the surface 10 μm range. Experimental measurements show that when the doping concentration exceeds 1 × 10¹⁸ cm⁻³, free carrier absorption further increases the effective absorption coefficient by 10–20% [41]. Therefore, in this study, 92.5% of the incident energy of the 785 nm laser will be considered as absorbed, while the energy conversion process of the 10.6 μm laser in the silicon wafer excites a mechanism known as free carrier absorption, where the absorption rate of the laser by the silicon wafer increases with the concentration of free carriers. Since the free carrier concentration significantly depends on temperature, to enhance the wafer’s absorption of the CO₂ laser, preheating before ion doping and annealing can be implemented. The laser energy absorption coefficient α (N, T_x,y,z) of silicon for the CO₂ laser, which depends on both dopant concentration and temperature, is expressed as:

$$\alpha (N,T_{x,y,z})=1.9\times {10}^{-20}(T_{x,y,z}{)}^{{\displaystyle \frac{3}{2}}}\times [N+n_i\left(T_{x,y,z}\right)]+{\alpha }_0$$

(6)

The N is the dopant concentration (cm⁻³), T_x,y,z is the temperature in the annealed area of the wafer in K, n_i(T_x,y,z) is the temperature-dependent intrinsic carrier concentration (cm⁻³), and ${\alpha }_0$. is the lattice absorption coefficient. The temperature dependence of intrinsic carrier concentration in silicon follows the relationship:

$$n_i\left(T_{x,y,z}\right)=3.87\times {10}^{16}{\left({\displaystyle \frac{T_{x,y,z}}{300}}\right)}^{{\displaystyle \frac{3}{2}}}\exp {\displaystyle \frac{-7020}{T_{x,y,z}}}{\mathrm{c}\mathrm{m}}^{-3}$$

(7)

This equation accounts for the thermal excitation of charge carriers across the semiconductor bandgap. In the simulation, it is assumed that the doped ion injected into the silicon wafer is phosphorus, and the injection dose is set as 1 × 10¹⁵ atoms/cm⁻². The process of laser energy absorption mechanisms in silicon and the influencing factors of the temperature field are shown in Figure 4:

2.3.5. Dopant Concentration Profile

During the annealing process, the dopant ions are activated, enhancing the electrical properties of the material. However, under the influence of temperature, these ions also diffuse into the surrounding areas of the wafer. Excessive diffusion in the junction region can lead to short-channel effects, significantly increasing leakage current. Therefore, this study analyzes the diffusion effects of ions based on the spatiotemporal distribution of annealing temperature. In the simulation, phosphorus was set as the dopant, with an implantation energy of 20 keV and a dose of 1 × 10¹⁵ cm⁻². Initially, according to the work of Gibbons et al. [42], the ion concentration distribution equation of the untreated initial sample can be expressed as:

$$N\left(l\right)={\displaystyle \frac{0.4Q}{\mathsf{\Delta }{R}_P}}\exp \left(-{\displaystyle \frac{(l-R_P{)}^2}{2\left({\mathsf{\Delta }{R}_P}^2\right)}}\right)$$

(8)

Here, N(l) represents the dopant concentration at depth l (nm), and Q is the total dopant dose (cm⁻²). R_P denotes the projected range of the implanted dopant, and ΔR_P is the standard deviation within the projected range.

Since ion implantation is performed across the entire surface region and the junction depth affecting electrical properties is in the depth direction, our primary focus is on the vertical diffusion of ions. In a one-dimensional scenario, the redistribution of implanted ions during annealing can be described by Fick’s diffusion equation:

$${\displaystyle \frac{\partial N\left(l,t\right)}{\partial t}}=D{\displaystyle \frac{{\partial }^{2}N\left(l,t\right)}{\partial l^2}}$$

(9)

Here, N (x, t) represents the concentration of the dopant at depth l (nm) and annealing time t (ms), and D is the diffusion coefficient of the dopant (cm²/s), whose magnitude directly characterizes the speed of particle diffusion. Extensive experiments have demonstrated that the diffusion coefficient D follows an exponential relationship with temperature T (K) as follows:

$$D=D_0\exp \left({\displaystyle \frac{-E_a}{k_{B}T}}\right)$$

(10)

Here, D₀ is the apparent diffusion coefficient (1.44 cm²/s), E_a is the diffusion activation energy (2.69 eV), and k_B is the Boltzmann constant (8.617 × 10⁻⁵ eV/K). T, here, takes the annealing temperature value obtained from this simulation.

In the annealed sample, the concentration distribution of doped ions should be the convolution result of the initial distribution and the diffusion equation, which can be expressed through the Gaussian diffusion correction model as:

$$N\left(x,t\right)={\displaystyle \frac{Q}{\sqrt{2\pi \left({\mathsf{\Delta }{R}_P}^2+2\mathrm{D}t\right)}}}\exp \left(-{\displaystyle \frac{(x-R_P{)}^2}{2\left({\mathsf{\Delta }{R}_P}^2+2\mathrm{D}t\right)}}\right)$$

(11)

In simulations, it was found that most previous studies on calculating doping concentrations simply multiplied the term Dt directly. However, in fact, the diffusion coefficient D undergoes nonlinear changes with annealing temperature during the annealing dwell time and thus cannot be treated as a constant directly multiplied by the annealing time t as an additional term for diffusion width. Therefore, this study integrates this term:

$$Dt={\int }_0^t D\left(t^{\prime }\right)d{t}^{\prime }$$

(12)

Based on the work of Gibbons et al., this study sets R_P at 13.8 nm, ΔR_P at 5.42 nm, and annealing time at 1 ms. The diffusion of dopant ions was analyzed according to the simulated annealing temperature distribution.

2.3.6. Thermal Stress Deformation

In advanced semiconductor manufacturing, wafer flatness is also a critical parameter that determines device performance and yield. One important step in the entire chip fabrication process that significantly impacts flatness is the annealing of wafers. The thermal stress caused by temperature changes during annealing can lead to wafer deformation. Based on this, a mechanical module is incorporated into the simulation, and the governing equations can be expressed as [43]:

$$\nabla \cdot \left[C:\left(\nabla \mathrm{u}-\alpha \mathsf{\Delta }T\mathrm{I}\right)\right]+\rho \mathrm{g}=0$$

(13)

The displacement control term $\nabla \mathrm{u}$ is used to describe the spatial variation rate of the displacement field. The thermal strain term $\alpha \mathsf{\Delta }T\mathrm{I}$ is composed of the expansion coefficient $\alpha$, the temperature change $\mathsf{\Delta }T$, and I as the tensor unit, indicating that thermal expansion is an isotropic volumetric strain. Together with the elastic tensor C, it forms the stress tensor $S=C:\left(\nabla \mathrm{u}-\alpha \mathsf{\Delta }T\mathrm{I}\right)$, reflecting the material’s ability to resist deformation internally; g = 9.8 m/s² is the gravitational acceleration. In the unbounded free thermal simulation process, it was found that the thermal deformation data at 1.5 mm from the annealing zone had already decreased to zero. Therefore, considering the chuck setup of the experimental apparatus, the sidewalls around the wafer were designated as the mechanical constraint layer, while the boundary constraints of the annealing scan zone were set at 5 mm from the sidewalls to avoid the influence of fixed positions on the simulation results. Subsequently, the deformation magnitude in the z-direction of the wafer within the annealing zone was observed.

2.4. Experimental Equipment and Annealing Effect Characterization Methods

Figure 5 shows a schematic diagram of the dual-beam laser wafer annealing experimental setup used in the experiment, which consists of two parts in its system architecture.

1. Dual-beam heat source system: Divided into the preheating system and the main annealing system. The preheating system employs a 785 nm semiconductor laser, shaped into a rectangular spot of 11.0 mm × 0.35 mm using cylindrical lenses, to establish a gradient temperature field before annealing, thereby improving the subsequent CO₂ laser absorption efficiency. The main annealing system utilizes a 10.6 μm CO₂ laser source with a maximum output power of 405.9 W [44]. The laser operates with a root mean square fluctuation of 0.3% within one hour at maximum output power, meeting the experimental requirements. After shaping through a Fresnel lens and cylindrical lens group, the spot is adjusted to a 3.5 mm × 0.1 mm rectangular flat-top homogenized beam. During the experiments, the energy distribution within the central 3.0 mm range along the length direction was measured, as shown in Figure 6. The results indicate a power density non-uniformity of ≤5%, ensuring precise control of peak temperature during the annealing process.

2. Motion Control System: This experiment employs a high-precision two-dimensional motion platform to achieve laser dynamic scanning annealing. The wafer is fixed on a chuck supported by guide rails and driven by linear motors for nanometer-level precise positioning. The motion system is built on a marble base (flatness ≤ 0.01 mm/m²), utilizing real-time position feedback from grating scales and PID closed-loop control to achieve ±1 μm repeat positioning accuracy. Practical measurements confirm that during scanning, even at an acceleration of 2 m/s², the trajectory tracking accuracy remains within ±0.5 μm, providing a reliable experimental foundation for studying the effects of different scanning paths and trajectory speeds on annealing uniformity.

This experiment employs a high-precision infrared pyrometer for real-time temperature monitoring of the laser annealing zone. The pyrometer operates within a wavelength range of 0.7–1.1 μm with a response time of less than 100 μs. Its primary functions include verifying the accuracy of multiphysics simulation model results and quantifying the temperature stability of the annealing zone. As shown in Figure 7a, the pyrometer’s effective measurement radius is 0.3 mm, which exceeds the linear width of the annealing spot. This may introduce radiation interference from non-target areas (outside the annealing spot) into the temperature signal. To address this issue, this study developed a dynamic temperature compensation algorithm based on a pre-established static annealing model. The algorithm utilizes a high-precision temperature compensation mechanism grounded in multispectral radiation principles. It collects full-spectrum thermal radiation signals from the target area in real time and establishes a wavelength–temperature correlation model based on Planck’s radiation law. By dynamically weighting radiation within the detection wavelength range and applying the Stefan–Boltzmann equation, it achieves precise inversion of radiation energy to temperature values. Data analysis, as illustrated in Figure 7b, shows that this mechanism achieves a temperature resolution of ±1.5 K and a μs-level response speed within the operational range. The linear correlation coefficient between the compensated equivalent temperature (T_equ) and the actual annealing temperature (T_max) reaches 99.8%, meeting process control requirements.

3. Results and Discussion

3.1. Validation of Simulation Results

The CO₂ laser is incident on the wafer to be annealed at the Brewster angle (74.3°) through a beam shaping system, with the P-polarized direction adjusted to reduce the reflection component, thereby providing energy for the annealing process. The optical path of the retroreflective beam is shown in Figure 8. In the experiment, the preheating laser is incident normally on the wafer surface, focused into a line spot of 11.0 mm × 3.5 mm, with the annealing spot located at its center to ensure uniform preheating temperature distribution.

In the simulation, a preheating laser power density of 136.4 W/mm², a CO₂ laser power density of 52.5 kW/cm², and an annealing dwell time of 1 ms were used to simulate the experimental annealing process. As shown in Figure 9, the resulting maximum temperature in the annealing zone matched the highest temperature measured by the pyrometer in the experiment, thereby validating the simulation results.

3.2. Influence of Process Parameters on Annealing Temperature Distribution

Based on the thermal interaction process between the light source and the silicon wafer, we analyzed and discussed the influence of process parameters, such as laser power density, annealing scan speed, and preheating temperature, on the annealing temperature distributions. Through systematic research on the interaction of these parameters, we established a quantitative relationship model between them and the annealing temperature distribution, providing a theoretical basis for improving wafer annealing processes.

3.2.1. Annealing Laser Power Density

A major influencing factor of the annealing temperature is the power density of the annealing laser. Here, the annealing dwell time is defined as the duration for which the CO₂ main annealing beam remains on a unit length segment of the wafer. When both the annealing dwell time and the preheating beam power density remain constant (preheating laser power density = 136.4 W/mm², dwell time = 1 ms), the preheating temperature is also determined. Under these conditions, variations in the annealing laser power density significantly influence the peak annealing temperature achieved on the wafer surface.

The preheating temperature was set to 820 K in the simulation. Under this condition, there is a positive correlation between the CO₂ laser power density and the maximum annealing temperature: as shown in Figure 10a, when the power density increased from 36.0 kW/cm² to 56.0 kW/cm², the peak annealing temperature rose from approximately 1280 K to 1684 K, verifying the controllable regulation capability of the laser energy input on the temperature field. The annealing temperature within the range of 36.0 to 40.0 kW/cm² will rapidly rise to 1470.8 K as the laser power density increases. The temperature rise rate slows down in the power density range of 40.0–48.0 kW/cm². This is conducive to our control of the annealing temperature, enabling efficient annealing while avoiding overmelting of the material. After 53.0 kW/cm², the temperature rise tends to level off, and the material properties change. As the melting point of silicon is reached, significant changes occur in its surface morphology, density, and thermal conductivity, which is a situation that should be prevented and avoided. Figure 10a simultaneously marks the variation in the isothermal layer depth reaching 1450 K and 1500 K in the longitudinal direction with the annealing power density, indicating that the higher the surface annealing temperature, the deeper the longitudinal activation depth.

Figure 10b shows the variation in the equivalent annealing temperature T_equ with the maximum annealing temperature T_max. When the surface maximum annealing temperature reaches 1665.8 K, the equivalent temperature is 1476.7 K. In multiple simulation experiments, the fluctuation of T_equ is ≤2.5 K, maintaining relatively good stability.

The doping activation rate is quantified by the change in sheet resistance (ΔR_s) measured using a four-point probe system. This electrical evaluation method is widely adopted in advanced node processes. To validate the simulation results, a self-built dual-beam annealing experimental platform was used to anneal a 425 μm thick, 2-inch p-type silicon wafer. The annealing process was conducted at a scanning speed of 100 mm/s and within a laser power density range of 35.0–54.0 kW/cm². The sheet resistance ρ of the samples before and after annealing was measured using a four-point probe resistivity meter, as shown in Figure 11.

In the experiment, a four-point probe resistivity meter was used to measure the sheet resistance, with the probe spacing set at 1.0 mm. Four measurement points were uniformly selected along the scanning direction for each sample (spacing of 3.0 mm) to ensure the statistical reliability of the data. Before the annealing experiment began, the thin-layer resistivity of the wafer to be annealed was measured, which showed infinity. This indicates that after ion doping, many boron ions are in the interlayer positions of silicon atoms, and the number of free carriers is nearly zero. After annealing treatment at a lower energy density, there was no significant change in the thin-layer resistance, indicating that the target annealing temperature was not reached and the activation degree of doped ions was relatively low. At 36.0 kW/cm², the sheet resistance sharply drops to 10.0 kΩ/sq, indicating the onset of activation. When the energy density is further increased, within the range of 36.0 to 44.0 kW/cm², the measured value of the thin-layer resistance begins to show a significant downward trend. At this stage, a large number of doped ions are activated and participate in the conductive process of sheet resistance measurement. When the energy density reaches 44.0 kW/cm², the sheet resistance decreases to 907.5 Ω/sq. The trend chart clearly shows that the subsequent resistivity decline tends to flatten, indicating that the activation process of doped ions is nearing saturation. At 54.0 kW/cm², the sheet resistivity ultimately drops to 125 ± 0.4 Ω/sq, achieving the desired annealing effect.

3.2.2. Beam Scanning Speed

Another variable that needs to be strictly controlled in the laser annealing process is the scanning speed of the beam, which affects the residence time of the laser on the material surface and thereby influences the heat exchange process between the heat source and the material. To observe the influence of the residence time of the annealing laser on the distribution of the maximum annealing temperature T_max, the preheating temperature of the annealing area is set at 850 K in the simulation. The CO₂ laser power is 48.0 kW/cm², and the scanning speed ranges from 80 mm/s to 170 mm/s. The relationship between the maximum annealing temperature and the scanning speed is shown in Figure 12.

The Figure 12a shows the negative correlation between the scanning speed and the peak annealing temperature during the laser annealing process. As the scanning speed gradually increases from 80 mm/s to 170 mm/s, the maximum annealing temperature shows a decreasing trend, dropping from nearly 1660 K to approximately 1450 K. This variation pattern is mainly due to the change in heat input per unit area: a lower scanning speed prolongs the laser’s residence time on the material surface, resulting in a significant energy accumulation effect and thus generating a higher peak temperature. However, during high-speed scanning, the thermal action time is shortened, and energy deposition is reduced, which limits the extent of temperature rise. Moreover, the relationship between the thermal effect duration and the scanning speed is not linear, as shown in the illustration of Figure 12a, but rather inversely proportional. Changes in speed within the low scanning speed range result in relatively minor variations in annealing duration. The temperature gradient is steeper at lower scanning speeds (80–120 mm/s) and becomes more gradual at higher speeds (120–170 mm/s). This feature provides an important reference for the optimization of experimental conditions. In cases where the annealing temperature needs to be precisely controlled (such as 1570–1670 K), a medium scanning speed range of 120–140 mm/s can be selected, which not only ensures sufficient annealing effect but also achieves better stability.

The isothermal layer reaching 1500 K in the longitudinal direction was selected as the effective annealing depth. Figure 12b shows the changing trend of the effective annealing depth as the laser scanning speed increases. When the scanning speed increases, the effective annealing depth decreases accordingly. This is because the laser stays on the wafer surface for a shorter time, and under the same laser power density, the heat transfer time of the light source to the wafer is shortened. The time for energy to conduct into the interior of the wafer is shortened, and more heat will be concentrated on the surface and shallow areas of the wafer. Moreover, a faster scanning speed will increase the material portion available for heat dissipation after the annealing process, making it less likely for heat to conduct into the depth direction.

Figure 13 shows the simulation of the temperature distribution in the internal cross-section of the wafer when 100 mm/s and 130 mm/s are selected; the v in the figure represents the direction of laser movement relative to the wafer. It can be seen from the two-dimensional distribution that when the annealing scanning speed increases from 100 mm/s to 130 mm/s, the depth of the 1500 K isothermal layer decreases from 12.26 μm to 6.47 μm, a relative reduction of 46.4%. When other conditions remain unchanged, the alteration of the annealing scanning speed can significantly reduce the diffusion of the internal thermal effect of the wafer. In combination with the curve of surface temperature varying with scanning speed in Figure 12a, a scanning speed range that not only heats the shallow area to the annealing temperature but also controls the deep diffusion should be selected.

3.2.3. Preheating Temperature

Another factor affecting the absorption efficiency of the CO₂ laser by the wafer is the initial temperature, the preheating temperature before annealing. Based on the simulation model, the influence of preheating temperature on the distribution of the maximum surface annealing temperature is explored.

From the above discussion, different preheated temperatures significantly affect the rate of surface temperature rise during annealing. With the maximum surface annealing temperature fixed at 1660 K, we varied the preheating temperature from 700 K to 900 K to observe the required time and power density to achieve the desired annealing temperature under conditions of controlled laser power density and dwell time. Figure 14a shows the variation curves of the required annealing time to reach the desired annealing temperature.

Under a fixed laser power density (48 kW/cm²), the increase in preheating temperature T_pre significantly reduces the time required to reach the target annealing temperature T_max = 1660 K. Experimental data show that when T_pre rises from 700 K to 900 K, the heating time sharply decreases from 1.094 ms to 0.402 ms, representing a reduction of 63.6%. The nonlinear decreasing trend shown in Figure 14b further indicates that the time gradient (dt/dT_pre) increases with higher preheating temperatures. This physical phenomenon stems from the exponential growth of the silicon lattice’s absorption coefficient for 10.6 μm CO₂ laser radiation as the temperature rises.

However, there is an upper limit constraint on the preheating temperature (T_pre ≤ 950 K), due to the following reasons:

1. Short-wave parasitic absorption: When T_pre is too high, the wafer’s absorption of auxiliary light sources (laser of 785 nm) may cause localized overheating, leading to changes in the wafer’s surface morphology.

2. Process optimization balance: The long-wavelength characteristics of the CO₂ laser (λ = 10.6 μm) can effectively avoid pattern effects. Its penetration depth works synergistically with the temperature gradient formed by preheating, enhancing energy coupling efficiency while maintaining the geometric integrity of the internal structure.

This phenomenon reveals a temperature-dependent photothermal conversion mechanism—preheating reduces the bandgap energy of silicon and increases the concentration of free carriers, thereby enhancing the CO₂ laser’s energy absorption rate by 3–5 times while avoiding the side effects of short-wavelength irradiation.

3.2.4. Dopant Diffusion Extent

To observe the diffusion effects on dopant ions during the activation process, set the preheating temperature to 820 K, with an annealing dwell time of 1 ms. When the annealing power densities are 37.14 kW/cm², 38.03 kW/cm², and 40.16 kW/cm², the surface annealing temperatures reach 1350 K, 1400 K, and 1500 K respectively. The concentration distribution of doped ions was analyzed under these three conditions. Firstly, calculate the relationship between the diffusion coefficient and temperature according to Equation (11), as shown in Figure 14a. Then, substitute it into Equation (12) after time integration to calculate the diffusion concentration of doped ions varying with depth. After comparing with the initial unannealed sample, the results are presented in Figure 15b:

The simulation results indicate that the concentration distribution of dopant ions in the silicon wafer exhibits a Gaussian distribution characteristic with a central offset. By comparing the diffusion behavior at different annealing temperatures, it was found that the changes in ion diffusion concentration distribution were not significant compared to the original sample (FWHM increase < 3.0%, peak concentration decreased by only 3.2%) at the three selected annealing temperatures. Moreover, as the temperature increased, the trend of change became even less pronounced. Taking the junction depth as the distance from the surface to where the dopant concentration drops to 5 × 10⁻¹⁸ at/cm³, the original sample had a junction depth of 46.5 nm, while the maximum junction depth of the annealed samples was 50.1 nm, indicating only a 3.6 nm diffusion, which has minimal impact on the sample. This suggests that the brief dwell time during the annealing process can effectively control the diffusion effect of dopants, and within a relatively wide temperature range, the spatial redistribution of phosphorus dopants is minimally affected.

3.2.5. Thermal Stress Deformation Analysis

To observe whether warping or other issues occur in the wafer during the annealing process, the maximum displacement on the wafer surface is analyzed based on the mechanical module and Equation (13) set in the simulation conditions. The annealing process had previously been simulated with a boundary layer cooling down to room temperature. In this mechanical module, fixed constraints are applied to areas outside the boundary layer to simulate the clamping state in experiments. It is known from physical properties that higher temperatures cause greater thermal stress on wafers, leading to more severe deformation. The annealing temperature was selected within the range of 300–1600 K for simulation, and the surface deformation data are shown in Figure 16.

The simulation-based real-time monitoring reveals that during the complete annealing process, the maximum deformation on the wafer surface exhibits a significant nonlinear temperature dependence. The deformation curve in Figure 16a can be clearly divided into two stages: Between 300 K and 1200 K, the deformation rate reaches 0.22 nm/K, with a total deformation of approximately 0.208 μm, which aligns with the nonlinear increase in silicon’s thermal expansion coefficient within this temperature range. From 1200 K to 1600 K, the deformation rate decreases to 0.05 nm/K, indicating that annealing in the high-temperature region does not cause excessive deformation on the wafer surface. Based on the temperature–deformation relationship, the z-direction displacement data at the peak annealing temperature (1600 K) was extracted and plotted in Figure 16b. It shows that the maximum displacement in the annealing core region is 0.22 ± 0.003 μm, spatially characterized by a flat-top central uniformity of 0.22 μm, with a Gaussian decay towards the periphery, diminishing to 0 μm at 1.30 ± 0.05 mm. Thermodynamic simulations confirm that the von Mises equivalent stress corresponding to this deformation is only (12 ± 3) MPa, far below silicon’s yield strength (7 GPa). Comprehensive analysis verifies that, under a 1 ms annealing dwell time, the maximum mechanical deformation caused by thermal stress is 0.22 ± 0.003 μm, and this deformation fully recovers upon cooling. This characteristic ensures that the physical parameters used in this study have a negligible impact on wafer flatness and structural integrity.

4. Discussion

Traditional short-wavelength lasers are susceptible to pattern effects and shadowing effects due to the shallow penetration depth (~100 nm) in silicon materials, resulting in temperature non-uniformities as high as 15% in dense regions. In contrast, the long-wavelength characteristics of the CO₂ laser employed in this study substantially reduce pattern effects, achieving temperature uniformities of ±2.5 K (1350–1650 K) in annealed regions and ultimately reducing wafer sheet resistance variations to 0.4 Ω/sq.

Within an annealing duration of 0.55–1.20 ms, an impurity activation rate of (92.3 ± 1.8)% was attained based on sheet resistivity changes, while maintaining the maximum junction depth redistribution below 3.6 nm. Compared to the 50 nm diffusion depth characteristic of RTP, our method significantly reduced diffusion depth while achieving lower resistance values of 125 ± 0.4 Ω/sq. This method not only accomplishes dual optimization of diffusion depth and thermal gradients but also effectively mitigates stress and warpage issues in integrated devices. Compared to Donghyeok Choi’s direct single-beam CO₂ laser annealing of silicon wafers [44], which resulted in a 62 nm junction depth diffusion at 1610 K, this method shows significant improvement. The addition of a preheating laser reduces the temperature rise rate during wafer annealing, thereby further minimizing the diffusion behavior of doped ions. These improvements provide substantial support for 3D integration and manufacturing under advanced process nodes.

5. Conclusions

This study systematically investigates the spatiotemporal distribution characteristics of annealing temperature and its influence mechanisms on dopant diffusion and wafer deformation by constructing a transient multi-physics model for dual-beam laser synergistic annealing (DB-LSA) using a 785 nm preheating laser and a 10.6 μm CO₂ main laser. The key findings are as follows: The research reveals that when the CO₂ laser power density exceeds 48 kW/cm², the peak annealing temperature exhibits significant saturation characteristics, with the temperature increase rate subsequently decreasing by approximately 40%. This phenomenon stems from the nonlinear optical absorption properties of silicon at high temperatures. By optimizing the synergistic matching of scanning speed and preheating temperature (700–900 K), the system reduces the heating time by 63% while maintaining the heat-affected zone depth within 18.5 ± 0.5 nm. Furthermore, the 785 nm laser preheating unit, employed for the first time in this study, enhances CO₂ laser absorption efficiency through a dual mechanism: reducing the bandgap excitation energy of the silicon lattice (1.12 eV @ 300 K → 0.98 eV @ 750 K) and increasing free carrier concentration (10¹⁵ → 10¹⁸ cm⁻³). This mechanism provides a theoretical basis for the efficient energy interaction of long-wavelength lasers in silicon materials. Additionally, the phosphorus diffusion concentration profile along the wafer depth indicates that the DB-LSA annealing mechanism not only achieves activation but also effectively suppresses dopant diffusion, which is attributed to its rapid heating mechanism. The issue of wafer warpage due to thermal stress is also discussed, with DB-LSA reducing thermal gradients in the annealed region, resulting in a maximum surface displacement deformation of only 0.22 μm, meeting the substrate flatness requirements for 3D IC stacking. In future work, greater emphasis will be placed on the guiding significance of simulations for experimental parameters, as well as using Secondary Ion Mass Spectrometry (SIMS) to record changes in the internal dopant ion concentration of wafers before and after annealing to validate the model’s effectiveness.