New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

Rangel, José; Anides, Esteban; Vázquez, Eduardo; Sanchez, Giovanny; Avalos, Juan-Gerardo; Duchen, Gonzalo; Toscano, Linda K.

doi:10.3390/math12223472

Open AccessArticle

New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

by

José Rangel

,

Esteban Anides

,

Eduardo Vázquez

,

Giovanny Sanchez

^*

,

Juan-Gerardo Avalos

^*

,

Gonzalo Duchen

and

Linda K. Toscano

Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico

^*

Authors to whom correspondence should be addressed.

Mathematics 2024, 12(22), 3472; https://doi.org/10.3390/math12223472

Submission received: 1 October 2024 / Revised: 5 November 2024 / Accepted: 5 November 2024 / Published: 7 November 2024

(This article belongs to the Special Issue Methods, Analysis and Applications in Computational Neuroscience)

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Abstract

During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches.

Keywords: spiking neural P systems with communication on request; arithmetic circuits; FPGA

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MDPI and ACS Style

Rangel, J.; Anides, E.; Vázquez, E.; Sanchez, G.; Avalos, J.-G.; Duchen, G.; Toscano, L.K. New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA. Mathematics 2024, 12, 3472. https://doi.org/10.3390/math12223472

AMA Style

Rangel J, Anides E, Vázquez E, Sanchez G, Avalos J-G, Duchen G, Toscano LK. New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA. Mathematics. 2024; 12(22):3472. https://doi.org/10.3390/math12223472

Chicago/Turabian Style

Rangel, José, Esteban Anides, Eduardo Vázquez, Giovanny Sanchez, Juan-Gerardo Avalos, Gonzalo Duchen, and Linda K. Toscano. 2024. "New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA" Mathematics 12, no. 22: 3472. https://doi.org/10.3390/math12223472

APA Style

Rangel, J., Anides, E., Vázquez, E., Sanchez, G., Avalos, J.-G., Duchen, G., & Toscano, L. K. (2024). New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA. Mathematics, 12(22), 3472. https://doi.org/10.3390/math12223472

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New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

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