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Rangel J, Anides E, Vázquez E, Sanchez G, Avalos J-G, Duchen G, Toscano LK. New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA. Mathematics. 2024; 12(22):3472. https://doi.org/10.3390/math12223472

Rangel, José, Esteban Anides, Eduardo Vázquez, Giovanny Sanchez, Juan-Gerardo Avalos, Gonzalo Duchen, and Linda K. Toscano. 2024. "New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA" Mathematics 12, no. 22: 3472. https://doi.org/10.3390/math12223472

Rangel, J., Anides, E., Vázquez, E., Sanchez, G., Avalos, J.-G., Duchen, G., & Toscano, L. K. (2024). New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA. Mathematics, 12(22), 3472. https://doi.org/10.3390/math12223472