An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA
Institute of Electronics and Computer Science, 14 Dzerbenes St., LV-1006 Riga, Latvia
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Electronics 2020, 9(12), 2193; https://doi.org/10.3390/electronics9122193
Received: 31 October 2020 / Revised: 8 December 2020 / Accepted: 15 December 2020 / Published: 18 December 2020
(This article belongs to the Special Issue Advanced AI Hardware Designs Based on FPGAs)
Artificial Neural Networks (ANNs) have become an accepted approach for a wide range of challenges. Meanwhile, the advancement of chip manufacturing processes is approaching saturation which calls for new computing solutions. This work presents a novel approach of an FPGA-based accelerator development for fully connected feed-forward neural networks (FFNNs). A specialized tool was developed to facilitate different implementations, which splits FFNN into elementary layers, allocates computational resources and generates high-level C++ description for high-level synthesis (HLS) tools. Various topologies are implemented and benchmarked, and a comparison with related work is provided. The proposed methodology is applied for the implementation of high-throughput virtual sensor.
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MDPI and ACS Style
Novickis, R.; Justs, D.J.; Ozols, K.; Greitāns, M. An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA. Electronics 2020, 9, 2193. https://doi.org/10.3390/electronics9122193
AMA Style
Novickis R, Justs DJ, Ozols K, Greitāns M. An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA. Electronics. 2020; 9(12):2193. https://doi.org/10.3390/electronics9122193
Chicago/Turabian StyleNovickis, Rihards; Justs, Daniels J.; Ozols, Kaspars; Greitāns, Modris. 2020. "An Approach of Feed-Forward Neural Network Throughput-Optimized Implementation in FPGA" Electronics 9, no. 12: 2193. https://doi.org/10.3390/electronics9122193
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