# LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators

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## Abstract

**:**

## 1. Introduction

## 2. Model of the Power Converter

## 3. Available Standard Arithmetics for FPGAs

- Real type: The Real type is a non-synthesizable arithmetic which uses double-precision floating-point. As it uses 64 bits for every signal, its accuracy is good enough for any HIL simulation. However, as it cannot be synthesized into an FPGA, its use is only restricted to software simulation, not achieving real time.
- Fixed-point: Fixed-point simulations achieve optimized models in terms of latency (simulation step) and the use of hardware resources. However, the cost, in terms of design time, of implementing a model with fixed-point arithmetics is quite high, not being reasonable to use it in many cases.
- Synthesizable floating-point: This is a common choice as it is synthesizable while the design effort is reasonably low. However, the resource usage is excessively high in many cases. It can be implemented using the standard Float library included in the standard VHDL2008 [15].

#### 3.1. IEEE-754 Floating-Point Basis

#### 3.2. IEEE-754 Addition, Subtraction and Multiplication

## 4. LOCOFloat: Low-Cost Floating-Point Format

## 5. Experimental Results

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 9.**Accuracy results for all the arithmetics using a simulation step of 40 ns. Percentage error related to the reference model.

**Figure 10.**Accuracy results for all the arithmetics using their corresponding simulation step (20 ns, 30 ns and 40 ns, respectively). Percentage error related to the reference model.

Significand | Point Location | Binary Value | Decimal Value | |
---|---|---|---|---|

${010011001001}_{2}$ (${1225}_{10}$) | ${0000101}_{2}$ (${5}_{10}$) | 0100110.01001 | 38.28125 | |

${1111111011001000}_{2}$ ($-{312}_{10}$) | ${0000111}_{2}$ (${7}_{10}$) | 111111101.1001000 | −2.4375 | |

${011001101001}_{2}$ (${1641}_{10}$) | ${1111010}_{2}$ ($-{6}_{10}$) | 011001101001******. | 105.024 | |

${011111111001}_{2}$ (${2041}_{10}$) | ${0101110}_{2}$ (${46}_{10}$) | 0.00[..]011111111001 | $2.900435\xb7{10}^{-11}$ |

Number Leading with | Action | Explanation | Example | |
---|---|---|---|---|

Before soft-norm | After soft-norm | |||

00 | Left shift | Positive number with | Mantissa: 00001010010 | Mantissa: 00010100100 |

suboptimal notation | Point location: 6 | Point location: 7 | ||

11 | Left shift | Negative number with | Mantissa: 110100101101 | Mantissa: 10100101101 |

suboptimal notation | Point location: 4 | Point location: 5 | ||

Other | Nothing | No overflow risk | Mantissa: 011100110101 | Mantissa: 011100110101 |

possibilities | Point location: 7 | Point location: 7 |

**Table 3.**FPGA (Xilinx XC7Z010-1CLG400C) resources used by the design, and percentage value with respect to the available resources in the FPGA.

System | Min Simulation Step | 6-Input LUTs | FFs | DSPs |
---|---|---|---|---|

LOCOFloat | $38.973$ ns | 2017 | 150 | 8 |

$11.5\%$ | $0.4\%$ | $10\%$ | ||

32-bit Floating-point | $19.778$ ns | 306 | 112 | 12 |

$1.7\%$ | $0.3\%$ | $15\%$ | ||

64-bit Floating-point | $28.178$ ns | 614 | 192 | 50 |

$3.5\%$ | $0.5\%$ | $62.5\%$ | ||

Fixed-Point | $35.339$ ns | 586 | 98 | 7 |

$3.3\%$ | $0.3\%$ | $8.7\%$ | ||

LOCOFloat | $42.433$ ns | 4693 | 150 | 0 |

no DSPs | $26.7\%$ | $0.4\%$ | $0\%$ | |

32-bit Floating-point | $22.943$ ns | 3147 | 115 | 0 |

no DSPs | $17.9\%$ | $0.3\%$ | $0\%$ | |

64-bit Floating-point | $31.452$ ns | 11277 | 212 | 0 |

no DSPs | $64.1\%$ | $0.6\%$ | $0\%$ | |

Fixed-Point | $37.730$ ns | 1536 | 98 | 0 |

no DSPs | % | % | $0\%$ |

Latency LUTS | 6-Input | DSPs | ||
---|---|---|---|---|

64-bit Barrel shifter | $2.178$ ns | 128 | 0 | |

25 × 25 Multiplier | $5.554$ ns | 24 | 2 | |

50 + 50 Adder/Subtractor | $13.165$ ns | 460 | 0 |

Case | C | L | ${\mathit{V}}_{\mathit{in}}$ | ${\mathit{V}}_{\mathit{out}}$ | P | ${\mathit{F}}_{\mathit{sw}}$ |
---|---|---|---|---|---|---|

1 [27] | 100 $\mathsf{\mu}$F | 22 $\mathsf{\mu}$H | 62 V | 5 V | 10 W | 210 kHz |

2 [26] | 220 $\mathsf{\mu}$F | 22 $\mathsf{\mu}$H | $3.3$ V | $2.8$ V | $0.27$ W | 300 kHz |

3 [28] | $8.8$ mF | 40 $\mathsf{\mu}$H | 12 V | $5.2$ V | 250 W | 150 kHz |

4 [29] | 94 $\mathsf{\mu}$F | 1 $\mathsf{\mu}$H | $5.4$ V | $4.5$ V | 20 W | 700 kHz |

5 [30] | 100 $\mathsf{\mu}$F | $2.2$$\mathsf{\mu}$H | $5.5$ V | $4.7$ V | 40 W | 550 kHz |

5 [31] | 66 $\mathsf{\mu}$F | $0.33$$\mathsf{\mu}$H | $3.9$ V | $3.25$ V | 33 W | 700 kHz |

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**MDPI and ACS Style**

Sanchez, A.; de Castro, A.; Martínez-García, M.S.; Garrido, J. LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators. *Electronics* **2020**, *9*, 81.
https://doi.org/10.3390/electronics9010081

**AMA Style**

Sanchez A, de Castro A, Martínez-García MS, Garrido J. LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators. *Electronics*. 2020; 9(1):81.
https://doi.org/10.3390/electronics9010081

**Chicago/Turabian Style**

Sanchez, Alberto, Angel de Castro, Maria Sofía Martínez-García, and Javier Garrido. 2020. "LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators" *Electronics* 9, no. 1: 81.
https://doi.org/10.3390/electronics9010081