Next Article in Journal
Action Recognition Using Deep 3D CNNs with Sequential Feature Aggregation and Attention
Previous Article in Journal
DSFTL: An Efficient FTL for Flash Memory Based Storage Systems
Previous Article in Special Issue
A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

Electronics 2020, 9(1), 146; https://doi.org/10.3390/electronics9010146

Article
A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process
1
Division of Electronics and Electrical Engineering, Dongguk University, Seoul 04620, Korea
2
Jung-Dong Park, Division of Electrical and Electronics Engineering, Dongguk University, Seoul 04620, Korea
*
Author to whom correspondence should be addressed.
Received: 31 December 2019 / Accepted: 10 January 2020 / Published: 12 January 2020

Abstract

:
In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.
Keywords:
CMOS; LDO; low dropout; power supply rejection ratio; regulation

1. Introduction

In the power management system, the demand for integrating the whole power management integrated circuit (PMIC) into a single chip has significantly increased [1]. By integrating the power management system into a chip, the system cost is reduced significantly, since the external power management blocks can be dramatically simplified. The main reason for using a low-dropout (LDO) regulator is to reject the ripples from the voltage source, which means power supply rejection (PSR) is vital. For a conventional LDO regulator, it is necessary to have a high DC gain and bandwidth of the error amplifier [2]. For the voltage regulators, the bandwidth of the circuit should be improved and must provide a higher power supply rejection (PSR) according to the surrounding blocks. Conventional LDO regulators provide poor PSR at relatively high frequencies even around 300 kHz.
Various techniques have been introduced to improve PSR. Using an RC filter at the output of the LDO regulator or using two regulators helps to improve the PSR [3]. This technique can improve the PSR, but it also increases the dropout voltage because of the series resistor or the second regulator. Another technique is using a charge pump and an NMOS pass transistor [4]. This method utilizes an NMOS pass transistor which requires that the bias of the NMOS should be higher than the supply voltage. [4] implemented a charge pump in order to provide a higher bias which is an independent bias for the regulator. However, this technique dissipates more DC power and increases the complexity of the circuit.
In this paper, we introduce an LDO regulator which achieves a significantly improved PSR by utilizing the feed-forward ripple cancellation technique. The purpose of this technique is to duplicate the input ripples to the gate of the pass transistor so that it will cancel out the input ripples to increase the power supply rejection significantly. The proposed LDO regulator consists of a three-stage error amplifier (EA), a summing amplifier (SA), and a feed-forward amplifier (FFA), which helps to increase the PSR and provide a robust output voltage. To precisely control the gain of the summing amplifier, we employ a variable resistor consisting of MOS switches and a binary resistive bank which can change the total resistance linearly with the control bits. This paper is structured as follows. Section 2 describes the operation of a conventional LDO regulator and describes various techniques used to improve the PSR of an LDO regulator. Section 3 explains the circuit design of the proposed LDO regulator, and the measurements for the proposed LDO regulator are presented in Section 4, followed by the conclusion in Section 5.

2. Techniques Used in Low-Dropout Regulator for the Enhanced Power Supply Rejection Ratio (PSRR)

A conventional LDO regulator, shown in Figure 1, includes a pass transistor Mpass and an error amplifier for comparing the voltage of the feedback circuit and Vref. The conventional LDO regulator has three paths by which the noise can couple with the output of the LDO regulator. The first path is through the pass transistor, the second path is from the error amplifier which is connected with the supply voltage, VDD, and the third path is from the Vref. The first path is mainly dependent on the feedback network produced by R1 and R2 at low frequencies. As the frequency starts to increase, the load capacitance, CL, takes the role of getting rid of the input ripples. However, the equivalent self-inductance and resistance of the capacitor CL will reduce the effect [1]. The PSR of the second path is limited by the DC gain and bandwidth of the error amplifier. Therefore, the challenge of the error amplifier is that both DC gain and bandwidth have to be large. At high frequencies, the effect of the second path is weak due to the capacitance seen at the gate of the pass transistor. The PSR of the third path is limited by the bandgap reference or the bias voltage source.

3. Proposed LDO Regulator Circuit Design

The schematic diagram of the proposed low-dropout regulator is shown in Figure 2. To have a clean output voltage, a zero-transfer gain from the input to the output is required. To achieve the zero-transfer gain in an ideal case, a feed-forward ripple cancellation technique is used in the proposed LDO regulator. A feed-forward path carries the same input ripples through the feed-forward amplifier and the summing amplifier to the gate of the Mpass. Then, the ripples at the gate cancel out the ripples at the source of the Mpass. However, in the practical case, some of the ripples at the source leak through the drain-source resistance (rds,pass) of the Mpass. Thus, to cancel out the additional ripples from rds,pass, the produced ripples at the gate of the Mpass should be higher in ripple amplitude [1]. The pass transistor (Mpass) is implemented using a PMOS transistor considering that the DC voltage level required at the gate is lower than the supply voltage VDD, while the NMOS pass transistor needs a higher DC voltage level at the gate. The length of the pass transistor is 0.1 um and the width is 1.5 mm.
The error amplifier is implemented to have a feedback circuit and controls the output voltage with RF1 and RF2. The summing amplifier’s objective is to combine the signal from the feed-forward path with the feedback regulating loop. The summing feedback resistances (R3, R4, Rbank) push the output pole higher so that it is higher than the gain bandwidth (GBW) of the LDO regulator [1].
Figure 3 shows the transistor-level schematic diagram of the feed-forward, summing, and error amplifier implemented in the proposed LDO regulator. Specific size and parameters are given in Table 1. The operational transconductance amplifier (OTA) consists of a differential amplifier with active load, common source amplifier, compensating capacitor, and a series resistor next to the compensating capacitor. The differential amplifier with active load performs differential to single-ended conversion while maintaining the gain [5]. The capacitor CC for compensation achieves pole-splitting in the circuit, which will affect the stability. The series resistor, Rgd, provides a left half-plane zero to compensate for the right half-plane zero that was produced by CC.
For the resistive bank (Rbank) presented in Figure 2, it is implemented to cover the range of resistance from 750 Ω to 1125 Ω in the typical process condition. Considering the process variation of the polyresistor and the active device, the designed resistive bank was designed to provide the correct summing gain over the possible process variation. Figure 4 presents the schematic diagram of the proposed resistive bank. The aimed resistance of the resistor bank is 950 Ω. The parallel switch and the series switches use the bits 0, 1, 2, and 3. The 15 resistors, RB, are added to provide a 25 Ω step from 750 Ω to 1125 Ω. The parallel switches make the entire resistance fixed so that only the number of RB determines the total resistance. The equation for the resistor bank is given by
R b a n k [ Ω ] = 600 + R M O S F E T R P R P + ( b 0 + b 1 + b 2 + b 3 ) R M O S F E T + R B b 0 + 2 R B b 1 + 4 R B b 2 + 8 R B b 3   [ Ω ]
where RP is the parallel switch and bnumber is the bit number. The resistance bit table is shown in Table 2.
To supply a fixed reference voltage to the error amplifier in any conditions like temperature changes or power supply variations, the circuit needs a bandgap voltage reference shown in Figure 5. An OTA is implemented to provide feedback for MB1 and MB2. The feedback on the MB1 side is implemented as positive feedback and the other side as negative feedback. To stabilize the output voltage of the bandgap reference is to have more negative feedback than the positive one. Three resistors, RB1, RB2, and RB3, make the loop gain of the negative feedback stronger than that of the positive feedback.
The OTA in the bandgap voltage reference is presented in Figure 6. The reference voltage (VREF) of 880 mV was selected to have 1 V as the output voltage. The resistors RF1 and RF2 determine the output voltage, 1 V, based on the ratio of those resistors and the reference voltage from the bandgap reference. The equation for the output voltage (Voutput) can be expressed as
V O U T P U T [ V ] = V R E F × R F 1 + R F 2 R F 2 [ V ] .

4. Measurement Results

Figure 7 shows a microphotograph of the implemented LDO regulator with a chip size of 0.092 mm2 without pads, while Figure 8 is the power supply rejection ratio (PSRR) and regulation measurement setup. Rpar is the parasitic resistance in the measurement setup. An SPI (Serial Peripheral Interface) module is used to control the resistor bank and the biasing points of each OTA. The quiescent current consumption of the circuit is 0.385 mA under a 1.2 V supply voltage.
In Figure 9, the PSRR comparison graph between the simulation and measurement of the proposed LDO regulator and a conventional LDO regulator is shown. Measurements and simulation correspond well when we include the parasitic series resistance Rpar in the VDD input port as presented in Figure 8. Compared with a conventional LDO regulator, 30–40 dB of extra PSRR were observed from 10 kHz–10 MHz. Figure 10 shows the output voltage when the load changes. Load regulation can be calculated by Equation (3).
Load   Regulation = Δ V O U T Δ I L [ m V / m A ] .
ΔVOUT is 45 mV when ΔIL is 19.38 mA in this work. Thus, the load regulation is calculated to be 2.3 (mV/mA).
Figure 11 shows the change in VOUT when changing the VIN with a 100 Ω load. With Figure 11, the line regulation can be calculated by Equation (4).
Line   Regulation = Δ V O U T Δ V I N [ V / V ]
ΔVOUT is 5 mV when ΔVIN is 300 mV in this work. Thus, the line regulation is calculated to be 0.08 (V/V).
The performances of the proposed LDO regulator are summarized and compared with the recently reported LDO regulators in Table 3.

5. Conclusions

A power supply rejection ratio (PSRR)-enhanced LDO regulator is proposed by utilizing the feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. In the summing amplifier, we introduced a resistive bank which is linearly controlled by binary signals to achieve an optimal ripple cancellation. The regulator provides 35–76.8 dB of PSRR at 1 MHz–1 GHz. The LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 (mV/mA), while the line regulation is 0.05 (V/V). The circuit consumes 385 μA with an input voltage of 1.2 V. The area without the pads is 0.092 mm2.

Author Contributions

Data curation, Y.-J.C.; Methodology, J.-D.P.; Supervision, J.D.P.; Validation, H.N.; Writing—original draft, Y.-J.C.; Writing—review & editing, J.-D.P. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIP) (2019M3F6A1106118); the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20194030202320).

Acknowledgments

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2019M3F6A1106118); the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20194030202320).

Conflicts of Interest

The funders had no role in the design of the study; in the collection, analyses or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

References

  1. El-Nozahi, M.; Amer, A.; Torres, J.; Entesari, K.; Sanchez-Sinencio, E. High PSR Low Drop-Out Regulator with Feed-Forward Ripple Cancellation Technique. IEEE J. Solid-State Circuits 2010, 45, 565–577. [Google Scholar] [CrossRef]
  2. Jang, H.-J.; Roh, Y.-S.; Moon, Y.-J.; Park, J.-P.; Yoo, C.-S. Low Drop-Out (LDO) Voltage Regulator with Improved Power Supply Rejection. JSTS 2012, 12, 313–319. [Google Scholar] [CrossRef]
  3. Application Note 883: Improved Power Supply Rejection for IC Linear Regulators; Maxim Integrated Products, Inc.: Sunnyvale, CA, USA, 2002.
  4. Gupta, V.; Rincón-Mora, G.A. A 5 mA 0.6 um CMOS Millercompensated LDO regulator with -27 dB worst-case power-supply rejection using 60 pF of on-chip capacitance. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 11–15 February 2007; pp. 520–521. [Google Scholar]
  5. Razavi, B. Fundamentals of Microelectronics; Wiley: Hoboken, NJ, USA, 2006. [Google Scholar]
  6. Park, C.; Onabajo, M.; Silva-Martinez, J. External Capacitor-Less Low Drop-Out Regulator with 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range. IEEE J. Solid-State Circuits 2014, 49, 486–501. [Google Scholar] [CrossRef]
  7. Lim, Y.; Lee, J.; Park, S.; Jo, Y.; Choi, J. An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J. Solid-State Circuits 2018, 53, 2675–2685. [Google Scholar] [CrossRef]
Figure 1. The schematic diagram of the conventional low-dropout regulator.
Figure 1. The schematic diagram of the conventional low-dropout regulator.
Electronics 09 00146 g001
Figure 2. The schematic diagram of the proposed low-dropout regulator.
Figure 2. The schematic diagram of the proposed low-dropout regulator.
Electronics 09 00146 g002
Figure 3. Schematic of the feed-forward, the summing amplifier, and the error amplifier.
Figure 3. Schematic of the feed-forward, the summing amplifier, and the error amplifier.
Electronics 09 00146 g003
Figure 4. Schematic diagram of the proposed resistive bank.
Figure 4. Schematic diagram of the proposed resistive bank.
Electronics 09 00146 g004
Figure 5. Schematic diagram of the bandgap voltage reference.
Figure 5. Schematic diagram of the bandgap voltage reference.
Electronics 09 00146 g005
Figure 6. Schematic diagram of the operational transconductance amplifier (OTA) used in the bandgap voltage reference.
Figure 6. Schematic diagram of the operational transconductance amplifier (OTA) used in the bandgap voltage reference.
Electronics 09 00146 g006
Figure 7. A microphotograph of the proposed low-dropout (LDO) regulator.
Figure 7. A microphotograph of the proposed low-dropout (LDO) regulator.
Electronics 09 00146 g007
Figure 8. (a) Power supply rejection ratio (PSRR) and (b) regulation measurement setup of the proposed LDO regulator.
Figure 8. (a) Power supply rejection ratio (PSRR) and (b) regulation measurement setup of the proposed LDO regulator.
Electronics 09 00146 g008aElectronics 09 00146 g008b
Figure 9. PSRR comparison graph between the simulation and measurement.
Figure 9. PSRR comparison graph between the simulation and measurement.
Electronics 09 00146 g009
Figure 10. Load regulation comparison graph between the simulation and measurement.
Figure 10. Load regulation comparison graph between the simulation and measurement.
Electronics 09 00146 g010
Figure 11. Line regulation comparison graph between the simulation and measurement with a 100 Ω load.
Figure 11. Line regulation comparison graph between the simulation and measurement with a 100 Ω load.
Electronics 09 00146 g011
Table 1. Parameters of the feed-forward, summing amplifier, and error amplifier.
Table 1. Parameters of the feed-forward, summing amplifier, and error amplifier.
Feed-Forward Amp.Summing Amp.Error Amp.
M1 [μm/μm]10/110/15/1
M2 [μm/μm]10/110/15/1
M3 [μm/μm]25/125/115/1
M4 [μm/μm]25/125/115/1
M5 [μm/μm]27/150/195/1
M6 [μm/μm]12/18/16/1
M7 [μm/μm]12/1-6/1
M8 [μm/μm]12/112/126/1
M9 [μm/μm]12/112/126/1
CC [pF]441
Rgd [kΩ]45-
Table 2. Bit table of the resistive bank.
Table 2. Bit table of the resistive bank.
Bit 3Bit 2Bit 1Bit 0Resistance [Ω]
0000744
0001772
0010796
0011827
0100845
0101876
0110900
0111935
1000951
1001981
10101006
10111041
11001056
11011091
11101115
11111157
Table 3. Summary of the proposed LDO regulator compared with recently reported LDO regulators.
Table 3. Summary of the proposed LDO regulator compared with recently reported LDO regulators.
LDO RegulatorThis Work[1][2][6][7]
Technology [nm]6513013018065
VIN [V]1.21.151.21.81.2
VOUT [V]0.98111.61
Dropout Voltage [V]0.220.150.20.20.2
Maximum Load [mA]2025505025
Quiescent Current [μA]3855065558–297.5
PSRR [dB][email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
[email protected] MHz
Load Regulation [mV/mA]2.30.0480.130.140.042
Line Regulation [mV/mV]0.080.0264.250.0750.0038
Area [mm2]0.0920.0490.40.140.087
Back to TopTop