Fault Modeling of Graphene Nanoribbon FET Logic Circuits
- Device fabrication. It may be difficult to extend optical lithography into the realm of low tens of nanometers. Furthermore, random process variations can lead to device characteristics that are unpredictable.
- Device operation. As dimensions are reduced, voltage levels also need to be reduced accordingly. This fact increases the subthreshold static power of the metal–oxide–semiconductor field-effect transistors (MOSFETs). In addition, conventional MOSFETs will behave differently, appearing quantum effects, such as tunneling and ballistic transport.
- Heat dissipation. As device density increases, heat dissipation becomes a major problem, reducing circuit reliability and leading to shorter device lifetimes, or even to device failure.
- Identifying a wide set of fault causes and mechanisms in GNR FET devices. This constitutes a deep review task, necessary to develop points 2 and 3.
- Analyzing the fault propagation and modeling faults at the logic level. This phase is done based on the previous point, and the structure and equations of digital circuits. Fault modeling opens the possibility of evaluating the reliability of defect-tolerant nanoarchitectures by means of fault injection at a manageable cost.
- Comparing the fault models with other emerging devices, namely, CNT FETs and NW FETs. They are also promising devices for future digital applications.
2. Graphene Nanoribbon Devices
3. Graphene Nanoribbon Logic Circuits
4. Reliability Challenges and Requirements
5. Fault Causes, Mechanisms, and Models
- Study of the impact of defects and faults on GNR FETs. Generation of fault models at the device (transistor) level. In this step, we analyzed the equations of the devices and their parameters.
- Study of fault propagation from the device level to the (logic) circuit level. Generation of fault models at the logic circuit level. This step is based on the structure of logic circuits made of transistors.
5.1. Manufacturing Variations
5.1.1. Ribbon Width
- Power degradation. GNR FET ON current scales proportionally with width W, whereas the OFF current has an exponential dependency :
- Noise margin degradation. The second effect is a significantly diminishing noise margin. Band-to-band tunneling in narrow bandgap GNR FETs prevents either PUN or PDN of logic circuits from completely cutting off when its complement network is active . This may lead to voltage variations in the output of logic circuits. We propose complementary value and indetermination fault models for combinational circuits. The complementary value model means a change in the logic value (“0” changes to “1” or vice versa). The indetermination model represents a value that is in the forbidden gap between “0” and “1” logic values. In the case that the perturbed signal arrives at a sequential circuit, it can propagate and manifest as a bit-flip, which means a change in the memory state.
- Speed degradation. W variations can provoke the mobility degradation of the carriers, and thus the reduction of the GNR FET switching speed. Let us analyze this relationship. First, the ribbon width affects the energy bandgap according to Equation (3). Then, the mobility µ depends on Eg using the following expression :
- λsc = scattering length,
- m* = effective mass,
- m*v = ℏkF = carrier momentum,
- ℏ = h/2π = reduced Planck constant,
- kF = Fermi wavenumber.
5.1.2. Oxide Thickness
5.1.3. Channel Length
5.1.4. Misalignment of Electrodes
5.2. Manufacturing Defects
5.2.1. Edge Roughness
5.2.2. Charge Impurities
5.2.3. Lattice Vacancies and Adsorbates
5.2.4. Electrical Contacts
5.3. Environmental Faults
5.3.1. Ion Radiation
5.3.2. Thermal Effects
5.4. Aging Faults
Graphene Interconnection Defects
- Fault causes have been classified in four groups (see Table 1): manufacturing variations, manufacturing defects, environmental faults and aging faults. The most harmful causes according to the literature are ribbon width variations, edge roughness, and charge impurities in gate oxide.
- Two main types of fault mechanisms have been identified (see Figure 5): those that perturb the logic signal value and those that impact the logic signal timing. The former are related to Ion/Ioff degradation and some aging processes, whereas the latter are linked with mobility degradation.
- With respect to fault models at the device level, we note that the most frequent is the delay fault model (see Table 1). This is because there is no standard fault model (stuck-on, stuck-off, delay) related to Ion/Ioff degradation at the device level. In this case, a dash appears in the table. Nevertheless, stuck-off related to wire breakdown has been identified.
- Directly related to the fault mechanisms, two groups of fault models are proposed at the logic level. Timing degradation can be modelled with the delay fault model. Value degradation can be modelled with several fault models: complementary value and indetermination in combinational circuits, and bit-flip in sequential circuits and memory. Complementary value, indetermination and delay are permanent faults, whereas bit-flip is transient. Other fault models that affect the output value are stuck-at and high impedance, related to the breakdown of graphene wires. Table 1 and Figure 5 show that timing degradation and the delay fault model are quite relevant, because they are related to more fault causes.
- Note that manufacturing defects and variations are permanent faults in essence. Nevertheless, environmental and wear-out faults can provoke aging processes, where the device characteristics change over time. Even transient faults may be generated by environment, although this is a subject of future research. The term “degradation” related to permanent faults implies an alteration in the spatial domain.
6. Comparison with CNT and NW Circuits
6.1. Comparison with CNTs
- Manufacturing defects of the metallic and misalignment/misposition types . The manufacturing process makes it nearly impossible to guarantee the perfect alignment and accurate positioning of all CNTs at the Very Large Scale Integration (VLSI scale, or the growing of semiconducting CNTs exclusively. GNR FET circuits avoid these defects, because graphene’s planar profile makes it amenable to well-established top-down planar fabrication techniques for silicon CMOS devices [40,41,42]. Some fault models, different from those of GNR FET circuits, have been identified in relation with metallic and misalignment/misposition defects. For instance, we note stuck-on/stuck-off at the device level, which may manifest as stuck-at or even a change in the logic function at the logic level [20,29].
- Producing a good electrical contact between CNTs and metal electrodes can be problematic, because they tend to create Schottky barriers. Although electrical contacts also remain an important issue in graphene circuits, GNR metal–semiconducting junctions can be patterned together into all-graphene circuits (see Figure 2), avoiding metallic contacts to some extent. Moreover, GNR–CNT junctions are possible, as shown in Figure 3. Poor contacts in CNT circuits provoke an increase of the device resistance. They can be modelled with the delay fault model . Defective metallic contacts in GNR circuits are also modelled with the delay fault model (see Figure 5 and Table 1).
- Manufacturing variations, which affect some parameters of the CNT FET. Variations in the dimensions of the devices (CNT diameter, length, and oxide thickness) can modify the channel resistance and the threshold voltage of the transistor. This degrades the circuit speed. Thus, the delay fault model is proposed. As we have seen in Section 5, manufacturing variations are a critical issue in GNR FETs, especially ribbon width variation.
- The break probability in CNT is very low, due to its high flexibility and fracture strain. Nevertheless, some research papers have studied the fracture mechanism in small diameter (less than 5 angströms) CNTs due to deformation and bending . Related fault models have been identified in . The fracture of CNT provokes the opening of the CNT FET channel and can be modelled with the stuck-off fault model at the device level. This may manifest as stuck-at or high impedance (open) at the logic level. About GNR, extremely high Young’s modulus and excellent flexibility has been demonstrated . Although the fracture process is similar to that occurred in carbon nanotube, the width of the GNR was found to have a slight effect on the fracture point. On the other hand, graphene wire degradation with time has been observed . Under constant current, wire conductivity degrades linearly with time, similar to CNTs. This can be modelled with delay, stuck-at, or high impedance at the logic level, as shown in Section 5.4.
6.2. Comparison with NWs
Conflicts of Interest
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|Defects and Faults||Causes and Mechanisms||Effect on GNR FET||Fault Model at Device Level||Effect on the Logic Circuits||Fault Model at Logic Level|
|Manufacturing variations||Width [9,21,23,27,31]||Energy band-gap variation||Leakage current, Ion/Ioff degradation||-||Power degradation, noise margin degradation||Combinational → Complementary value, Indetermination FF, memory → Bit-flip|
|Mobility degradation||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Oxide thickness ||Gate capacitance variation||Delay degradation||Delay||Speed degradation||Delay|
|Channel length [1,32]||Channel resistance variation||Reduction of the switching speed, degradation of ballistic transport||Delay||Speed degradation||Delay|
|Misalignment of electrodes ||Access resistance in the channel||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Manufacturing defects and residues||Edge roughness [7,9,12,23,31]||Irregular edges||Leakage current, reduction of Ion/Ioff||-||Noise margin degradation, power degradation||Combinational → Complementary value, Indetermination FF, memory → Bit- flip|
|Edge scattering, mobility degradation||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Charge impurities in the gate oxide [9,21,23,31,32,34]||Modification of the electrostatic potential in the channel||Ion/Ioff degradation||-||Noise margin degradation, power degradation||Combinational → Complementary value, Indetermination FF, memory → Bit-flip|
|Charge scattering, mobility degradation, conductance decay||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Lattice vacancies and adsorbates [10,35]||Charge scattering, mobility degradation, conductance decay||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Electrical contacts [12,36,37,38]||Contact resistance between electrodes and graphene channel||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Environment||Ion radiation ||Lattice disruption, mobility degradation||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Thermal effects ||Lattice vibration, mobility degradation||Reduction of the switching speed||Delay||Speed degradation||Delay|
|Thermal decoherence of the electron wave function (quantum)||-||-|
|Wearout||Interconnect defects ||Graphene oxidation||Increase of wire resistance, breakdown||Delay,|
|Speed degradation, Fixed or floating output||Delay,|
|Most harmful causes and mechanisms||Width variation,|
gate oxide impurities
|Models at device level||Delay,|
|Models at logic level||Delay,|
change of logic function
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Gil-Tomàs, D.; Gracia-Morán, J.; Saiz-Adalid, L.J.; Gil-Vicente, P.J. Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics 2019, 8, 851. https://doi.org/10.3390/electronics8080851
Gil-Tomàs D, Gracia-Morán J, Saiz-Adalid LJ, Gil-Vicente PJ. Fault Modeling of Graphene Nanoribbon FET Logic Circuits. Electronics. 2019; 8(8):851. https://doi.org/10.3390/electronics8080851Chicago/Turabian Style
Gil-Tomàs, D., J. Gracia-Morán, L.J. Saiz-Adalid, and P.J. Gil-Vicente. 2019. "Fault Modeling of Graphene Nanoribbon FET Logic Circuits" Electronics 8, no. 8: 851. https://doi.org/10.3390/electronics8080851