A High-Accuracy Ultra-Low-Power Offset-Cancelation On-Off Bandgap Reference for Implantable Medical Electronics

Abstract

An ultra-low-power and high-accuracy on-off bandgap reference (BGR) is demonstrated in this paper for implantable medical electronics. The proposed BGR shows an average current consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy of 0.69%. The on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism allows a relatively higher current in the sample phase to alleviate the process variation of bipolar transistors. To compensate the error caused by operational amplifier offset, the correlated double sampling strategy is adopted in the BGR. The proposed BGR is implemented in 0.35 μm standard CMOS process and occupies a total area of 0.063 mm². Measurement results show that the circuit works properly in the supply voltage range of 1.8–3.2 V and achieves a line regulation of 0.59 mV/V. When the temperature varies from −20 to 80 °C, an average temperature coefficient of 19.6 ppm/°C is achieved.

1. Introduction

Along with the continuous development of modern society and growing demand for high-quality life, implantable medical electronics are increasingly adopted in healthcare medical devices such as cardiac pacemakers [1,2,3]. These devices are usually battery powered and need to have ultra-low power consumption of a few microwatts or less [4,5,6,7,8]. Since they would probably be placed where they are not easily removed or recharged, they have to continue working for a relatively long time. A number of important analog circuits for high-precision signal processing, such as voltage regulators, analog to digital converters (ADCs) and digital to analog converters (DACs), are used in almost every biomedical system. All of them demand an accurate bandgap reference (BGR) [9]. In these devices, BGRs provide the voltage references for other important functional blocks and are supposed to be working all the time. Thus, the required average current dissipation of BGR is in the range of several tens of nano-ampere [10,11,12].

To meet the requirement for low power, subthreshold voltage references without bipolar transistors have been developed and used widely [10,11,12]. However, these V_TH-based references often suffer from degraded performance in accuracy since the threshold voltage (V_TH) of MOSFET changes too much (about 50–100mV) with process variation. Trimming is usually employed to solve this issue. However, the temperature coefficient would be worse after trimming [12]. A conventional bipolar junction transistor (BJT)-based BGR can provide a fairly precise reference voltage, but it requests larger power consumption. When we try to budget a lower current consumption for BJT-based BGR, resistors with very large values are needed, and the V_BE of BJT also varies dramatically. V_BE variation introduces large fluctuations to the output reference voltage. Even for relatively larger budgeted power consumption, trimming is still generally required for BJT-based BGR because of the existence of mismatch and offset [13].

In this paper, an ultra-low power, high accuracy BGR is presented. The proposed reference provides a 1.17 V output under 2.8 V supply voltage with 78 nA average current consumption. An on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism increases the working current of the BJT-based BGR during the sample period, which decreases V_BE spread. A correlated double sampling (CDS) strategy is adopted to cancel the offset of the operational amplifier (Opamp), which is fulfilled by a sampling capacitor block combined with chopper mechanism. The conflict between low power and high accuracy is preliminarily settled. The theoretical foundation and specific circuit design are described in Section 2. Section 3 presents the simulation and measurement results as well as a performance comparison. Finally, conclusions are summarized in Section 4.

2. Proposed Bandgap Reference

2.1. Error Analysis of the BJT-Based BGR

The key point of this paper is to utilize the techniques of offset cancelling, correlated double sampling and switched-RC to improve the accuracy of the raw BGRs under stringent power consumption constraints. A conventional BJT-based BGR is employed here for demonstration. The core circuit of the BJT-based BGR is shown in Figure 1. The reference voltage generated by it is given by:

$$V_{REF}=V_{BE2}+\frac{R_2}{R_1}\Delta V_{BE}.$$

(1)

When considering non-ideal factors relevant with V_BE and Opamp offset, Equation (1) can be approximately rewritten as

$$V_{REF}{}^{\prime }=V_{BE2}{}^{\prime }+\frac{R_2}{R_1}(\Delta V_{BE}+V_{os})$$

(2)

where the superscript ′ denotes the erroneous quantity. High mismatch characteristic of MOS transistors can introduce considerate offsets to Opamp especially under extreme low power consumption. The V_BE spread is also critical because it directly translates an error in V_REF. The proposed circuit concentrates on canceling these two sources of errors which have large magnitudes of effects on the accuracy of BGR output voltage.

2.2. Architecture of the Proposed BGR Circuit

The systematic architecture of the proposed BGR is shown in Figure 2, which consists of an on-off V_BE-based BGR with chopper mechanism, a sampling-capacitor block, and a sample-and-hold switched-RC filter. Also, there is a digital block to generate the low-duty-cycle clocks used in the on-off BGR, which is manually designed as the analog circuits to reduce the turnover rate of the clocks and thus save power. The on-off BGR takes advantages of the conventional V_BE-based BGR topology. When consuming dozens of microampere (μA), the conventional V_BE-based BGR operates reliably and has little process variation spread. During the hold period, the on-off BGR is turned off to save power. The sampling-capacitor block is based on the technique of correlated double sampling (CDS), which samples twice in a working (on) period, before and after the conversion of the chopper connection state in the on-off BGR, respectively. Therefore, the offset of the Opamp V_os is cancelled out. When the BGR block entered the off state, the switched-RC filter takes the average of the last twice sampled voltages, holds it until next working (on) state, and gets rid of the out-of-band noise through the function of filtering.

2.3. Chopper Mechanism and Correlated Double Sampling

Figure 3 shows the implementation of the on-off BGR which employs chopper mechanism. A near-zero power consumption start-up structure is adopted. The parameter values of the main components in the BGR core circuit are as follows. The emitter area of Q₁ and Q₂ is 2 × 2 μm. R₁ = 10 kΩ and R₂ = 80 kΩ. The size of MP_1/2 is 8 μm/16 μm × 6 while the size of the switch transistors is 4 μm/1 μm × 1. The sizes of the transistors are designed to be large for good matching and low flicker noise. Considering the low speed characteristic of the designed circuit, the lengths of the transistors are selected at least 3 times of the 350 nm minimum channel length for lower static leakage current.

Under phase Φ₁ and Φ₂, the BGR power cycle is controlled by the clock ON/OFF CLK as shown in Figure 3b. With the duty cycle D = 0.25% (T_ON = 250 us, T_ON + T_OFF = 100 ms), a working current of 16 uA is budgeted for the BGR block to achieve an average power consumption as low as 40 nA. The base-emitter voltage of transistor Q₂ is given by

$$V_{BE2}=V_T\ln (\frac{I_C}{J_{S}A}),$$

(3)

where I_C and J_S are the working collector current and reverse saturation current per unit area of the transistor, respectively, and A is the emitter area. We assume the current variation is I_X. Then the relative error can be deduced as in Equation (5).

$$V_{BE2}{}^{\prime }=V_T\ln (\frac{I_C+I_X}{J_{S}A})$$

(4)

$$\epsilon =\frac{V_{BE}{}^{\prime }-V_{BE}}{V_{BE}}=\frac{\ln (\frac{I_C+I_X}{J_{S}A})}{\ln (\frac{I_C}{J_{S}A})}-1\approx \frac{1}{\ln (\frac{I_A}{J_{S}A})}\cdot \frac{I_{X}D}{I_A},$$

(5)

where ε represents the relative error, and I_A = I_C. D is the average current. When the working collector current I_C is increased by an on/off duty cycle of 0.25%, the relative error spread of V_BE is 400 times less.

The chopper blocks are controlled by the 10Hz CH_CLK to cancel the offset of the Opamp under phases Φ₃ and Φ₄. In the middle of the on-phase of BGR, the chopper blocks convert connection status from (X₂---A, X₁---B) to (X₁---A, X₂---B). In the next on-phase, the connection status changes back. Another chopper block is introduced in the signal path of the designed Opamp to assure that a negative feedback loop be formed according to the chopper status in the on-off BGR.

Figure 4 shows the sampling-capacitor circuit using the technique of correlated double sampling (CDS) [14,15]. The values of the sampling capacitors are selected as C₁ = C₂ = C₀ = 40 μm × 40 μm (1.6 pF). In the control of double sampling clocks CLK_1 and CLK_2, whose clock timings are shown in Figure 4b, C₁ and C₂ sample the output of the on-off BGR V_REF before and after the chopper connection state conversion during T_S1 and T_S2, respectively, in a working (on) period. C₀ samples during the interval T_S and sums up the two sampled voltages in it. Using Equation (2), only the Opamp offset is considered,

$$V_1{}^{\prime }=V_{BE2}+\frac{R_2}{R_1}(\Delta V_{BE}+V_{os})=V_{des}+\frac{R_2}{R_1}{V}_{os}$$

(6)

$$V_2{}^{\prime }=V_{BE2}+\frac{R_2}{R_1}(\Delta V_{BE}-V_{os})=V_{des}-\frac{R_2}{R_1}{V}_{os}$$

(7)

$$V_1{}^{\prime }C+V_2{}^{\prime }C+V_{0}C=V_0^{\prime }*3C\mathrm{If},V_0^{\prime }=V_0\mathrm{So},V_0^{\prime }=\frac{V_1{}^{\prime }+V^{\prime }{}_2}{2}=V_{des},$$

(8)

where C₁ = C₂ = C₀ = C, V₁′ is the voltage on C₁ which is sampled before the connection state conversion, V₂′ is the voltage on C₂ sampled after the conversion, V₀ is the current voltage on C₀ and V₀′ is the sample voltage in next cycle on C₀. Eventually, V_des is the original design value of V_REF. When the stable condition is reached, V₀ is the average value of V₁′ and V₂′, canceling the error of V_REF caused by the Opamp offset.

2.4. Sample-and-Hold Switched-RC Filter

Figure 5 shows the circuit implementation of the sample-and-hold switched-RC filter. A MOS-R is used to achieve a high RC filtering resistance of 25 MΩ with small chip area. To alleviate the effect of injection and clock feedthrough, a dummy MOS switch M₂ is added in series with the actual switch M₁ [13].

Since the drain-bulk and drain-source leakage is critical to the accuracy and stability of V_REF output, especially during a long hold time of 100 ms, a simple feedback buffer A₁ is used to reduce the voltage drop. In the hold phase, the bulk and source nodes of M₁ are buffered to V_REF through M₇, eliminating charge leakage at C_S.

Moreover, the filter emulates a much lower filter pole frequency by pulse-switching them. Compared to the RC filter in Figure 2, the effective pole frequency in Figure 5 is given by [13]:

$$f_{LPF}=\frac{D}{2\pi R_S{C}_S}$$

(9)

with C_S = 10 pF, R_S = 25 MΩ, and D = 0.06% (T_S = 60 us, T_H + T_S = 100 ms), a filter pole of 0.4 Hz can be achieved, which is about two decades lower than the noise integration bandwidth. Consequently, out-of-band noise could be filtered more thoroughly.

3. Simulation and Measurement Results

The Offset-Cancelation Switched-RC Bandgap Reference presented in this paper has been applied in an implanted cardiac pacemaker ASIC, featured with low power, high reliability and low speed. Consequently, 0.35 μm CMOS technology is employed, which is not advanced but adequately qualified for such applications [1,2]. Also, a lithium-iodine battery with a typical supply voltage of 2.8 V is usually used for cardiac pacemakers, which has a sufficient level of safety and good discharging characteristics [4].

For on-off BGRs with small duty cycles, the settling time for start-up is usually concerned. Figure 6 shows the transient output voltage of the proposed circuit at the supply voltage of 2.8 V and temperature of 27 °C. It takes about 0.6 ms to reach steady state. Monte Carlo 200 simulation runs have been done after layout parasitic extraction, considering the process variation and mismatch. The results are presented in Figure 7a. The mean value (μ) of the proposed BGR is 1.1689 V with the standard deviation (σ) of 4.6 mV, and the coefficient of variation is calculated to be about 0.39%. The simulated temperature dependence of the output reference voltage V_REF is plotted in Figure 7b. The temperature coefficient (TC) of the proposed BGR is 9.43 ppm/°C with temperature ranging from −20 to 80 °C.

The proposed BGR circuit is implemented in 0.35 μm standard CMOS process. Figure 8 shows the BGR micrograph of the die. The core circuit occupies an area of 0.063 mm², which could be optimized after an elaborate layout design. The total current consumption is measured as 78 nA on average from 30 samples. The digital clock generation block consumes 26 nA average current, which means that the percentage of the overhead power consumption by the clock generation block is 33.3% or one third. Figure 9 shows the distribution of the measured output voltage in 30 samples with 2.8 V supply voltage at 27 °C. The mean value (μ) is 1.167 V with the standard deviation (σ) of 8.1 mV. The proposed BGR can achieve an accuracy of 0.69% in the measurement. The accuracy of 0.69% is achieved without trimming and could be considered to be adequate for most implantable biomedical electronics. The low power feature is obtained due to the low duty cycle (D = 0.25%) operation of the on-off BRG. Moreover, the following correlated double sampler and the switched-RC filter just consume about 12 nA average current and occupy about 0.03 mm² chip area of the total 0.063 mm² chip area, but guaranteed the good performance of the on-off BRG. The on-off BGR achieves an untrimmed measured accuracy of 0.69%, which is comparable with the accuracy of BGRs with current consumptions of hundreds of times larger, just at a small price.

Figure 10 shows V_REF versus temperature ranging from −20 to 80 °C and the measured TC ranges from 13.7 ppm/°C to 38.2 ppm/°C with an average TC of 19.6 ppm/°C. Figure 11 shows the measured reference voltage versus the supply voltage at 27 °C. When the supply voltage changes from 1.8 V to 3.2 V, the BGR voltage variation is less than 0.83 mV. The reference voltage can achieve the line regulation of 0.59 mV/V. For measurement convenience, when measuring the power supply rejection ratio (PSRR), the on-off period is set at 10 ms instead of 100 ms, which will not affect the authenticity of the measured results. Figure 12 shows the PSRR results, which is better than 58.6 dB before 200 kHz. There are peaks at multiples of 100 Hz (1/10 ms) due to the characteristic of sampling. When the frequency of the fluctuation on the supply is the same as the sampling rate, the effect of the supply fluctuation on the sampled output voltage is also the same during the on phase in every sampling period and thus will be attenuated.

The performance of the proposed BGR circuit is summarized in

Table 1. Comparison table.

Parameter	[16]	[17]	[18]	[19]	This Work
Process	65 nm	180 nm	130 nm	180 nm	350 nm
Publication Year	JSSC 2017	TCAS-II 2015	ISSCC 2015	TCAS-II 2017	2019
Accuracy (σ/µ)	0.39%(T)	3.9%(UT)	0.67%(UT)	2%(T),1	0.69%(UT)
Type	VTH	VTH	VBE	VTH	VBE
TC (ppm/℃)	5.6(T)	64(T)	75(UT)	84.5(UT)	19.6(UT)
Supply	0.8 V	0.45 V	0.5 V	0.4 V	2.8 V
Output Voltage	428 mV	120 mV	500 mV	212 mV	1.17 V
Current Consumption	16.3 μA	32.4 nA	64 nA	480 nA	78 nA
Line regulation	1 mV/V	1.2 mV/V	10 mV/V	2 mV/V	0.59 mV/V

^(T): trimmed. ^(UT): untrimmed. ¹: 3σ.

, and these results are compared with other published references. From Table 1, it is observed that this work has the best line regulation and temperature coefficient in the untrimmed voltage references, while it also has advantages in the aspects of current consumption and untrimmed accuracy. However, the limitations of such on-off BGR are analyzed as follows. First, a small ripple at the switching moment still exists after switched-RC filtering. For continuous-time applications, this issue should be considered. Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.

4. Conclusions

An ultra-low power, high accuracy BGR designed for implantable medical electronics is presented in this paper. To solve the conflict between low power and high accuracy, an on-off bandgap combined with sample-and-hold switched-RC filter is developed. A higher working current is allowed to alleviate V_BE spread, which directly causes error to output voltage, but also keeps the average power consumption as low as 220 nW with the voltage supply of 2.8 V. Furthermore, to improve the accuracy ulteriorly, the error brought by the Opamp offset is eliminated by applying correlated double sampling strategy. As a result, the measured voltage accuracy of 0.69% is achieved without trimming, which is adequate for most implanted medical electronics. The circuit shows a line regulation of 0.59 mV/V in the supply voltage range of 1.8–3.2 V and a TC of 19.6 ppm/°C in the temperature ranging from −20 to 80 °C. The proposed BGR circuit meets all the requirements of implantable medical electronics. It is very suitable for application in biomedical systems.