# Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example

^{1}

^{2}

^{3}

^{*}

## Abstract

**:**

## 1. Introduction

_{m}) [22]. The electronic control of the voltage gain (A) [23] is also very important in many applications. Variable gain amplifiers (VGAs), referred to as AEs with a controllable A, can be obtained by the particular interconnection between OTAs and CCs [3,13,24] or are accessible as standalone commercial devices [25]. Variants of CCs with controllable internal parameters are also available. They usually allow for adjusting one of the following parameters: The resistance of the current input terminal (R

_{X}) [26], current gain (B) between terminals [27,28,29], and voltage gain (A) [30] between terminals.

_{x}and B [31,32,33,34]. These multiparametric features are beneficial especially for signal generation and filtering in order to extend the available range of tunability [34,35].

_{m}, R

_{x}, B) into one device can be found in Reference [43], where a modification of the VDCC (behavioral model) was presented. Many other concepts were introduced in References [3,4], and especially in Reference [13]. These AEs are described and compared to our design in detail in Section 2.

#### 1.1. Contribution of the Paper

- (1)
- (2)
- A new topology of CMOS MLT with a current output terminal is proposed. It contains additional linearizing blocks (not used in the most similar topology [48]) and a “current-boosting” OTA stage in order to increase dynamic range and decrease the linearity error. Note that the multiplier in Reference [48] operated with an input voltage range ±100 mV, but our CMOS MLT design provides ±500 mV. Therefore, the dynamics are significantly improved;
- (3)
- A standard Gilbert core-based [49] BJT MLT was designed in order to obtain a more accurate device than the CMOS MLT (in general, the accuracy of the CMOS design is a problem). It has a larger transconductance constant and better symmetry of output swing currents than the CMOS MLT does. Moreover, our BJT MLT concept, compared to Reference [48], has a current output terminal instead of a voltage output terminal. Thanks to the presence of two multipliers (CMOS and BJT) in our IC package, an extension of the controllability of new advanced AEs is possible;
- (4)
- Compared to Reference [50], a modified CCCII cell topology with full mirroring of currents from differential stage (pair) to four output terminals is presented. The main innovation is in specific biasing current reference generation for output mirrors and driving the value of R
_{X}(which was not the intention of Reference [50]). In contrast to our solution, the concept in Reference [50] is not capable of providing a large dynamic range and output cascoding due to its bias sources (voltage drop in real MOS elements) when very low supply voltage used; - (5)
- A current amplifier cell with a completely new topology, designed for low-power purposes, is presented. Good linearity in a dynamic range of ±200 µA, linear control of current gain, low input (around 1 Ω) and excellent output resistance, and low power consumption are the main advantages of the proposed concept.

#### 1.2. Organization of the Paper

## 2. Related Solutions of Modular Concepts

- (a)
- (b)
- (c)
- (d)
- (e)
- (f)

- (a)
- Five various cells (independent active cells implementing four different types of operations) are available;
- (b)
- (c)
- Four independent electronically controllable parameters of three types (2 g
_{m}, R_{X}, and B); and - (d)
- Differential and summing voltage operations as well as multiplicative operations are available.

- (a)
- Continuous electronic control is not available (FPAAs are tunable digitally in discrete steps);
- (b)
- Not favorable frequency features (the expected speed of applications and operation of signal paths up to tens of kHz);
- (c)
- High power consumption (in hundreds of mW);
- (d)
- Not a fully analog solution (additional mixed-mode subsystems and control circuits, including a clock signal, are required in an IC), and therefore the overall complexity is much higher; and
- (e)
- A high cost of available development kits.

## 3. A Developed Integrated Device for the Modular Design of Active Elements

#### 3.1. Voltage Differencing Differential Buffer (VDDB)

_{Y}

_{1}–V

_{Y}

_{3}, are processed to the output low-impedance terminal V

_{W}according to the following formula:

#### 3.2. Voltage Multipliers with Current Output (CMOS MLT, BJT MLT)

_{X}

_{1}, V

_{X}

_{2}and V

_{Y}

_{1}, V

_{Y}

_{2}) in the form of output current I

_{Z}. It has beneficial features for circuit synthesis, especially for the construction of lossy and lossless integrator blocks [21] employing grounded capacitors.

#### 3.3. Current-Controlled Current Conveyor of the Second Generation (CCCII)

#### 3.4. Current Amplifier with Controllable Current Gain (CA)

_{o}= B∙I

_{i}).

## 4. Experimentally Tested Features of the Proposed Cells

#### 4.1. The VDDB

#### 4.2. The CMOS MLT and BJT MLT

_{2}, Y

_{2}terminals are grounded, X

_{1}(signal input), Z (signal output (X

_{1}→ Z, indicated in Table A2)), and Y

_{1}(DC driving voltage); and (2) Y

_{1}(signal input), Z (signal output (Y

_{1}→ Z, indicated in Table A3)), X

_{1}(DC driving voltage), and X

_{2}, Y

_{2}are grounded. This configuration actually extended the concept of an OTA [21,22] because the operation of multiplication could be used for a simple change in the polarity of the output current. Table A2 indicates the expected differences between the simulated and measured transconductance values (g

_{m}-s). These differences were mainly caused by different values of k in the case of simulation (k ≅ –1.8 mA/V

^{2}) and measurement (k ≅ –1.3 mA/V

^{2}). This parameter significantly depended on temperature and fabrication mismatches. The inaccuracy resulted from a variation in the transconductance parameters of partial transistors (thermal voltage) and the non-equal bulk and source voltages (the threshold voltage is influenced) of differential pairs. The design recommendations of the CMOS process supposed that bulks are connected to the highest (P-type/channel MOS) or the lowest (N-type/channel MOS) voltage potentials in the circuit. Therefore, all bulks of NMOS elements are connected to negative supply voltage, and bulks of PMOS types are connected to positive supply voltage. Note that the dispersion of k was predicted from so-called process corner, supply voltage, and temperature variation (PVT) analyses. The experimentally obtained value fell into the expected range of possible deviation (see Figure 7). High input impedances (100 MΩ) represent an important advantage of this cell. In real experiments, the driving of transconductance was possible up to 660 μS. Deviation from the maximum simulated value (about 1000 μS) was given by the uncertainty of k. This was acceptable when fabrication mismatches were considered. The output impedances (real parts) remained above 100 kΩ for the highest value of driving DC voltage V

_{X}(the worst case). The measured linear dynamic input range was ±500 mV. The THD of the CMOS MLT reached, maximally, 1.5%. This was higher than in the case of the VDDB, but was still very acceptable.

^{2}(simulated) and k ≅ 4.9 mA/V

^{2}(measured). The obtained results (simulation and measurement), summarized in Table A3 (see Appendix A), indicated better accuracy and correspondence of simulated and measured transfer responses than in the case of the CMOS MLT. In comparison to the CMOS MLT solution, this represents a very important advantage. Input impedances achieved lower values in the BJT case (due to the bipolar input stage), but they were still sufficiently high for most of the applications. The input dynamic range with linear behavior was slightly higher, ±600 mV and ±700 mV in the simulation and from measurement, respectively. The frequency bandwidth of only 39 MHz could be considered to be some kind of limitation in particular cases, but it was obtained for a very low driving voltage. The range of possible transconductance controls was wider (measuring up to 2400 µS) than in the case of the CMOS MLT (measuring up to 660 µS). The output resistance achieved values >100 kΩ (even for the highest control voltages). The THD values were similar to the previous case. Exemplary DC and AC transfer responses are plotted in Figure 8.

#### 4.3. CCCII

_{1–4}) of the CCCII cell were from ±80 µA up to ±1700 µA, depending on the bias current I

_{set_Rx}(driving R

_{X}as R

_{X}≅ 3.5∙I

_{B}

^{–1/2}). Correspondence between Cadence and the experimental results in most of the DC/AC parameters was relatively high. In the worst case, the lowest usable frequency bandwidth was 37 MHz, but it was possible to reach 50 MHz for the highest I

_{set_Rx}at specific transfers.

_{set_Rx}setting (the worst case). Note that quite large levels of currents were supposed to be processed. Therefore, quiescent DC bias currents in the branches of the output stages were also quite high (hundreds of µA). The THD levels were maximally up to 0.1%. Selected features of the CCCII are shown in Figure 9.

_{X}(simulation: from 2320 Ω → 240 Ω) on I

_{s}

_{et_Rx}(see Table A4) was visible from 5 µA to 350 µA, but there was a significant difference between the simulation and measurement results. This was caused by a natural and expected change in the operation regime of transistors in the structure (the starts of this change in the case of simulations and in the case of a real circuit were different).

#### 4.4. CA

^{3}∙I

_{set_B}and can be adjusted by the DC driving current I

_{set_B}. The linearity of the DC transfer response was excellent (despite dynamics limited to ±200 µA), as well as input and output resistances are/were too. However, this cell targets low-power applications (the main purpose) and not speed. The frequency features of this cell were the worst from all units included in our IC (not overcoming 1.6 MHz, see Figure 10 (left)). A comparison of the real behavior of the CA cell (see Table A5) to Cadence design (nominal) showed the inaccuracy of DC as well as AC performances (Figure 10), especially for higher values of driving current I

_{set_B}. Its power consumption was the lowest of all of the designed cells (at least five times). This is the reason why this cell is appropriate for low-power applications. The current gain control was designed for an I

_{set_B}current (maximally 15 μA). Differences between the simulation and measurement results for I

_{set_B}> 15 μA are given through uncertainty of the setting of the operational regime of particular transistors in the topology (simulations). The evaluated distortion was not higher than 0.6% in the case of this cell.

## 5. Example Interconnection of Internal Cells: A Novel Advanced Active Element

_{m1}, R

_{X}, and g

_{m2}. Note that the outer terminals of the AE are distinguished from inner (cell) terminals by the symbol “ * ”. This AE is characterized by the following operation. MLT

_{1}transforms the differential input voltage from the p* and n* terminals to the current (through the controllable transconductance, g

_{m1}) flowing out of the auxiliary terminal z

_{a*}(I

_{Za*}= ± (V

_{p*}– V

_{n}

_{*})∙g

_{m1}). The voltage input Y of the CCCII is connected to this terminal to process the voltage drop at external impedance, which is connected to this terminal. The voltage at z

_{a*}also appears at the terminal X* (if not grounded). When the current is flowing through terminal X*, then relation V

_{X*}= V

_{Za*}+ R

_{X}I

_{X*}is valid (R

_{X}is also electronically controllable). The CCCII creates a direct copy of I

_{X*}(I

_{Zb*}= I

_{X*}) at the second auxiliary terminal, marked as Z

_{b}

_{*}. The voltage drop obtained at the external impedance, connected to this terminal, is again transformed to the current. It flows from MLT

_{2}(where the third controllable parameter g

_{m2}is available) at the x* terminal (I

_{x}

_{*}= ±V

_{Zb*}∙g

_{m2}). Note that the implementation of the MLTs in the AE concept allows for a simple change of polarity for the output currents I

_{Za*}, I

_{Zb*}, and I

_{x}

_{*}(i.e., transconductance polarity). We refer to this device as a current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA).

#### Application Example: CC-VDCCTA-Based Quadrature Oscillator

_{m2}≥ 1. The frequency of oscillation (FO) and the relation between generated signals are given respectively by Equations (4) and (5).

_{X}+ R

_{ex}

_{t}and g

_{m}

_{1}(g

_{m}

_{1}= 1/(R

_{X}+ R

_{ext})) ensures linear tuning of the FO while keeping output levels constant with the quadrature phase shift during the tuning process. Parameters g

_{m2}or R are suitable for automatized CO control (amplitude stabilization). Note that the circuit is able to operate without external R

_{ext}. However, direct grounding of the X terminal of the CC-VDCCTA causes operation with lower linearity. Therefore, THD also increases significantly. A small value of R

_{ext}increases linearity and the dynamics of signal processing.

_{0}= 159 kHz (oscillation frequency), C

_{1}= C

_{2}= C = 1 nF, R

_{x}= 420 Ω (I

_{set_Rx}= 100 µA), R

_{ext}= 82 Ω, and R = 4.7 kΩ. Next, calculations from Equation (4) lead to g

_{m}

_{1}= 1 mS (V

_{set_gm1}= 0.2 V). We designed and realized an amplitude stabilization circuit (CO control) of this oscillator (see Figure 14) based on the regulation of R. It was supplied from the node of C

_{2}and was used in all experimental tests. The circuit contained a high-input impedance adjustable amplifier with an OA and a voltage doubler/multiplier controlling the junction field effect transistor (J-FET)-based controllable resistor connected to the node of C

_{2}(in parallel to R = 4.7 kΩ). The value of g

_{m}

_{2}was kept to about 540 µS (V

_{set_gm2}= 0.3 V). The measured waveforms and their spectral analyses are shown in Figure 15.

_{0}= 164 kHz (very close to the expected 159 kHz). A spectral analysis yielded THD values of 0.8% and 1.3% (obtained for V

_{1}and V

_{2}, respectively).

_{0}is tuned by g

_{m}

_{1}(V

_{set_gm1}) and R

_{X}(R

_{X}+ R

_{ext}) simultaneously. Note that the low value of R

_{ext}= 82 Ω in these tests kept R

_{X}as a dominant source in the adjustment of f

_{0}. The value of R

_{X}+ R

_{ext}(connected actually in a series) was set from 500 Ω to 5 kΩ (I

_{set_Rx}= 100 → 10 µA), and the value of g

_{m}

_{1}was adjusted in the opposite direction, from 196 µS to 2 mS (V

_{set_gm1}= 0.041 → 0.41 V). When this setting was considered, the oscillator offered an ideal tuning range for the FO: f

_{0}= 32 kHz → 319 kHz (10:1). Cadence simulations yielded tunability from 43 kHz to 295 kHz (7:1), and the laboratory experiments provided the adjustment between 38 kHz and 337 kHz (9:1). The phase shift fluctuated around 90°, with a maximal deviation of ±2° in these bands. The amplitude levels, as well as their ratio, were almost constant during the measured FO tuning (see Figure 16 (right)).

_{m}

_{2}or R) for the implementation of the system for automatic amplitude stabilization, and (f) constant output levels and phase shift when oscillation frequency was tuned.

_{X}in the AE was not supposed. Interesting features were also available in the case of the solution presented in Reference [55]. However, this oscillator did not provide quadrature outputs with constant signal levels (when FO was tuned).

_{m}parameters) are not sufficient for fully linear tuning of frequency of oscillations even when we accept an unfavorable disturbance of the ratio of output amplitudes during the tuning procedure. The quadrature and linearly tunable solutions, employing OTAs, require at least four active devices (see Reference [59]) and, in addition, also an amplitude stabilization (AGC) as a circuit. From the viewpoint of the number of active devices, our solution brings a reduction in the needed number of active devices (when internal IC cells are counted as discrete parts).

_{set_Rx}is adjusted to the highest value in order to obtain the lowest R

_{X}value). This current distributor extends the number of output currents of both polarities when it is connected through the X terminal to the current output z of the MLT (forming the OTA part) in the IC package.

## 6. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## Appendix A

Parameters/Conditions | Simulation Results (Nominal Run) | Measured Results | Error (Measured vs Simulated) | Design Target |
---|---|---|---|---|

Small-signal AC transfer | ||||

K_{Y}_{1} → _{W} (−3 dB) | 1.00 [-] (51.6 MHz) | 1.02 [-] (55.4 MHz) | +2% (+7%) | 1 (≥30 MHz) |

K_{Y}_{2} → _{W} (−3 dB) | 1.00 [-] (54.3 MHz) | 1.02 [-] (61.6 MHz) | +2% (+13%) | 1 (≥30 MHz) |

K_{Y}_{3} → _{W} (−3 dB) | 1.00 [-] (51.3 MHz) | 1.01 [-] (45.1 MHz) | +1% (–12%) | 1 (≥30 MHz) |

Input dynamic range | ||||

Y_{1,2,3} → W | ≥ ±700 mV | ≥ ±700 mV | 0% | ≥±500 mV |

Input DC offset (Monte Carlo) | ||||

systematic + statistical (mismatch, 3 sigma; 99.7%) | real | |||

Y_{1,3} → W | −0.57 ± 20.5 mV | |10| mV | expected statistical range | - |

Y_{2} → W | −0.57 ± 20.5 mV | |10| mV | expected statistical range | - |

Total harmonic distortion (for input voltage 500 mV_{pk-pk}, 1 kHz) | ||||

THD _{Y}_{1,2,3→W} | <0.10% | - | <1% | |

Terminal impedances | ||||

R_{Y}_{1,2,3}, C_{Y1,2,3} | ≥1 GΩ, 2.8 pF | 100 MΩ, 13 pF | - | >50 kΩ |

R_{W}, L_{W} | 0.37 Ω, 4.3 µH | 0.54 Ω, 4.3 µH | - | <10 Ω |

measured quiescent power consumption: 9.1 mW |

**Basic principle**: The topology of the VDDB included an OA-based folded cascoded core. The difference between the standard topology in References [45,46] and our proposal consisted of the following: (a) additional differential NMOS and PMOS pairs (M

_{p}

_{3–4}, M

_{n}

_{3–4}) were used to obtain two additional voltage inputs, where one of them was used for full negative feedback. The low-impedance voltage output was solved as a class A source follower (M

_{9}).

Parameters/Conditions | Simulation Results (Nominal Run) | Measured Results | Error (Measured vs Simulated) | Design Target |
---|---|---|---|---|

Small-signal AC transfer | ||||

g_{m (X1} → _{Z}_{)} (−3 dB)for V _{Y}_{1} = ±0.05 → ±0.50 V | ±98 → ± 975 µS (≥53.0 MHz) | ±45 → ± 650 µS (≥30.0 MHz) | –54% → –33% (–43%) | ≥100 µS → ≥1000 µS (≥30 MHz) |

g_{m (Y1} → _{Z}_{)} (−3 dB)for V _{X}_{1} = ±0.05 → ±0.50 V | ±98 → ± 980 µS (≥44.0 MHz) | ±60 → ± 665 µS (≥44.0 MHz) | –39% → –32% (0%) | ≥100 µS → ≥1000 µS (≥30 MHz) |

Input DC dynamic range | ||||

X_{1} → Zfor V _{Y}_{1} = ± 0.05 → ± 0.50 V | ≥±500 mV | ≥±500 mV | 0% | ≥±500 mV |

Y_{1} → Zfor V _{X}_{1} = ± 0.05 → ± 0.50 V | ≥±600 mV | ≥±600 mV | 0% | ≥±500 mV |

Input DC offset (Monte Carlo) | ||||

systematic + statistical (mismatch, 3 sigma; 99.7%) | real maximum | |||

X_{1} → Z for V_{Y}_{1} = ± 0.5 V | 3.3 ± 63 mV | |6| mV | expected statistical range | - |

Y_{1} → Z for V_{X}_{1} = ±0.5 V | 3.2 ± 66 mV | |18| mV | expected statistical range | - |

Total harmonic distortion (for input voltage 500 mV_{pk-pk}, 1 kHz) | ||||

THD _{X}_{1} → _{Z} for V_{Y}_{1} = ± 0.1 V | ≤0.16% | - | <1% | |

THD _{X}_{1} → _{Z} for V_{Y}_{1} = ± 0.5 V | ≤0.14% | - | <1% | |

THD _{Y}_{1} → _{Z} for V_{X}_{1} = ± 0.1 V | ≤1.45% | - | <1% | |

THD _{Y}_{1} → _{Z}for V_{X}_{1} = ± 0.5 V | ≤0.45% | - | <1% | |

Terminal impedances | ||||

R_{X1}, C_{X}_{1} for all V_{Y}_{1} | ≥1 GΩ, 2.5 pF | 100 MΩ, 10–24 pF | - | >50 kΩ |

R_{Y1}, C_{Y1} for all V_{X}_{1} | ≥1 GΩ, 2.5 pF | 100 MΩ, 14 pF | - | >50 kΩ |

R_{Z}, C_{Z} for V_{X}_{1} = ± 0.50 V | 1.55 MΩ, 5.3 pF | ≥100 kΩ, 16.2 pF | - | >50 kΩ |

measured quiescent power consumption: 7.8 mW |

**Basic principle**: Two input differential voltages were processed by linearizing segments (M

_{x}

_{1-2}and M

_{y}

_{1-2}) in order to extend the linear range of the DC transfer. Each linearizing segment worked as an operational transconductance amplifier with very low but highly linear (from the viewpoint of signal level) transconductance (practically given by degradation resistor R

_{b}, and therefore high linearity between the input differential voltage and the output current was ensured) with a differential current output that performed differential output voltage at two identical resistive loads. Then, both output voltages were connected to the multiplying core (the basic concept introduced in Reference [48]). A boosting OTA section (differential pair M

_{7–8}) was used because of the low output level (low gain) of the current (tens of µA instead of hundreds of µA) when the output of the multiplying core, through appropriate current mirrors, was taken directly out.

Parameters/Conditions | Simulation Results (Nominal Run) | Measured Results | Error (Measured vs Simulated) | Design Target |
---|---|---|---|---|

Small-signal AC transfer | ||||

g_{m}_{(X1} → _{Z)} (-3 dB)for V _{Y}_{1} = ± 0.05 → ±0.50 V | ±222 → ±2220 µS (≥53.0 MHz) | ±250 → 2340 µS (≥52.0 MHz) | +13% → +5% (–2%) | ±200 → ± 2000 µS (≥30 MHz) |

g_{m}_{(Y1} → _{Z}_{)} (-3 dB)for V _{X}_{1} = ±0.05 → ±0.50 V | ±222 → ±2210 µS (≥53.0 MHz) | ±250 → 2350 µS (≥39.0 MHz) | +13% → +6% (–26%) | ±200 → ± 2000 µS (≥30 MHz) |

Input DC dynamic range | ||||

X_{1} → Zfor V _{Y1} = ±0.05 → ±0.50 V | ≥±600 mV | ≥±700 mV | +17% | ≥±500 mV |

Y_{1} → Zfor V _{X}_{1} = ±0.05 → ±0.50 V | ≥±600 mV | ≥±700 mV | +17% | ≥±500 mV |

Input DC offset (Monte Carlo) | ||||

systematic + statistical (mismatch, 3 sigma; 99.7%) | real maximum | |||

X_{1} → Z for V_{Y}_{1} = ±0.5 V | −1.4 ± 29 mV | |14| mV | expected statistical range | - |

Y_{1} → Z for V_{X}_{1} = ±0.5 V | −1.3 ± 29 mV | |15| mV | expected statistical range | - |

Total harmonic distortion (for input voltage 500 mV_{pk-pk}, 1 kHz) | ||||

THD _{X}_{1} → _{Z} for V_{Y}_{1} = ±0.1 V | ≤0.32% | - | <1% | |

THD _{X}_{1} → _{Z} for V_{Y}_{1} = ±0.5 V | ≤0.47% | - | <1% | |

THD _{Y}_{1} → _{Z} for V_{X}_{1} = ±0.1 V | ≤0.17% | - | <1% | |

THD _{Y}_{1} → _{Z}for V_{X}_{1} = ±0.5 V | ≤0.44% | - | <1% | |

Terminal impedances | ||||

R_{X1}, C_{X}_{1} for all V_{Y}_{1} | 129 kΩ, 2.8 pF | 176 kΩ, 18.3 pF | - | >50 kΩ |

R_{Y1}, C_{Y}_{1} for all V_{X}_{1} | 127 kΩ, 2.8 pF | 173 kΩ, 15.4 pF | - | >50 kΩ |

R_{Z}, C_{Z} for V_{X}_{1} = ±0.50 V | 803 kΩ, 3.9 pF | ≥100 kΩ, 16.1 pF | - | >50 kΩ |

measured quiescent power consumption: 9.5 mW |

**Basic principle:**This cell was prepared for high-precision applications (inaccuracies in CMOS MLT were expected). In accordance with Reference [49], a linearizing segment was applied to one differential voltage, and the linearizing procedure was different than with the CMOS MLT. It uses exponential/logarithmic dependence of the collector current on base-emitter voltage and linearization of the g

_{m}(differential pair) stage by the degradation resistor (R

_{a}). The attenuation of the signal through the linearizing segment was less significant than with the CMOS MLT. The boosting OTA is also presented in this case due to the same reasons as with the CMOS MLT. In our design, for the highest bandwidth, it was always better to use an additional block than increase the current mirror ratio to a value of 1:100 (a high increase in the C

_{gs}parasitic capacity in the node of the current mirror and drop of bandwidth).

**Figure A4.**Full CMOS topology of the current-controlled current conveyor of the second generation (CCCII).

Parameters/Conditions | Simulation Results (Nominal Run with Input/Output Capacity 5 pF) | Measured Results | Error (Measured vs Simulated) | Design Target |
---|---|---|---|---|

Small-signal AC transfer | ||||

K_{X} → z_{1} (−3 dB) for I_{set_Rx} = 350 µA | 1.00 [-] (49.6 MHz) | 0.98 [-] (51.5 MHz) | –2% (+9%) | 1 (≥30 MHz) |

K_{X} → z_{2} (−3 dB) for I_{set_Rx} = 350 µA | 1.00 [-] (49.6 MHz) | 0.98 [-] (47.5 MHz) | –2% (–4%) | 1 (≥30 MHz) |

K_{X} → z_{3} (−3 dB) for I_{set_Rx} = 350 µA | 0.93 [-] (41.1 MHz) | 1.00 [-] (37.0 MHz) | +7% (–10%) | 1 (≥30 MHz) |

K_{X} → z_{4} (−3 dB) for I_{set_Rx} = 350 µA | 0.93 [-] (41.1 MHz) | 1.00 [-] (38.7 MHz) | +7% (–5%) | 1 (≥30 MHz) |

K_{Y} → _{X} (−3 dB) for I_{set_Rx} = 350 µA | 1.00 [-] (52.1 MHz) | 1.00 [-] (49.7 MHz) | 0% (–5%) | 1 (≥30 MHz) |

GBW_{X} → _{Z}_{1} for I_{set_Rx} = 10→350 µA | 12.7 → 49.6 MHz | 11 → 51.5 MHz | –13% → +4% | - |

GBW_{X} → _{Z}_{2} for I_{set_Rx} = 10→350 µA | 12.7 → 49.6 MHz | 9.8 → 47.5 MHz | –23% → –4% | - |

GBW_{X} → _{Z}_{3} for I_{set_Rx} = 10→350 µA | 10.8 → 41.1 MHz | 7.8 → 37 MHz | –28% → –10% | - |

GBW_{X} → _{Z}_{4} for I_{set_Rx} = 10→350 µA | 10.8 → 41.1 MHz | 8 → 38.7 MHz | –26% → –6% | - |

GBW_{Y} → _{X} for I_{set_Rx} = 10→350 µA | 11.9 → 52.1 MHz | 6.1 → 49.7 MHz | –49% → –5% | - |

Input DC dynamic range | ||||

X → Z_{1-4} for I_{set_Rx} = 10 → 350 µA | ±80 → ±1700 µA | ±99 → ±1700 µA | +24% → +0% | ±100 → ±1000 µA |

Y → X for I_{set_Rx} = 10, 350 µA | ≥±500 mV | ≥±1000 mV | +100% | ≥±500 mV |

Input DC offset (Monte Carlo) | ||||

systematic + statistical (mismatch, 3 sigma; 99.7%) | real | |||

X → Z_{1} for I_{set_Rx} = 100 µA | 0.047 ± 8.2 µA | −5.4 µA | expected stat. range | - |

X → Z_{2} for I_{set_Rx} = 100 µA | 0.047 ± 8.2 µA | −0.05 µA | expected stat. range | - |

X → Z_{3} for I_{set_Rx} = 100 µA | −0.043 ± 12.0 µA | 0.65 µA | expected stat. range | - |

X → Z_{4} for I_{set_Rx} = 100 µA | −0.043 ± 12.0 µA | −0.64 µA | expected stat. range | - |

Y → X for I_{set_Rx} = 100 µA | 0.336 ± 3.771 mV | 2.5 mV | expected stat. range | - |

Total harmonic distortion | ||||

THD _{X} → z_{1,2} for I_{set_Rx} = 50, 350 µA(for input current 100 µA _{pk-pk}, 1 kHz) | 0.04, 0.07% | - | <1% | |

THD _{X} → z_{3,4} for I_{set_Rx} = 50, 350 µA(for input current 100 µA _{pk-pk}, 1 kHz) | 0.003, 0.11% | - | <1% | |

THD _{Y} → _{X} for I_{set_Rx} = 50 and 200 µA(for input voltage 500 mV _{pk-pk}, 1 kHz) | 0.08, 0.07% | - | <1% | |

Terminal impedances | ||||

R_{X}, C_{X} for I_{set_Rx} = 5 → 350 µA | 2320 → 240 Ω, 10 pF | 6670 → 280 Ω, 20 pF | +188% → +17% | 2500 → 250 Ω |

R_{Y}, C_{Y} for all I_{set_Rx} | ≥1 GΩ, 2.7 pF | 100 MΩ,14.5 pF | - | >50 kΩ |

R_{z1,2}, C_{z1,2} for I_{set_Rx} = 5 µA | 52 MΩ, 4.8 pF | 100 MΩ, 15.9 pF | - | >50 kΩ |

R_{z1,2}, C_{z1,2} for I_{set_Rx} = 350 µA | 44 kΩ, 4.8 pF | 66 kΩ, 15.9 pF | - | >50 kΩ |

R_{z3,4}, C_{z3,4} for I_{set_Rx} = 5 µA | 106 MΩ, 2.5 pF | 100 MΩ, 15.9 pF | - | >50 kΩ |

R_{z3,4}, C_{z3,4} for I_{set_Rx} = 350 µA | 49 kΩ, 2.5 pF | 82 kΩ, 15.9 pF | - | >50 kΩ |

measured quiescent power consumption: 16.8 mW |

**Basic principle:**The topology of the CCCII was based on a differential pair (M

_{1-2}) with full negative feedback that allowed for a simple control of terminal resistance X as an inversely proportional function of g

_{m}by bias current. Then, the current difference of the differential pair was taken out by cascoded current mirrors. The ideal scheme of this idea is shown in Reference [50], but our solution had some significant modifications. One of them consists in the full mirroring of currents from the differential pair. Then, symmetrical dynamics of the current and voltage responses (no DC drop on bias sources) was available. The next modification included cascoded and multiple current outputs.

Parameters/Conditions | Simulation Results (Nominal Run) | Measured Results | Error (Measured vs Simulated) | Design Target |
---|---|---|---|---|

Small-signal AC transfer | ||||

K_{(i → o)} [-] for I_{set_B} = 1→22.5 µA | 0.08 → 6.35 | 0.07 → 2.14 | –12% → –8% | 0.1 → 1.0 |

K_{(i → o)} [dB] (−3 dB) for I_{set_B} = 1 µA | –22.3 → 16 dB (0.69 → 2.89 MHz) | –23.4 → 6.6 dB (0.46 → 1.56 MHz) | –12% → –66% | |

B [-] for I_{set_B} = 1 → 22.5 µA | 0.076 → 6.346 | 0.067 → 2.138 | +5% → –59% | |

GBW _{i→o} for I_{set_B} = 1 → 22.5 µA | 0.69 → 2.89 MHz | 0.46 → 1.56 MHz | –33% → –46% | ≥100 kHz |

Input dynamic range | ||||

I → o for I_{set_B} = 1 → 22.5 µA | ≥±200 µA | ≥±180 µA | –10% | ≥±150 µA |

Input DC offset (systematic) | ||||

I → o for I_{set_B} = 1 → 22.5 µA | 0.04 → 0.06 µA | 6 → −9 µA | expected stat. range | - |

Total harmonic distortion (for input current 100 µA A_{pk-pk}, 1 kHz) | ||||

THD _{I} → o for I_{set_B} = 12.5 µA | 0.14% | - | <1% | |

Terminal (input/output) impedances | ||||

R_{i}, L_{i} for all I_{set_B} | 0.91 Ω, 31 µH | 1.4 Ω, 42 µH | - | <10 Ω |

R_{o}, C_{o} for I_{set_B} = 1 → 22.5 µA | 80 MΩ → 59 kΩ, 3.9 pF | 30 MΩ → 3 MΩ, 14.1 pF | - | >1 MΩ |

measured quiescent power consumption: 1.7 mW |

**Basic principle:**A part of this cell used a very similar but not identical to principle of CCCII. The input stage (see top part of Figure A5) consisted of an OTA section with a full negative feedback. After processing and DC-shifting the signal in both polarities, the current gain-controlling part was connected (see bottom part of Figure A5). Both branches were tied together in the output stage, including current mirrors.

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**Figure 1.**The fabricated IC: (left) contents on a cell level and (right) an illustration of the top layout design.

**Figure 2.**Schematic symbol and interterminal transfer relation of the voltage differencing differential buffer (VDDB).

**Figure 3.**Schematic symbol and description of the ideal interterminal transfer relation of the voltage multiplier to the current output CMOS MLT (left) and BJT MLT (right).

**Figure 4.**Schematic symbol and description of the ideal interterminal transfer relations of the current-controlled current conveyor of the second generation (CCCII).

**Figure 5.**Schematic symbol and description of the ideal interterminal transfer relations of the adjustable current amplifier (CA).

**Figure 6.**Selected results of the measured and simulated responses of the VDDB: (left) DC transfer responses Y1–3 → W; (right) magnitude AC transfer responses Y1–3 → W.

**Figure 7.**Selected results of the measured and simulated responses of the CMOS MLT: (left) DC transfer responses Y

_{1}→ Z for a V

_{X1}controlled by DC voltage; (right) magnitude of AC transfer responses Y

_{1}→ Z for a V

_{X1}controlled by DC voltage.

**Figure 8.**Selected results of the measured and simulated responses of the BJT MLT: (left) DC transfer responses X

_{1}→ Z for a V

_{Y1}controlled by DC voltage; (right) magnitude of AC transfer responses X

_{1}→ Z for a V

_{Y1}controlled by DC voltage.

**Figure 9.**Selected results of the measured and simulated responses of the CCCII: (left) DC response of the Y → X transfer; (right) AC responses of X → z

_{1–2}transfers.

**Figure 10.**Selected results of the measured and simulated responses of the CA: (left) AC responses of i → o transfers; (right) dependence of B on I

_{set_B}.

**Figure 11.**Example of the interconnection of three cells of the fabricated IC, defining an advanced active element (AE) with three adjustable parameters: a so-called current-controlled voltage differencing current conveyor transconductance amplifier (CC-VDCCTA).

**Figure 13.**PCB for experimental verification of applications with fabricated chips shown in case of using only one IC package as discussed in the paper (implementation of the designed oscillator).

**Figure 15.**Experimental results for the oscillator: (left) output waveforms; (middle) spectral analysis of V

_{1}; (right) spectral analysis of V

_{2}.

**Figure 16.**Measured dependences with linear tuning of the frequency of oscillation (FO) of the oscillator: (left) f

_{0}versus simultaneous control of g

_{m1}(V

_{set_gm1}) and R

_{x}(I

_{set_Rx}); (right) amplitude levels of V

_{1}and V

_{2}versus f

_{0}.

**Table 1.**Comparison of typical examples of commercially available devices to relevant customized modular IC devices.

References | Number of Cells (Internal Subparts) | Types of Cells (Number and Purpose of Terminals) | Independent Cells (No Internal Interconnection) | Variability in Interconnection | Electronically Controllable Parameters | Number of Electronically Controllable Parameters | Types of Electronically Controllable Parameters | Differential/Summing Voltage Operations Available | Multiplicative Operations | Technology (Fabrication Process) |
---|---|---|---|---|---|---|---|---|---|---|

[20] | 2 | 1 current conveyor (1 voltage input, 1 current input, 1 current output); | Yes | Yes | No | 0 | - | No | No | BJT commercial |

1 voltage buffer (1 input, 1 output) | ||||||||||

[36,37] | 2 | 1 current-controlled current conveyor (1 voltage input, 1 current input, 2 current outputs); | Yes | Yes | Yes | 2 | 1 g_{m}, 1 R_{X} | No | Yes | CMOS 0.7-µm |

1 CMOS multiplier (4 voltage inputs, 1 current output) | ||||||||||

[38] | 2 | 1 current conveyor (1 voltage input, 1 current input, 1 current output); | No | No | No | 0 | - | No | No | BJT commercial |

1 voltage buffer (1 input, 1 output) | ||||||||||

[39,40] | 2 | 1 universal multiterminal current conveyor (3 voltage inputs, 1 current input, 4 current outputs); | Yes | Yes | No | 0 | - | Yes | No | CMOS 0.35-µm |

1 current conveyor (1 voltage input, 1 current input, 1 current output) | ||||||||||

[41] | 2 | 1 current conveyor (1 voltage input, 1 current input, 1 current output); | Yes | Yes | Yes | 1 | g_{m} | No | No | CMOS 0.7-µm |

1 OTA stage (2 voltage inputs, 1 current output) | ||||||||||

[42] | 5 | 2 current differentiators (2 current inputs, 1 current output); 2 current conveyors (1 voltage input, 1 current input, 1 current output); | Yes | Yes | Yes | 4 | g_{m} | No | No | CMOS 0.7-µm |

1 OTA stage (2 voltage inputs, 1 current output) | ||||||||||

This work | 5 | 1 VDDB (3 voltage inputs, 1 voltage output); | Yes | Yes | Yes | 4 | 2 g_{m}, 1 R_{X}, 1 B | Yes | Yes | CMOS/BJT 0.35-µm |

1 current-controlled current conveyor (1 voltage input, 1 current input, 4 current outputs); | ||||||||||

1 CMOS multiplier (4 voltage inputs, 1 current output); | ||||||||||

1 BJT multiplier (4 voltage inputs, 1 current output); 1 current amplifier (1 current input, 1 current output) |

_{m}, transconductance; R

_{X}, resistance of current input terminal; B, current gain. Note that the simplest solutions [20,38] (commercially available devices) were added only for comparison purposes, and they are not typical representatives of complex modular ICs. CMOS: complementary metal–oxide–semiconductor; OTA: operational transconductance amplifier; VDDB: voltage differencing differential buffer.

**Table 2.**A comparison of recently published and the most similar electronically controllable quadrature oscillators based on a single active element and a grounded capacitor.

References | Active Elements | No. of Auxiliary High Impedance Terminals Z | No. of Controllable Parameters of Device | No. of Passive Elements | Parameters for f_{0} Control | Trend of Electronic Tunability | Fulfillment of CO Given by Parameter | No. of Parameters Suitable for CO Control | FO and CO Fully Uncoupled | Constant Output Amplitude While f_{0} Is Tuned | Chip Area/Cell Area (mm^{2}) | Power Consumption (Full IC/ Cells) (mW) |
---|---|---|---|---|---|---|---|---|---|---|---|---|

[36] | VDCC | 1 | 2 | 4 | g_{m} | nonlinear | R value^{a} | 1 | Yes | No | 4/0.79 | -/45 |

[55] | ZC-CG-VDCC | 1 | 3 | 4 | g_{m}, R_{X} | linear | B | 1 | Yes | No^{b} | N/A | -/7 |

[56] | VDTA | 1 | 2 | 3 | g_{m} | nonlinear | R value^{a} | 1 | Yes | No | N/A | N/A |

[57] | DVCCTA | 1 | 1^{c} | 5 | g_{m}, R_{X} | N/A | R value^{a} | 2 | Yes | N/A | N/A | N/A |

[58] | DDTA | 1 | 1 | 3 | g_{m} | nonlinear | C value | 0 | No | N/A | N/A | N/A |

Figure 11 | CC-VDCCTA | 2 | 3 | 4 | g_{m1}, R_{X} | linear | g_{m2}, R value^{a} | 2 | Yes | Yes | 2.34/0.35 | 45/34 |

_{m}: transconductance; R

_{X}: resistance of current input terminal; B: adjustable current gain.

^{a}Value of passive element.

^{b}Multiphase type of oscillator where quadrature output is also available: However, constant amplitudes (when tuned) are generated only with a 45°phase shift.

^{c}R

_{X}not implemented in the AE as electronically controllable (R

_{X}= external passive element), and electronic FO tunability available in nonlinear form only (but not tested).

**Table 3.**Brief comparison of the selected important measured features of the proposed cells included in the IC.

Cell | Frequency Features (Bandwidth) ^{a} | DC Features and Linearity (Dynamics) | Input Impedance | Output Impedance | Quiescent Power Consumption ^{a} | Accuracy of Simulation Results with Results of Experiments (Design Stage) |
---|---|---|---|---|---|---|

VDDB | Good (>45 MHz) | Good (±700 mV) | High (100 MΩ) | Low (good) (0.5 Ω) | Average (9.1 mW) | High |

CMOS MLT | Average (>30 MHz) | Good (±500 mV) | High (100 MΩ) | Average (>100 kΩ) | Average (7.8 mW) | Within expected range (process variation) |

BJT MLT | Good (>40 MHz) | Good (±700 mV) | Average (170 kΩ) | Average (>100 kΩ) | Average (9.5 mW) | Good |

CCCII | Good (>37 MHz) | Good (±500 mV, Y) (to ±1700 µA, X) | High (100 MΩ, Y) Average (0.28 → 3.4 kΩ, X) | Average (>60 kΩ) | High (16.8 mW) | Good |

CA | Low (<1.6 MHz) | Average (but excellent linearity) (±180 µA) | Low ^{b} (1.4 Ω) | High (good) (>3 MΩ) | Low (1.7 mW) | Average |

^{a}in frame of the IC device;

^{b}this is a significant advantage in the case of CA.

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

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Sotner, R.; Jerabek, J.; Polak, L.; Prokop, R.; Kledrowetz, V.
Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example. *Electronics* **2019**, *8*, 568.
https://doi.org/10.3390/electronics8050568

**AMA Style**

Sotner R, Jerabek J, Polak L, Prokop R, Kledrowetz V.
Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example. *Electronics*. 2019; 8(5):568.
https://doi.org/10.3390/electronics8050568

**Chicago/Turabian Style**

Sotner, Roman, Jan Jerabek, Ladislav Polak, Roman Prokop, and Vilem Kledrowetz.
2019. "Integrated Building Cells for a Simple Modular Design of Electronic Circuits with Reduced External Complexity: Performance, Active Element Assembly, and an Application Example" *Electronics* 8, no. 5: 568.
https://doi.org/10.3390/electronics8050568