# Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

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## Abstract

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## 1. Introduction

## 2. Single Gate Planar Junctionless Transistors

#### 2.1. Physical Structure of PJLT

#### 2.2. Working Principle of Single Gate PJLT

## 3. An Approximated Model for the Depletion Region

## 4. Analysis and Simulations of the Approximated Model

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A. Depletion Region Width Analytical Formula

## References

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**Figure 1.**N-type PJLT physical structure; (

**a**) complete structure on FDSOI wafer; (

**b**) simplified model of the JLT physical structure.

**Figure 3.**N-type PJLT working principle. (

**a**) state of the PJLT for a generic value of gate voltage; (

**b**) depletion region for different values of gate voltage.

**Figure 4.**Analytical depletion width as a function of the gate voltage computed with the data in Table 1. (

**a**) N-type PJLT; (

**b**) P-type PJLT.

**Figure 5.**Profiles of the main parameters characterizing the depletion region in an n-type PJLT. (

**a**) PJLT in capacitor configuration with source and drain sufficiently far from each other to consider the depletion region boundary uniform in the middle of the device layer; (

**b**) impurity ions distribution inside the device layer (complete ionization); (

**c**) carrier distribution inside the device layer (blue line = hole distribution, green line = real electron distribution, red line = ideal electron distribution); (

**d**) charge density inside the device layer ( green line = real charge density distribution, red line = ideal charge density distribution).

**Figure 7.**Comparison between the ideal and the simulated electron concentration inside the device layer, for different values of gate voltage. The parameter of the simulated structure are shown in Table 1. The PJLT was electrically connected as shown in Figure 3. $x=0$ is placed at the interface $Si{O}_{2}$/substrate. (

**a**) Profiles for ${V}_{G}=-0.25$ V. (

**b**) Profiles for ${V}_{G}=-0.75$ V. (

**c**) Profiles for ${V}_{G}=-2$ V. (

**d**) Profiles for ${V}_{G}=-3$ V. (

**e**) Profiles for ${V}_{G}=-4$ V. (

**f**) Profiles for ${V}_{G}=-4.5$ V.

**Figure 8.**Comparison between the ideal and the simulated charge density inside the device layer, for different values of gate voltage. The parameters of the simulated structure are shown in Table 1. The PJLT was electrically connected as shown in Figure 3. $x=0$ is place at the interface $Si{O}_{2}$/substrate. (

**a**) Profiles for ${V}_{G}=-0.25$ V. (

**b**) Profiles for ${V}_{G}=-0.75$ V. (

**c**) Profiles for ${V}_{G}=-2$ V. (

**d**) Profiles for ${V}_{G}=-3$ V. (

**e**) Profiles for ${V}_{G}=-4$ V. (

**f**) Profiles for ${V}_{G}=-4.5$ V.

**Figure 9.**RMS error between the ideal and the simulated electron concentration profile inside (${\u03f5}_{RMSi}$) and outside (${\u03f5}_{RMSo}$) the depletion region, normalized in respect to ${N}_{D}$.

**Figure 10.**(

**a**) electron concentration profiles for different values of gate voltage; (

**b**) charge density profiles for different values of gate voltage. The circles represents the value of electron concentration and charge density at the ideal boundary of the depletion region. The gate voltage was swept in the range [−0.25 V,−4.5 V] with a step of 0.25 V.

**Figure 11.**(

**a**) electron concentration at the boundary of the ideal depletion region for different values of gate voltage; (

**b**) charge density at the boundary of the ideal depletion region for different values of gate voltage; (

**c**) relative error between the data in (

**a**) and polynomial approximations of fourth, sixth, and eighth order; (

**d**) relative error between the data in (

**b**) and polynomial approximations of fourth, sixth, and eighth order. The gate voltage was swept in the range [−0.25 V,−4.5 V] with a step of 0.25 V.

**Figure 12.**Electron concentration generated by COMSOL Multiphysics. ${V}_{G}=-2$ V and ${V}_{D}=3$ V. The black line represents the boundary of the depletion region. (

**a**) whole PJLT; (

**b**) zoom on a specific area of the PJLT.

**Figure 13.**Comparison between the “common sense” model and the approximated analytic model. (

**a**) detection of the electron concentration at the boundary of the depletion region defined by the “common sense” model for different values of gate voltage; (

**b**) comparison between the depletion region estimated by the “common sense” model and the depletion region estimated by using the approximated analytic model described in Equation (4). The gate voltage was swept in the range [−0.25 V,−4.5 V] with a step of 0.25 V.

n-Type PJLT | p-Type PJLT | |
---|---|---|

Parameter | Value | |

Materials | ||

Device layer | Si/n-type | Si/p-type |

insulating gate layer | $Si{O}_{2}$ | |

Gate electrode | N-type Poly-Si | P-type Poly-Si |

Material proprieties | ||

Device layer Doping concentration (atoms/cm${}^{3}$) | ${N}_{D}={10}^{19}$ | ${N}_{A}=3.05\times {10}^{18}$ |

Intrinsic carrier concentration: ${n}_{i}$ (atoms/cm${}^{3}$) | $5.4\times {10}^{9}$ at 293.15 K | |

Dielectric constant device layer: ${\u03f5}_{Si}$ (F/cm) | $11.7{\u03f5}_{0}$ | |

Dielectric constant insulator: ${\u03f5}_{ox}$ (F/cm) | $3.9{\u03f5}_{0}$$\left(Si{O}_{2}\right)$ | |

Dimensions | ||

Channel length: ${L}_{ch}$ (nm) | 500 | |

Device layer thickness: ${t}_{Si}$ (nm) | 10 | |

Gate oxide thickness: ${t}_{ox}$ (nm) | 8 | |

Derived Parameters | ||

Electron affinity: $q\chi $ (eV) | 4.05 | |

Energy band gap: ${E}_{g}$ (eV) | 1.13 | |

Bulk potential: $q{\Phi}_{n,p}={k}_{B}T\phantom{\rule{0.166667em}{0ex}}ln({N}_{D,A}/{n}_{i})$ (eV) | 0.539 | 0.509 |

Oxide capacitance per unit area: ${C}_{ox}={\u03f5}_{ox}/{t}_{ox}$ (F/cm${}^{2}$) | $4.32\times {10}^{-7}$ | |

Gate work function: $q{\Phi}_{M}$ (eV) | 4.05 (PolySi/n-type) | 5.15 (PolySi/p-type) |

Flat Band Voltage: ${V}_{FB}$ (V) | −0.026 | 0.026 |

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**MDPI and ACS Style**

Nowbahari, A.; Roy, A.; Nadeem Akram, M.; Marchetti, L.
Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors. *Electronics* **2019**, *8*, 1436.
https://doi.org/10.3390/electronics8121436

**AMA Style**

Nowbahari A, Roy A, Nadeem Akram M, Marchetti L.
Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors. *Electronics*. 2019; 8(12):1436.
https://doi.org/10.3390/electronics8121436

**Chicago/Turabian Style**

Nowbahari, Arian, Avisek Roy, Muhammad Nadeem Akram, and Luca Marchetti.
2019. "Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors" *Electronics* 8, no. 12: 1436.
https://doi.org/10.3390/electronics8121436