Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor

Abstract

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on–off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

1. Introduction

A continuous scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) has enabled integrated circuit (IC) chips to be fabricated with more functionality and at a lower cost [1,2]. Currently, multi-gated (MG) FETs (e.g., FinFETs) have replaced conventional FETs, which face a physical limit on scaling owing to short-channel effects [3]. Moreover, FinFETs also have a theoretical limit on subthreshold swing (S), since they are based on Boltzmann statistics as well. Therefore, a decrease in power consumption through the maintenance of a high on–off current ratio (I_on/I_off) is a huge technical challenge for future complementary MOS (CMOS) technology.

A tunnel FET (TFET) has been regarded as one of the most promising candidates for the next-generation low-power devices, because it can achieve a subthreshold swing of 60 mV/decade at room temperature [4,5]. Most studies about TFETs have mainly focused on improving their performance in terms of I_on, S, etc. by changing their structures and materials of devices [6,7,8,9]. Moreover, most TFETs use silicon-on-insulator (SOI) structures; therefore, it is very important to understand how a back-gate bias (V_bg) affects the operation of TFETs. A few studies have reported that back-gate biases change the transfer characteristics of TFETs [8,10]. However, no in-depth analysis has yet been conducted on how a back-gate bias affects S specifically. Therefore, in this study, the subthreshold characteristics of a back-gated TFET are extensively analyzed by means of technology computer-aided design (TCAD) simulation. Through this simulation, it is shown, for different back-gate biases, the channel potential changes with gate bias, along with the mechanism behind this change. The results thus obtained were used to analyze the influence of back-gate bias on the transfer characteristics of the TFET, especially the subthreshold swing.

2. Simulation Conditions

The device structure studied in this work is shown in Figure 1. In order to improve current drivability with the help of pseudo-direct band-to-band tunneling (BTBT) model, a p-type source and a channel are made of Ge [9]. On the other hand, a Si drain is used for suppressing a leakage current due to the ambipolar behavior (I_amb) and the Shockley–Read–Hall (SRH) recombination observed in TFETs. As well as the top-gate oxide of a 1 nm thick SiO₂ layer, the back-gate electrode is also separated from the Ge channel, using the same thickness of SiO₂ to prevent the substrate leakage current, through the forward-biased source to the substrate junction; in this case, the substrate is negatively biased. The work functions for both the top and back gates are 4.05 eV. The other device design parameters are summarized in

Table 1. Device parameters used in technology computer-aided design (TCAD) simulation.

Parameter	Description	Unit	Value
Lgate	gate length	nm	50
Tox	equivalent oxide thicknesses of top- and back-gate oxides	nm	1
Xj	junction depth	nm	10
TB	body thickness	nm	50
NS	source doping concentration	/cm3	1020
ND	drain doping concentration	/cm3	1020
NB	body doping concentration	/cm3	1017

. In order to rigorously examine the BTBT behavior, a dynamic nonlocal BTBT model was used for TCAD simulation after calibration [11,12]. In addition, both indirect and direct BTBTs were considered in this simulation [7,9,11].

3. Results and Discussions

Figure 2 shows drain current (I_d) as a function of top-gate voltage (V_tg) for different values of V_bg. Different drain voltages (V_ds) of 0.05 V and 0.5 V were applied as shown in Figure 2a,b, respectively. Two noteworthy phenomena were discussed below.

First, a comparison of Figure 2a,b clarified that a higher V_ds contributed to a lower minimum S. Furthermore, it was also observed that, as V_ds increased_, the channel inversion voltage (V_inv) increased. V_inv is defined as the value of V_tg required for the formation of an inversion layer [9]. It was observed that, similar to those of MOSFETs, the surface potential of the TFET rarely changed after an occurrence of channel inversion (V_tg ≥ V_inv). However, it was observed that the V_inv of the TFET was unaffected by the gate-to-source voltage (V_gs), but it was determined by the gate-to-drain voltage (V_gd) instead. Moreover, an increase in V_ds also increased V_inv, while the change in turn-on voltage (V_on) was negligible during the first occurrence of the BTBT. Due to this, the gate-to-channel coupling for high V_ds was stronger than that for low V_ds, which further resulted in a smaller S compared with that for low V_ds.

Second, the insets of both Figure 2a,b indicate that S was improved as the amount of V_bg increased. As shown, if the amount of V_bg was increased up to 2 V, S was decreased from 84 to 77 mV/dec for V_ds = 0.05 V and from 74 to 68 mV/dec for V_ds = 0.5 V. In addition, Figure 3a,b depict the change in ratio (I_on/I_off) of the on-state current (I_on) and the off-state current (I_off) with increasing amount of V_bg. The I_on and I_off are defined as I_d at V_tg = 1.0 V and V_tg = 0 V, respectively. As mentioned earlier, due to the improved S by increasing the amount of V_bg, the I_on/I_off increased by 144% and 126% for V_ds of 0.05 and 0.5 V, respectively.

In order to analyze these phenomena, the change in surface potential (Δφ_s) of the back-gated TFET as a function of V_tg was examined, as shown in Figure 4. Δφ_s was extracted as the change in surface potential with respect to V_tg sweep starting from −0.4 V. As shown, for small values of V_tg, the surface potential was linearly proportional to it. However, as V_tg further increased, the surface potential became saturated. This behavior is attributed to the formation of an inversion layer, which decouples the V_tg with the surface potential [13]. Owing to the screening of the V_tg by the inversion charges at the channel, the surface potential could not be increased any further. As a result, the BTBT barrier width (i.e., BTBT probability) was almost fixed, and I_d became slightly saturated, which resulted in a distinct degradation of S with the increase in V_tg, as shown in Figure 2. An interesting phenomenon observed in Figure 4 is that the saturation point of the surface potential was pulled back when V_bg was applied. The channel potential was well-controlled by V_tg before the saturation region, which explained the improvement in S with a larger |V_bg|.

In order to confirm the dependence of S on V_bg more quantitatively, the values of V_inv were extracted from the gate capacitance (C_g) and V_tg relationship for different values of V_bg, as shown in Figure 5a, and were further compared with V_on, as shown in Figure 5b. By referring to [14], the values of V_inv were extracted from the first extremums of the second derivative of the C_g–V_tg curves. The extraction method is a concept of extracting the V_th of an MOESFET similar to the maximum transconductance (g_m,max) method; and the extraction equation was written as below:

$$\frac{\mathrm{d}{g}_{\mathrm{m}}}{\mathrm{d}{V}_{\mathrm{tg}}}=\frac{{\mathrm{d}}^2{I}_{\mathrm{d}}}{\mathrm{d}{V}_{\mathrm{tg}}{}^2}\propto \frac{{\mathrm{d}}^2{C}_{\mathrm{g}}}{\mathrm{d}{V}_{\mathrm{tg}}{}^2}.$$

(1)

As a result, the larger extremum points were obtained, when higher values of |V_bg| were applied, which meant the higher V_tg was required for the channel inversion. Because the better gate controllability was secured before the formation of the inversion layer, the higher value of V_inv means that the region of steeper transfer characteristics was expanded. The top-gate controllability improvement by the back-gate bias can be explained with the energy band diagrams of a single-gate device and a double-gate device, as shown in Figure 5c.

Considering the definitions of V_inv and V_on, the mechanism of the change in S with respect to the amount of V_bg can be understood by comparing the values of V_inv and V_on. As clearly observed from Figure 2a and Figure 5b, V_on did not vary for different values of V_bg, and the transistor was turned on for the same value of V_tg (−0.04 V). Since the energy level of the Γ valley of Ge for direct tunneling is 0.14 eV higher than that of the L valley, where indirect tunneling occurred, it is necessary to change the surface potential, even after the turn-on point of the transistor V_on, in order to improve S using direct tunneling. In the absence of V_bg, V_inv was found to be lower than V_on, as shown in Figure 5b. This meant that, in this case, it was hard for direct tunneling to take place, because of the already formed inversion layer, which screened the electric field. In contrast, when a negative V_bg was applied, V_inv became larger, while V_on remained the same, as shown in Figure 5b. Therefore, the direct tunneling between the source and the channel became dominant after the turn-on point of the transistor. Moreover, S was kept at a low level, until the coupling between the V_tg and the surface potential became weaker due to the formation of the inversion layer. As a result, the voltage window between V_on and V_inv was found to be the determining factor for the subthreshold characteristics of TFETs. Furthermore, this is the reason why a lower S can be obtained in back-gated TFETs compared to that in conventional TFETs.

4. Conclusions

In this study, using the TCAD simulation, it was confirmed that the subthreshold characteristics of a TFET can be improved by introducing a back-gate bias, compared to those of conventional TFETs. The impact of V_bg on S was discussed using the concepts of V_on and V_inv. A V_bg value of −2 V can help reduce S of the TFET with L_gate = 50 nm. For V_ds = 0.05 V, an improvement in S by −7 mV/dec was achieved. In addition, the minimum S value of 68 mV/dec was obtained at V_ds = 0.5 V for V_bg = −2 V. Moreover, an improvement in transfer characteristics, which was caused by the back-gate voltage, was confirmed by an increase of 126% in on–off current ratio at V_ds = 0.5 V for V_bg = −2 V. Considering the applications of TFETs as a low-power device, the back-gated TFET structure can be one of the strategies for achieving better performance.