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Open AccessArticle

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

1
School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, Korea
2
The Department of Information and Communication Engineering, Sejong University, Seoul 143-747, Korea
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(12), 1397; https://doi.org/10.3390/electronics8121397
Received: 9 October 2019 / Revised: 7 November 2019 / Accepted: 20 November 2019 / Published: 22 November 2019
(This article belongs to the Special Issue Hardware and Architecture Ⅱ)
This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors. View Full-Text
Keywords: delay elements; fast Fourier transform (FFT); single-path delay feedback (SDF); zero-padded signal delay elements; fast Fourier transform (FFT); single-path delay feedback (SDF); zero-padded signal
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Jung, Y.; Cho, J.; Lee, S.; Jung, Y. Area-Efficient Pipelined FFT Processor for Zero-Padded Signals. Electronics 2019, 8, 1397.

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