In many applications such as all-digital phase-locked loops (ADPLLs) [1
], chemical sensors readout [2
], frequency synthesizers [3
], and time-of-flight (ToF) systems [7
], time-to-digital converters (TDCs) play an important role by measuring a time interval. Thus far, many TDCs have been presented which have been trying to show high signal-to-noise ratio (SNR), resolution, bandwidth, and linearity. In this way, various TDC architectures such as time-interleaved, pipelined, flash, Successive approximation register (SAR) and cyclic architectures have been introduced [8
]. Since these architectures operate in Nyquist rate, they are ineligible to achieve important parameters of performance such as dynamic range and resolution higher than that of their oversampling counterparts.
Recently, researchers have introduced ∆∑ TDCs benefiting from an inherent noise-shaping property. Voltage-domain ∆∑ TDCs which are implemented mainly as analog utilize a time-to-voltage converter and a conventional ∆∑ modulator [15
]. To take advantage of the scaling of the CMOS process, time-domain ∆∑ TDCs utilizing digital circuits such as multi-bit counter, gated-ring oscillator (GRO) [17
] and switched-ring oscillator (SRO) [18
] have been proposed. However, the noticeable problem of GRO-TDC is the oversampling ratio (OSR) limitation by the rate of input pulse (fc
). Also, a SRO-TDC suffers from noise-shaping limitation to the first order. Consequently, achieving fine time-resolution is not affordable in these architectures. However, to achieve finer time-resolution a 1-1 multi-stage noise-shaping (MASH) TDC can be formed by cascading two SRO-TDCs using two identical SROs, and the difference in the SROs operating frequencies results in systematic error which requires calibration unit to compensate the error. Therefore, this takes a long settling time and also suffers from additional power consumption and chip area [19
]. A second-order MASH ∆∑ TDC has been presented in [20
] which solves the aforementioned problem in a 1-1 MASH SRO-TDC by exploiting gated switched-ring oscillators (GSROs) that lead to a fine time-resolution without calibration. However, the main drawback of that work is OSR limitation due to GSROs’ operating frequencies. As will be discussed later, in GSRO-TDC a counter counts the number of rising edges of GSRO output which is proportional to the time interval to be measured. Thus, sampling clock frequency (fs
) must be less than maximum frequency of the GSRO so that at least one rising edge occurs in each sampling clock. Therefore, as operating frequencies of the GSRO increase, higher fs
can be applied to the TDC which results in higher time-resolution. To enhance SNR, a multirated 1-1 MASH ∆∑ TDC has been proposed in [21
]. Although it exploits a digital ring oscillator in the second stage, a switched-capacitor VCO is used in its first stage that not only suffers from non-linearity and low operating frequency but also because of analog implementation occupies high chip area and consumes excessive power. Moreover, the second-stage ring oscillator produces a thermometric code corresponding to its input. Thus, an extra unit is needed to decode the thermometric code to a binary counterpart resulting in more chip area and power consumption. Also, the aforementioned decoding takes three clock cycles to be completed which degrades the speed of TDC. In the meantime, advancing of CMOS technology on the one hand, and introducing high-performance FPGA chips on the other, have had an impressive impact on presenting fast, accurate and low power application specific integrated circuit (ASIC) and FPGA-based TDCs [22
]. However, all-digital designing encourages some designers to implement their works on FPGA. Albeit optimizing the design in ASIC implementation, the benefit of FPGA implementation is that the design can be programmable to suit different applications. So, it can be tailored for wide variety of applications compared with ASIC which is not flexible. Although the FPGA boards are too big, the board is only used during the development phase. Once the design is confirmed, only the FPGA chip will be embedded in the system rather than the whole development board. Hence, we can say that the FPGA chip size is almost similar to ASIC IC while it can perform multiple operations and flexibility.
This paper presents an FPGA-based 1-1 MASH GSRO-based ΔΣ TDC which employs multirating technique in a ΔΣ GSRO-TDC for the first time. We propose a 16-bit continuous-time TDC that takes advantage of employing GSRO quantizer to suppress quantization error leakage and at the same time benefits from a multirating technique to improve SNR further over conventional TDCs. The operation principle and FPGA implementation are described in detail. The proposed FPGA-based TDC achieves a high performance in terms of dynamic range, time-resolution and figure-of-merit (FoM) while providing acceptable SNR and bandwidth.
This paper is organized as follows. In Section 2
, a background of GSRO-based MASH ∆∑ TDCs and multirating technique is presented. The proposed multirated 1-1 MASH ∆∑ TDC is introduced in Section 3
. Section 4
describes the implementation details of the proposed TDC. In Section 5
, the measured results of the FPGA-based prototype TDC are discussed. Finally, Section 6
concludes this paper.