# An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

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## Abstract

**:**

## 1. Introduction

## 2. Background

#### 2.1. Gated Switched-Ring Oscillator-Time-to-Digital Converter (GSRO-TDC)

_{max}, f

_{min}and 0. By keeping phase properly in GSRO, leakage can be avoided effectively.

_{GSRO2}) can be estimated by:

_{1}) are fed to QEGen that produces a quantization error pulse of the first stage (Q

_{1}) and a frequency sync pulse (Q

_{IN}) in every cycle which control the inputs of the second stage. Since the gates of the GSRO2 are controlled by Q

_{1}and the frequency of that is controlled by Q

_{IN}, oscillation frequencies of the GSRO1 and GSRO2 are equal during a sampling period as shown in Figure 3.

_{S}so that there exists at least one rising edge during a sampling period. Therefore, the relationship between the GSRO frequency, f

_{S}and f

_{C}can be expressed as: f

_{max}> f

_{min}> f

_{S}≥ f

_{C}[20]. Thus, it can be said that in GSRO-TDC OSR is limited by the frequency of GSRO. So, we set f

_{max}and f

_{min}of GSROs in this work at 4 GHz and 2 GHz, respectively, so that they are 1.6 and 2 times their counterpart in [20]. Such high GSRO frequency makes applying f

_{S}up to 2 GHz eligible in this design which results in higher OSRs and hence time-resolution below 0.5 ps.

#### 2.2. Multirating Technique in ∆∑ Multi-Stage Noise-Shaping (MASH) Converters

_{S1}) and second stage operates at higher speed (f

_{S2}= m × f

_{S1}). As a matter of fact, employing multirating technique is more attractive in ∆∑ MASH converters rather than single-loop converters, because in the MASH architecture each stage operates independently and thus no interstage feedback is required while the latter require complex feedback, multi-bit digital-to-analog converter (DAC) and anti-aliasing digital filter. Also, as op-amp based and analog implemented converters suffer from gain/bandwidth trade-off and limited speed, performance improvement by employing this technique is limited in such converters [21]. Thus, an all-digital multirate ∆∑ MASH TDC that can achieve high performance is of interest. To reveal maximum performance enhancement by exploiting the multirating technique at high clock frequencies, this paper presents an FPGA-based 1-1 MASH ∆∑ TDC employing the multirating technique in a GSRO-TDC for the first time.

_{MR}) is expressed as:

_{i}is the loop filter order and OSR

_{i}is over-sampling-ratio (OSR) of the i

^{th}stage. The NTF of conventional single-rate MASH structure is obtained by:

## 3. Proposed FPGA-Based 1-1 MASH ∆∑ TDC

_{S2}) is multiplied by the multirating ratio (m) in the proposed TDC. In addition, as f

_{S2}is m times higher than the first stage clock frequency (f

_{S1}), output of the first stage (Y

_{1}) should be up-sampled by m in the DCF. Like conventional ∆∑ converters, the first- and second-stage outputs (Y

_{1}and Y

_{2}) should be filtered by the signal transfer function (STF) of the second stage (z

^{−1}) and NTF of the first stage (1 − z

^{−1}), respectively. Finally, the overall output of the proposed TDC (D

_{OUT}) is obtained by subtraction of Y

_{2}from Y

_{1}which can be expressed as:

_{S1}and f

_{S2}are shown in Figure 6a and Figure 6b, respectively. As shown, a quantization error pulse of the first stage (Q

_{EN}) is generated by an interstage synchronizer (IntS Sync) every cycle to enable GSRO2 and (Q

_{IN}) to synchronize the GSROs operating frequency. Hence, as can be seen, this approach suppresses any frequency difference between GSROs perfectly which removes phase-domain quantization error leakage that allows the proposed design to achieve second-order noise-shaping as expected. Moreover, it can be deduced that the overall output number related to input time interval (D

_{OUT}) is the average of numbers counted in each sampling clock (CNT

_{OUT}).

_{min}and f

_{max}of the GSROs are set at higher frequencies than state-of-the-art VCO-based ∆∑ TDCs that allow OSRs greater than that feasible in previous works which result in finer time-resolution. Yet, by exploiting multirating technique, a notable improvement in performance of the proposed TDC rather than previous works using same architecture is attainable. Due to the speed and power limitation in analog circuitries used in the first stage of 1-1 MASH TDC in [21], it cannot benefit from this technique at high frequencies to enhance performance further. Hence, fine time-resolution below 1 ps is not achievable in that work. In addition, while in other works f

_{S1}and f

_{S2}are applied to the TDC using external sources, in the proposed design built-in PLLs of the Altera Stratix IV FPGA board provide f

_{S1}and f

_{S2}and, accordingly, no external sources are needed.

## 4. Implementation Details

#### 4.1. GSRO and Sampling Clocks

_{S1}and f

_{S2}) and GSROs operation frequencies (f

_{min}and f

_{max}) are extracted. Figure 7a illustrates the conceptual clock generating different frequencies in the proposed design. As can be seen, in order to obtain f

_{S1}, f

_{S2}, f

_{min}and f

_{max}, 100 MHz input clock is multiplied by 2, 8, 20 and 40, respectively. Furthermore, as shown in Figure 7b, a control unit with 3-state output emulates GSRO. When both Q

_{EN}and Q

_{IN}are low, the unit output is 0. If Q

_{EN}is high but Q

_{IN}is low f

_{min}goes to output. When both Q

_{EN}and Q

_{IN}are high output is f

_{max}.

_{min}and f

_{max}which result in better time-resolution compared to previous GSRO-TDCs with lower operating frequencies for GSRO, but high switching delay makes it difficult to obtain such high frequencies by using analog circuitries and conventional ring oscillators.

#### 4.2. Interstage Synchronizer (IntS Sync)

_{EN}to enable GSRO2 and Q

_{IN}to synchronize operating frequency of two GSROs. Schematics of this unit and timing diagram of that are shown in Figure 8a and Figure 8b, respectively. An edge-sensitive pulse generator (ESPG) of that schematic which is shown in Figure 8c produces Q

_{EN}with the width of interval between rising edges of CLK and Y

_{1}. Then Q

_{EN}which is proportional to the quantization error of the first stage is fed to GSRO2. This pulse can be very narrow and can even be ignored if rising time of the ESPG is larger than the quantization error pulse width. Thus, owing to limited GSRO gates switching time, a narrow pulse causes a deadzone problem and degrades the operation of the proposed TDC. Nevertheless, by adding a flip-flop (DFF2) a static offset of 2π is added to Q

_{EN}to avoid this problem. The static offset is removed in the DCF and the overall performance of the proposed TDC is not altered [20].

#### 4.3. The 16-Bit Quantizer

_{S}lower than f

_{min}to guarantee occurring a residue pulse each cycle. As f

_{min}> f

_{S}, a number of rising edges may appear in a sampling period and, thus, a multi-bit quantizer is needed. In the proposed FPGA-based TDC, built-in 16-bit counters count rising edges of the first and second stages outputs to quantize Y

_{1}and Y

_{2}in each sampling clock. Using such number of bits for quantization is a notable distinction point of the proposed TDC compared to previous works results in a better time-resolution. It is noteworthy that such an improvement is an advantage of implementing the proposed all-digital TDC on a high-performance FPGA board. A possible error that may occur during 16-bit quantizer operation is coinciding the transition of counter output with a sampling clock rising edge [31]. To avoid this large error, a delayed clock generator (DLCKgen) shown in Figure 9a is employed so that sampling clock occurs only after settling counter output (CNT

_{out}). As shown in Figure 9b, such an error is reduced effectively by adding a DLCKgen [20].

#### 4.4. Digital Cancellation Filter (DCF)

^{−1}) to produce D1. Also, digital output of the second stage is filtered by the NTF of the first stage (1 − z

^{−1}) to generate D2. Finally, the overall TDC digital output (D

_{OUT}) is obtained by subtraction of D2 from D1.

## 5. Measured Results

_{IN}) and obtain digital output (D

_{OUT}). It should be mentioned that the I/O standard of GPIO ports of the Altera Stratix IV FPGA board is 3 V. Thus, in order to obtain output spectrum, 3 V 10 MHz input pulses are applied to the proposed TDC using a function generator (Siglent SDG 1050) and 100-k samples are captured using a mixed-domain oscilloscope (Tektronix MDO 4104) that uses a Hann window. Then, post-processing of captured data was done using MATLAB. The measurement setup for obtaining the output spectrum of the proposed TDC is illustrated in Figure 10.

_{C}and 200 MHz f

_{S1}and f

_{S2}. As shown, this work can achieve appropriate second-order noise-shaping, and the measured SNR within 9.5 MHz bandwidth is 43.09 dB in this case. To demonstrate the improvement resulting from the multirating technique, a sampling clock of the second stage was quadrupled and the output spectrum of the proposed TDC at 100 MHz f

_{C}, 200 MHz f

_{S1}and 800 MHz f

_{S2}is shown in Figure 11b. As surmised, benefiting from multirating technique the measured SNR within 9.6 MHz bandwidth was 56.8 dB which showed 13.71 dB enhancement compared to single-rate case. According to Equation (8), by increasing the OSR, more enhancement in SNR is achievable. Therefore, another measurement was induced to the proposed TDC with higher f

_{S1}and f

_{S2}. In this case, 400 MHz f

_{S1}and 1.6 GHz f

_{S2}were applied to the first and second stages, respectively.

_{C}to the proposed TDC, the output spectrum was measured and the result of which was shown in Figure 11c. Interestingly, yielding 4.22 dB enhancement rather the previous case, the measured SNR within 9.6 MHz bandwidth was 61.02 dB which translates to 9.8 effective number of bits (ENOB) and 0.27 ps time-resolution. The core power consumption of the Altera Stratix IV FPGA board is 6.23 mW at 100 MHz f

_{C}, 200 MHz f

_{S1}and 800 MHz f

_{S2}. By increasing the sampling frequency (i.e., 400 MHz f

_{S1}and 1.6 GHz f

_{S2}), the power consumption increases up to 7.84 mW while it not only results in better time-resolution and SNR, but also increases the figure-of-merit (FoM) from 176 dB to 177 dB.

_{C}leads to higher SNR for the same OSR [20]. So, we examined this effect by the prototype of the proposed TDC once at 200 MHz f

_{S1}and 800 MHz f

_{S2}, and another time at 400 MHz f

_{S1}and 1.6 GHz f

_{S2}. Figure 12 depicts the measured SNR versus f

_{C}while OSR remains unchanged. According to Figure 12, it can be deduced that the SNR is improved by increasing f

_{C}for both cases.

## 6. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

- Yan, N.; Ma, L.; Xu, Y.; Chen, S.; Liu, X.; Xiang, J.; Min, H. A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications. IEEE Access
**2019**, 7, 7897–7904. [Google Scholar] [CrossRef] - Liu, Y.; Constandinou, T.G.; Georgiou, P. A 32 × 32 ISFET Array with In-Pixel Digitisation and Column-Wise TDC for Ultra-Fast Chemical Sensing. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26–29 May 2019; pp. 1–5. [Google Scholar]
- Hussein, A.; Vasadi, S.; Paramesh, J. A 50–66-GHz Phase-Domain Digital Frequency Synthesizer with Low Phase Noise and Low Fractional Spurs. IEEE J. Solid State Circuits
**2017**, 52, 3329–3347. [Google Scholar] [CrossRef] - Alkurwy, S.; Sawal, H.M.A.; Shabiul Islam, M.; Idros, F. A low power memoryless ROM design architecture for a direct digital frequency synthesizer. Turkish J. Electr. Eng. & Comput. Sci.
**2017**, 25, 4023–4032. [Google Scholar] - Ibrahim, S.H.; Sawal, H.M.A.; Shabiul Islam, M. Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer. Sci. World J.
**2014**, 2014, 1–9. [Google Scholar] [CrossRef] [PubMed] - Ibrahim, S.H.; Sawal, H.M.A.; Shabiul Islam, M. Implementation of a 32-Bit High-Speed Phase Accumulator for Direct Digital Frequency Synthesizer. Asian J. Sci. Res.
**2014**, 7, 118–124. [Google Scholar] [CrossRef] - Nguyen, V.; Duong, D.; Chung, Y.; Lee, J.W. A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique. Sensors
**2018**, 18, 3948. [Google Scholar] [CrossRef] - Lu, P.; Wu, Y.; Andreani, P. A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter with Digital Calibration. IEEE Trans. Circuits Syst. II Express Briefs
**2016**, 63, 1019–1023. [Google Scholar] [CrossRef] - Yu, W.; Kim, J.; Kim, K.; Cho, S. A time-domain high-order MASH ADC using voltage-controlled gated-ring oscillator. IEEE Trans. Circuits Syst. I Reg. Papers
**2013**, 60, 856–866. [Google Scholar] [CrossRef] - Kim, J.S.; Seo, Y.H.; Suh, Y.; Park, H.J.; Sim, J.Y. A 300-MS/s, 1.76-ps-resolution, 10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13-µm CMOS. IEEE J. Solid State Circuits
**2013**, 48, 516–526. [Google Scholar] [CrossRef] - Kim, K.; Kim, Y.H.; Yu, W.; Cho, S. A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier. IEEE J. Solid State Circuits
**2013**, 48, 1009–1017. [Google Scholar] [CrossRef] - Kim, K.S.; Yu, W.; Cho, S. A 9 b, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register. In Proceedings of the Symposium on VLSI Circuits, Kyoto, Japan, 12–14 June 2013; pp. 1007–1016. [Google Scholar]
- Seo, Y.H.; Kim, J.S.; Park, H.J.; Sim, J.Y. A 1.25 ps resolution 8 b cyclic TDC in 0.13 µm CMOS. IEEE J. Solid State Circuits
**2012**, 47, 736–743. [Google Scholar] [CrossRef] - Chung, H.; Ishikuro, H.; Kuroda, T. A 10-Bit 80-MS/s decision-select successive approximation TDC in 65 nm CMOS. IEEE J. Solid State Circuits
**2012**, 47, 1232–1241. [Google Scholar] [CrossRef] - Gande, M.; Maghari, N.; Oh, T.; Moon, U.K. A 71 dB dynamic range third-order TDC using charge-pump. In Proceedings of the Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 13–15 June 2012; pp. 168–169. [Google Scholar]
- Young, B.; Kwon, S.; Elshazly, A.; Hanumolu, P.K. A 2.4 ps resolution 2.1 mW second-order noiseshaped time-to-digital converter with 3.2 ns range in 1 MHz bandwidth. In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 19–22 September 2010; pp. 1–4. [Google Scholar]
- Straayer, M.Z.; Perrott, M.H. A multi-path gated ring oscillator TDC with first-order noise shaping. IEEE J. Solid State Circuits
**2009**, 44, 1089–1098. [Google Scholar] [CrossRef] - Elshazly, A.; Rao, S.; Young, B.; Hanumolu, P.K. A 13 b 315 fsrms 2 mW 500 MS/s 1 MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. In Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 20–24 February 2012; pp. 464–466. [Google Scholar]
- Konishi, T.; Okuno, K.; Izumi, S.; Yoshimoto, M.; Kawaguchi, H. A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillator and dynamic flipflops. In Proceedings of the Symposium on VLSI Circuits (VLSIC), 13–15 June 2012; pp. 190–191. [Google Scholar]
- Yu, W.; Kim, K.S.; Cho, S.H. A 148 fsrms integrated noise 4 MHz bandwidth second-order ∆∑ time-to-digital converter with gated switched-ring oscillator. IEEE Trans. Circuits Syst. I Reg. Papers
**2014**, 61, 2281–2289. [Google Scholar] [CrossRef] - Zaliasl, S.; Saxena, S.; Hanumolu, P.K.; Mayaram, K.; Fiez, T.S. A 12.5-bit 4 MHz 13.8 mW MASH Modulator with Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Reg. Papers
**2012**, 59, 1604–1613. [Google Scholar] [CrossRef] - Chandrasekaran, S.T.; Jayaraj, A.; Danesh, M.; Sanyal, A. A Highly Digital Second-Order Oversampling TDC. IEEE Solid State Circuits Lett.
**2018**, 1, 114–117. [Google Scholar] [CrossRef] - Liu, Q.; Edward, A.; Zhou, D.; Silva-Martinez, J. A Continuous-Time MASH 1-1-1 Delta–Sigma Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
**2018**, 26, 756–767. [Google Scholar] [CrossRef] - Dayanik, M.B.; Weyer, D.; Flynn, M.P. A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging. In Proceedings of the Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, 5–8 June 2017. [Google Scholar]
- Edward, A.; Liu, Q.; Briseno-Vidrios, C.; Kinyua, M.; Soenen, E.G.; Karşılayan, A.I.; Silva-Martinez, J. A 43-mW MASH 2-2 CT ∑∆ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits
**2017**, 52, 448–459. [Google Scholar] [CrossRef] - Li, H.; Breyne, L.; Van Kerrebrouck, J.; Verplaetse, M.; Wu, C.Y.; Demeester, P.; Torfs, G. A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs. IEEE Trans. Circuits Syst. II Express Briefs
**2019**, 66, 482–486. [Google Scholar] [CrossRef] - Tan, Y.T.; Bhuyan, M.S.; Sawal, H.M.A.; Shabiul Islam, M. FPGA Realization of Fault Diagnostic Manufacturing Equipment Using Fuzzy Expert System. Res. J. Appl. Sci.
**2014**, 9, 53–59. [Google Scholar] - Moubark, A.M.; Mohd Ali, M.A.; Sanusi, H.; Sawal, H.M.A. FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL. J. Appl. Sci.
**2013**, 13, 385–392. [Google Scholar] [CrossRef][Green Version] - Marufuzzaman, M.; Ibne Reaz, M.; Rahman, L.F.; Chang, T.G. FPGA Based Precise and High Speed Current dq PI Controller for FOC PMSM Drive. Curr. Nanosci.
**2014**, 10, 394–401. [Google Scholar] [CrossRef] - Straayer, M.Z. Noise Shaping Techniques for Analog and Time to Digital Converters Using Voltage Controlled Oscillators. Ph.D. Thesis, MIT, Cambridge, MA, USA, 2008. [Google Scholar]
- Kim, J.; Jang, T.K.; Yoon, Y.G.; Cho, S. Analysis and design of voltage-controlled oscillator based analog-to-digital converter. IEEE Trans. Circuits Syst. I Reg. Papers
**2010**, 57, 18–30. [Google Scholar]

**Figure 2.**1-1 Multi-stage noise-shaping (MASH) ∆∑ time-to-digital converter (TDC) architecture using GSRO [20].

**Figure 3.**The timing diagram of the second-order GSRO-TDC [20].

**Figure 6.**Timing diagram of the proposed 1-1 MASH multirate TDC: (

**a**) f

_{S1}= 200 MHz and f

_{S2}= 800 MHz with T

_{IN}= 1 ns; (

**b**) f

_{S1}= 200 MHz and f

_{S2}= 800 MHz with T

_{IN}= 4 ns; (

**c**) f

_{S1}= 400 MHz and f

_{S2}= 1600 MHz with T

_{IN}= 1 ns; (

**d**) f

_{S1}= 400 MHz and f

_{S2}= 1600 MHz with T

_{IN}= 2 ns.

**Figure 7.**(

**a**) Conceptual clock generating unit in the proposed TDC; (

**b**) schematic of GSRO operating frequency control unit.

**Figure 8.**Interstage synchronizer (IntS Sync): (

**a**) block diagram; (

**b**) timing diagram; (

**c**) schematic of the edge-sensitive pulse generator (ESPG).

**Figure 9.**Delaying rising edges of Y2 to avoid error: (

**a**) schematic of delayed pulse generator; (

**b**) timing diagram.

**Figure 11.**Measured output spectrum of the proposed 1-1 MASH TDC. (

**a**) f

_{S1}= 200 MHz and f

_{S2}= 200 MHz; (

**b**) f

_{S1}= 200 MHz and f

_{S2}= 800 MHz; (

**c**) f

_{S1}= 400 MHz and f

_{S2}= 1600 MHz.

**Figure 12.**Signal-to-noise ratio (SNR) versus f

_{C}: (

**a**) f

_{S 1}= 200 MHz and f

_{S2}= 800 MHz; (

**b**) f

_{S1}= 400 MHz and f

_{S2}= 1.6 GHz.

[25] | [24] | [23] | [22] | [20] | This work | ||
---|---|---|---|---|---|---|---|

Process (nm) | 40 | 40 | 40 | 65 | 65 | 40-FPGA | |

Shaping order | 4 | 3 | 3 | 2 | 2 | 2 | |

f_{BW} (MHz) | 50.3 | 156 | 50.5 | 2.5 | 4 | 9.6 | |

T_{range} (ns) | N/A | N/A | N/A | 4.5 | 4 | 4.5 | |

f_{S} (MHz) | 1000 | 5000 | 3000 | 205 | 400 | 200-800 | 400-1600 |

DR (dB) | 76.8 | 70 | 68.2 | 52.6 | 79.6 | 84.2 | 86.2 |

T_{int,rms} (f_{s,rms})^{1} | N/A | N/A | N/A | 3752 | 148 | 98.2 | 78 |

SNR (dB) | 75.8 | 66.6 | 68 | 56 | N/A | 56.8 | 61.02 |

Resolution (ps)^{2} | N/A | N/A | N/A | 13 | 0.51 | 0.34 | 0.27 |

Power (mW) | 43 | 233 | 19 | 0.63 | 6.72 | 6.23^{3} | 7.84^{3} |

FoM (dB)^{4} | 167.5 | 158.3 | 162.4 | 148 | 167 | 176 | 177 |

^{1}Estimated integrated noise ($\sqrt{Resolutio{\mathrm{n}}^{2}/12}$).

^{2}Estimated resolution ($\sqrt{{T}_{i\mathrm{n}t,rms}{}^{2}.12}$).

^{3}FPGA core power consumption.

^{4}FoM = DR + 10 log

_{10}(Bandwidth/Power) [dB], where DR = 20 log

_{10}(T

_{range,rms}/T

_{int,rms}).

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**MDPI and ACS Style**

Mouri Zadeh Khaki, A.; Farshidi, E.; Hamid MD Ali, S.; Othman, M. An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique. *Electronics* **2019**, *8*, 1285.
https://doi.org/10.3390/electronics8111285

**AMA Style**

Mouri Zadeh Khaki A, Farshidi E, Hamid MD Ali S, Othman M. An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique. *Electronics*. 2019; 8(11):1285.
https://doi.org/10.3390/electronics8111285

**Chicago/Turabian Style**

Mouri Zadeh Khaki, Ahmad, Ebrahim Farshidi, Sawal Hamid MD Ali, and Masuri Othman. 2019. "An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique" *Electronics* 8, no. 11: 1285.
https://doi.org/10.3390/electronics8111285