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Open AccessArticle

A Subthreshold Bootstrapped SAPTL-Based Adder Design

by Qi Zhang 1,2,3,4, Yuping Wu 1,2,3,4,5 and Lan Chen 1,2,3,4,*
1
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2
The EDA center of Chinese Academy of Sciences, Beijing 100029, China
3
Beijing Key Laboratory of 3D & Nano IC Design Automation Technology, Beijing 100029, China
4
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
5
Key Laboratory of Microelectronic Devices & Integrated Technology, Chinese Academy of Sciences, Beijing 100029, China
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1161; https://doi.org/10.3390/electronics8101161
Received: 11 September 2019 / Revised: 9 October 2019 / Accepted: 10 October 2019 / Published: 12 October 2019
(This article belongs to the Section Microelectronics and Optoelectronics)
This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other works in terms of performance, energy consumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis proved the proposed adder’s significant enhancement of robustness against process and temperature variations. At 0.3 V (TT corner, 25 °C), the proposed 16 bit adder achieved improvements of 72% in performance and 8% in energy savings, as well as a 74% reduction in energy-delay production as compared with the current design. View Full-Text
Keywords: ultra-low power; subthreshold circuit; bootstrapped circuit; SAPTL; adder; energy efficiency; robustness; process variation ultra-low power; subthreshold circuit; bootstrapped circuit; SAPTL; adder; energy efficiency; robustness; process variation
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Zhang, Q.; Wu, Y.; Chen, L. A Subthreshold Bootstrapped SAPTL-Based Adder Design. Electronics 2019, 8, 1161.

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