Next Article in Journal
A Subthreshold Bootstrapped SAPTL-Based Adder Design
Previous Article in Journal
Memory Optimization for Bit-Vector-Based Packet Classification on FPGA
 
 
Article

Article Versions Notes

Electronics 2019, 8(10), 1160; https://doi.org/10.3390/electronics8101160
Action Date Notes Link
article xml file uploaded 12 October 2019 13:34 CEST Original file -
article xml uploaded. 12 October 2019 13:34 CEST Update https://www.mdpi.com/2079-9292/8/10/1160/xml
article pdf uploaded. 12 October 2019 13:34 CEST Version of Record https://www.mdpi.com/2079-9292/8/10/1160/pdf
article html file updated 12 October 2019 13:36 CEST Original file -
article html file updated 30 October 2019 14:04 CET Update -
article html file updated 14 February 2020 00:24 CET Update -
article html file updated 20 July 2022 01:44 CEST Update https://www.mdpi.com/2079-9292/8/10/1160/html
Back to TopTop