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Open AccessArticle

Memory Optimization for Bit-Vector-Based Packet Classification on FPGA

Computer College, National University of Defense Technology, Changsha 410073, China
School of ECE, Shenzhen Graduate School, Peking University, Shenzhen 518055, China
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1159;
Received: 20 September 2019 / Revised: 4 October 2019 / Accepted: 8 October 2019 / Published: 12 October 2019
(This article belongs to the Special Issue New Applications and Architectures Based on FPGA/SoC)
High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy that, in the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively plenty of useless wildcards in the rules. We thus present a memory-optimized packet classification scheme named WeeBV to eliminate the memory occupied by the wildcards. WeeBV consists of a heterogeneous two-dimensional lookup pipeline and an optimized heuristic algorithm for searching all the wildcard positions that can be removed. It can achieve a significant reduction in memory resources without compromising the high throughput of the original Bit-Vector-based algorithms. We implement WeeBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can save 37% and 41% memory consumption on average for synthetic 5-tuple rules and OpenFlow rules respectively. View Full-Text
Keywords: packet classification; FPGA; bit-vector; wildcard compression packet classification; FPGA; bit-vector; wildcard compression
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Li, C.; Li, T.; Li, J.; Li, D.; Yang, H.; Wang, B. Memory Optimization for Bit-Vector-Based Packet Classification on FPGA. Electronics 2019, 8, 1159.

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