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Open AccessArticle

Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

Department of Electronic and Electrical Engineering, Daegu University, Gyeongbuk 38453, Korea
Broadcom Inc., HiBrand Living, Seocho-gu, Seoul 06771, Korea
Author to whom correspondence should be addressed.
Electronics 2019, 8(10), 1138;
Received: 6 September 2019 / Revised: 29 September 2019 / Accepted: 4 October 2019 / Published: 9 October 2019
(This article belongs to the Special Issue New CMOS Devices and Their Applications)
In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively. View Full-Text
Keywords: feedback timing; ΔΣ ADC; DEM feedback timing; ΔΣ ADC; DEM
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Jung, Y.; Jeon, J. Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications. Electronics 2019, 8, 1138.

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