Search Results (25)

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities. Full article

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec. Full article

In this article, a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD) is proposed and analyzed through TCAD simulations. The MCD incorporates a short channel, where the channel length can be adjusted by modifying the recess depth. Owing to the drain-induced barrier-lowering (DIBL) effect, a low potential barrier is created for electrons flowing from the JFET region to the N+ source region. This effectively eliminates the bipolar degradation of the parasitic body p-i-n diode and reduces the cut-in voltage $V_{\mathrm{on}}$ by 69.2%. Additionally, the breakdown voltage (BV) remains nearly unchanged. The reduction in the p-well region alleviates the JFET effect, successfully lowering the specific on-resistance $R_{\mathrm{on},\mathrm{sp}}$, making the channel easier to turn on, and reducing the threshold voltage ($V_{\mathrm{th}}$). However, the increase in the gate charge $Q_{\mathrm{g}}$ results in a slight rise in the switching loss. Full article

The continuous scaling down of MOSFETs is one of the present trends in semiconductor devices to increase device performance. Nevertheless, with scaling down beyond 22 nm technology, the performance of even the newer nanodevices with multi-gate architecture declines with an increase in short channel effects (SCEs). Consequently, to facilitate further increases in the drain current, the use of strained silicon technology provides a better solution. Thus, the development of a novel Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel with a 10 nm gate length is initiated and discussed. In this device, strain is incorporated in the channel, where a strained silicon germanium layer is wedged between two strained silicon layers. The GAAFET device has four gates that surround the channel to provide improved control of the gate over the strained channel region and also reduce the short channel effects in the devices. The electrical properties, such as the on current, off current, threshold voltage (V_TH), subthreshold slope, drain-induced barrier lowering (DIBL), and I_on/I_off current ratio, of the 10 nm channel length GAAFET are compared with the 22 nm strained silicon channel GAAFET, the existing SOI FinFET device on 10 nm gate length, and IRDS 2022 specifications device. The developed 10 nm channel length GAAFET, having an ultrathin strained silicon channel, delivers enriched device performance, being augmented in contrast to the IRDS 2022 specifications device, showing improved characteristics along with amended SCEs. Full article

In this work, we present the novel application of SiN_x stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiN_x passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as V_ds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiN_x passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as V_ds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiN_x stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V. Full article

Although Moore’s Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)…, longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor. Full article

The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO₂) with a stacked gate oxide of 0.5 nm of SiO₂ with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si₃N₄, Al₂O₃, ZrO_2, and HfO₂. It was found that the use of strained silicon and replacing only the SiO₂ device with the stacked SiO₂ and HfO₂ device was more beneficial to obtain an optimized device with the least leakage and improved drive currents. Full article

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F² DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V. Full article

In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) effect in 2D MoS₂-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. The dependence of the DIBL effect and the lattice temperature in the middle of the channel on the gate length is considered for transistors with different gate oxide and back oxide (BOX) materials. The effects of Al₂O₃ and HfO₂ as gate oxide and SiO₂ and HfO₂ as BOX materials are compared. Transistors, in which the channel is fully and partially (i.e., just below the gate) covered by a gate oxide, are considered. It is shown that the transistors with Al₂O₃ as gate oxide and SiO₂ as BOX materials have higher immunity to DIBL effect and transistors with HfO₂ as gate oxide and HfO₂ as BOX materials have higher immunity to SHE. Full article

Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling, the data disturbance becomes more serious, especially for neighbor wordline interference (NWI), which leads to a deterioration of data storage reliability. Thus, a physical device model was constructed to investigate the NWI mechanism and evaluate critical device factors for this long-standing and intractable problem. As simulated by TCAD, the change in channel potential under read bias conditions presents good consistency with the actual NWI performance. Using this model, NWI generation can be accurately described through the combination of potential superposition and a local drain-induced barrier lowering (DIBL) effect. This suggests that a higher bitline voltage ($V_{bl}$) transmitted by the channel potential can restore the local DIBL effect, which is ever weakened by NWI. Furthermore, an adaptive $V_{bl}$ countermeasure is proposed for 3D NAND memory arrays, which can significantly minimize the NWI of triple-level cells (TLC) in all state combinations. The device model and the adaptive $V_{bl}$ scheme were successfully verified by TCAD and 3D NAND chip tests. This study introduces a new physical model for NWI-related problems in 3D NAND flash, while providing a feasible and promising voltage scheme as a countermeasure to optimize data reliability. Full article

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is −54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of −20 to 80 °C, with a projected area of 0.003 mm². Full article

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS₂ in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS₂ MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS₂ FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (I_D vs. V_GS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage. Full article