Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope

Abstract

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance.

1. Introduction

Tunnel field-effect-transistors (TFETs) are being actively pursued as a potential replacement to conventional metal-oxide-semiconductor (MOS) technology [1]. TFETs offer a sub-thermal subthreshold slope (SS) but suffer from limited ON current I_ON performance [2]. To overcome the limit, different types of line tunneling type TFETs have been introduced, including L-shaped [3] (LTFETs), U-shaped [4] (UTFETs), and Z-shaped [5] TFETs (ZTFETs). Among them, only the LTFET has been experimentally demonstrated [3].

It was found using device simulations that the 2D corner effect [6] present in LTFETs degrades its subthreshold performance. In order to remove SS degradation due to the kink effect induced by the source corner, the fully depleted rounded corner with a gradual doping profile was used [6]. The LTFET still achieves a sub-thermal SS, but as shown in this work there is room for significant improvement in the subthreshold performance of LTFETs. To achieve this improvement, a new device based on the original LTFET is introduced. The new device uses a dual-gate (DG) structure and is termed the DG-LTFET. The two gates (gate1 and gate2) have different workfunctions and different heights. The DG-LTFET was thoroughly evaluated for different device parameters, including the source region height, gate1 and gate2 heights, gate1 and gate2 workfunctions, channel thickness, and drain doping levels. Optimum dimensions and drain doping level were determined for the DG-LTFET. Section 2 briefly discusses the corner-effect problem of the LTFET. Section 3 introduces the DG-LTFET and compares its results with the LTFET. Section 4 presents the conclusion.

2. The LTFET: The Corner Effect

Figure 1 shows a schematic for LTFET. The p⁺ (10²⁰ cm⁻³) doped source region overlaps the gate with the n⁻ (10¹² cm⁻³) channel sandwiched in between them. This sandwiched channel region is termed as R_nonoffset. There is also a part of the channel termed R_offset in which there is an offset present between the source and the gate, as indicted in Figure 1. The following parameters were used for all devices considered in this work unless otherwise specified: source height (H_s) = 40 nm, oxide thickness (t_ox) = 2 nm, length of R_nonoffset (T_j) = 5 nm, channel length (L_ch) = 50 nm, height of R_offset (H_offset) = 10 nm, height of R_nonoffset (H_nonoffset) = H_s, gate height (H_g1) = H_s + (H_offset − t_ox) = 48 nm, dielectric permittivity ε_ox = 25, metal gate workfunction W_{rk_LTFET} = 4.72 eV, and drain doping (N_d) = 10²⁰ cm⁻³.

Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7]. The following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling (BTBT) model, Fermi statistics, and the constant mobility model. The dynamic nonlocal BTBT model calculates BTBT in both lateral and 1D directions. Crystal orientation is assumed to be <100> in all devices. A constant electron effective tunneling mass of 0.19 m_o was used in all simulations [8]. All simulations were performed at a drain source bias V_ds = 0.1 V unless otherwise specified.

For analysis to follow, drain-source current (I_ds) versus gate-source bias (V_gs) characteristics of the LTFET are shown in Figure 2a. There is a direct overlap between gate and source in R_nonoffset, and the electric field in R_nonoffset is in the 1D direction. In R_offset, however, the electric field from the gate converges around the sharp source corner marked by an X in Figure 1. This increases the potential in R_offset as compared to R_nonoffset for any given bias (until potential saturates due to electron inversion). Figure 2b shows the surface potential at V_gs = 0 V. It can be seen that, because the electric field converges around the sharp source corner [6], the potential in R_offset has increased. Since the potential is higher in R_offset as compared to R_nonoffset, the threshold voltage for BTBT in R_offset (V_{th_Roffset}) is lower than the threshold voltage for BTBT in R_nonoffset (V_{th_Rnonoffset}).

Figure 3a,b show the tunneling rate (G_tun) contour plot and G_tun, respectively, at V_gs = 0.21 V which is the bias needed to generate I_ds = 10⁻¹³ A (from Figure 2a). It is obvious from Figure 3 that the BTBT only takes place in R_offset, whereas R_nonoffset is completely switched off. Figure 4a shows G_tun at several V_gs values. From Figure 4a, V_{th_Roffset} and V_{th_Rnonoffset} can be found to be around V_gs = 0.17 V and 0.24 V, respectively. Figure 4b shows the G_tun contour plot at V_gs = V_{th_Rnonoffset} = 0.24 V. Figure 4a shows that G_tun in R_nonoffset just after it turns on, is always higher and has a much larger BTBT area (in the y direction) as compared to R_offset. Thus, whenever R_nonoffset turns on, it dominates over R_offset. The reason why G_tun is higher in R_nonoffset is simply because the BTBT paths in R_offset are laterally oriented or 2D from source to the surface in R_offset, whereas the BTBT paths in R_nonoffset are 1D. The 2D BTBT paths being naturally longer than the 1D paths result in a lower G_tun in R_offset.

From Figure 4a, it can be observed that, for a large part of the subthreshold region (V_gs < 0.24 V), only R_offset with the longer 2D BTBT paths and lower G_tun is contributing to the BTBT current and the more efficient R_nonoffset makes no contribution to the current. In other words, the LTFET underperforms in the subthreshold region. If R_nonoffset could be forced to turn on at a lower bias than R_offset, which is the condition V_{th_Rnonoffset} < V_{th_Roffset}, R_nonoffset will turn on in the subthreshold region, and with the condition G_tun in R_nonoffset > G_tun in R_offset, demonstrated in Figure 4a, a significant improvement in SS could be expected.

In other words, the R_nonoffset could be regarded as a parasitic region with a parasitic, fringing capacitance originating from the bottom of the gate to the sharp source corner. Since the potential is different in this area (Figure 2b), the capacitance associated with this region is different from the R_nonoffset region. If V_{th_Rnonoffset} < V_{th_Roffset} could be achieved, as is demonstrated below, the effect of this parasitic capacitance could be practically eliminated, and this is the purpose of the device proposed below. Since drain is not in close proximity to R_offset/R_nonoffset, where the BTBT current is generated, gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT significantly at high frequency.

3. DG-LTFET

3.1. The DG-LTFET: Basic Device Physics

In order to achieve the condition V_{th_Rnonoffset} < V_{th_Roffset}, the DG-LTFET is presented in Figure 5a. DG-LTFET uses dual material gates denoted by gate1 and gate2, each with a different workfunction (W_{rk_gate1/2}) and height (H_g1/2). H_g1 = H_nonoffset = H_s = 40 nm, H_offset = 10 nm, H_g2 = H_nonoffset − H_g1 + (H_offset − t_ox) = 8 nm, and T_j = 5 nm. W_{rk_gate1} is always lower than W_{rk_gate2}. W_{rk_gate2} is fixed at W_{rk_LTFET} = 4.72 eV for all DG-LTFET considered in this work. The DG-LTFET process-flow is indicated in Figure 5a. The process-flow is based on the LTFET process-flow [3]. The DG-LTFET process-flow follows the LTFET process-flow until the chemical vapor deposition (CVD) of gate2 (similar to the gate deposition in the LTFET). After this, two additional steps are required. The device is masked to protect the gate oxide and channel areas, and gate2 is selectively etched according to the desired height. Gate1 is then deposited in the recess created by gate2-etching by a low-temperature atomic layer deposition process. Similar dual-material gate structures have been extensively reported in the literature including [9,10,11].

Lower W_{rk_gate1} results in an increased flatband voltage [12] (V_fb) in R_nonoffset as compared to R_offset. Figure 5b shows V_fb of DG-LTFET (red symbols) with W_{rk_gate1} = 4.5 eV and W_{rk_gate2} = W_{rk_LTFET}. Also shown for the reference is V_fb of the LTFET (blue symbols). Expectedly, the DG-LTFET potential increases in R_nonoffset. The potential does not change abruptly from gate1 to gate2 because of the presence of 2D effects around the source corner. Electric field from the bottom of gate2 converges around the source corner. Around the middle of R_offset, equilibrium is established between the two gates and DG-LTFET potential overlaps LTFET potential since W_{rk_gate2} = W_{rk_LTFET}. With W_{rk_gate1} < W_{rk_gate2}, the increased potential in R_nonoffset reduces V_{th_Rnonoffset}. If W_{rk_gate1/2} are appropriately tuned with W_{rk_gate1} < W_{rk_gate2}, the condition V_{th_Rnonoffset} < V_{th_Roffset} = 0.17 V can be achieved. Because W_{rk_gate2} = W_{rk_LTFET} = 4.72 eV, V_{th_Roffset} (in the DG-LTFET) is equal to V_{th_Roffset} (in the LTFET).

Figure 6a–c show I_ds-V_gs characteristics at different W_{rk_gate1}, SS, and I_ON/I_OFF of the DG-LTFET with constant W_{rk_gate2} = W_{rk_LTFET} = 4.72 eV for all DG-LTFET, respectively. Also shown for the reference is the I_ds-V_gs characteristics of the LTFET (black squares). I_ON is extracted at V_gs = 0.7 V, and I_OFF is defined as I_ds = 10⁻¹⁷ A. With W_{rk_gate1} = 4.675 eV (red circles), the V_{th_Rnonoffset} is reduced to 0.189 V. Compared with the LTFET, R_nonoffset now turns on earlier in the subthreshold region, along with R_offset. Since the BTBT is more efficient in R_nonoffset (Figure 4a) as compared to R_offset, I_ds increases more rapidly within the subthreshold region.

Hence, just at the transition point, where R_nonoffset turns on (V_gs ~ 0.189), a kink appears in the I_ds-V_gs curve. With W_{rk_gate1} = 4.65 eV (green triangles), V_{th_Rnonoffset} is reduced to V_gs = 0.167 V and the condition V_{th_Rnonoffset} < V_{th_Roffset} is achieved, and DG-LTFET exhibits a remarkable SS with values less than 10 mV/dec as seen in Figure 6b. With W_{rk_gate1} = 4.625 eV (blue stars), V_{th_Rnonoffset} reduces further to 0.1448 V, which is < V_{th_Roffset}. If V_{th_Rnonoffset} < V_{th_Roffset} is established, then any increase in V_{th_Roffset} − V_{th_Rnonoffset} simply shifts the I_ds-V_gs to the left without any change in SS as shown by the blue stars (W_{rk_gate1} = 4.625 eV) and orange diamonds (W_{rk_gate1} = 4.5 eV) in Figure 6a,b, respectively. An improvement of ~16% is observed in the I_ON/I_OFF of the DG-LTFET (with W_{rk_gate1} = 4.625 eV) over the LTFET.

Figure 7a shows the G_tun contour plot of DG-LTFET at a V_gs (= 0.172 V) bias needed to achieve an equivalent I_ds of 10⁻¹³ A in DG-LTFET with W_{rk_gate1} = 4.65 eV. Figure 7b shows the contour plot extracted from Figure 7a. For reference, Figure 7b also shows that G_tun needed to generate an equivalent amount of I_ds in the LTFET (at a V_gs bias of 0.21 V, Figure 3b). As can be seen in Figure 7b, the LTFET needs contribution only from R_offset, but generating the same amount of I_ds DG-LTFET depends heavily on R_nonoffset with some contribution from R_offset. Because G_tun in R_nonoffset is more efficient (Figure 4a), as the V_gs bias increases, G_tun increases exponentially in a much larger area in R_nonoffset, which results in the DG-LTFET exhibiting a much steeper subthreshold swing, while the LTFET continues to depend only on the inefficient BTBT in R_offset until around V_{th_Rnonoffset} = 0.24 V.

3.2. Device Optimization

To optimize device performance, the impact of variations in key parameters including H_g1/2, H_s/T_j, and N_d was investigated. To investigate the impact of H_g1/2 values, I_ds-V_gs characteristics for the DG-LTFET at different H_g1 and H_g2 = H_nonoffset − H_g1 + (H_offset − t_ox) with fixed W_{rk_gate1} = 4.5 eV and W_{rk_gate2} = W_{rk_LTFET}, H_s = H_nonoffset = 40 nm, H_offset = 10 nm, and T_j = 5 nm is presented in Figure 8. It can be seen that I_ds is independent of H_g1/2.

Next, to investigate the effect of T_j on device performance, I_ds-V_gs characteristics, SS, and I_ON/I_OFF of DG-LTFET are presented for different T_j with fixed W_{rk_gate1} = 4.5 eV and W_{rk_gate2} = W_{rk_LTFET}, H_g1 = H_nonoffset = 40 nm, H_offset = 10 nm. and H_g2 = H_nonoffset − H_g1 + (H_offset − t_ox) = 8 nm in Figure 9a–c, respectively. It was found that the increasing T_j results in a degradation of the I_ON/I_OFF ratio. It is simply because of the increase in BTBT path length with the increase in T_j. The T_j of 5 nm was found to be optimum in this work as any further reduction will bring significant quantum confinement effect into play, which is well known to degrade device performance [4,5,13,14,15].

Next, the impact of varying H_s was investigated. I_ds-V_gs characteristics of the DG-LTFET for several H_s with fixed W_{rk_gate1} = 4.5 eV and W_{rk_gate2} = W_{rk_LTFET}, H_g1 = H_s = H_nonoffset, H_g2 = H_nonoffset − H_g1 + (H_offset − t_ox) = 8 nm, and T_j = 5 nm is presented in Figure 10. By maintaining H_g1 = H_s, H_offset = 10 nm, and H_g2 = 8 nm, the electric field vector distribution within the DG-LTFET remains the same as H_s is varied, and the BTBT area simply scales with H_s. An increase (decrease) in the BTBT area with H_s simply results in an increased (decreased) I_ON/I_OFF ratio as shown in Figure 10b with no change in SS, as evident from Figure 10a.

Finally, the ambipolar current of the DG-LTFET is discussed. Ambipolar I_ds of TFET depends on the drain-channel junction. In the DG-LTFET, the drain-channel junction is controlled by gate2 with W_{rk_gate2} = W_{rk_LTFET}. With the same workfunction, the electrostatics of the drain-channel junction in the DG-LTFET is exactly the same as that in the LTFET. Figure 11a shows ambipolar I_ds of the DG-LTFET compared with the LTFET. Any change in W_{rk_gate1} in the DG-LTFET does not affect the drain-channel junction. The same argument applies for any other design parameter variation in DG-LTFET including H_s, H_g1/2, and T_j; that is, as long as the electrostatics of the drain-channel junction remains unaffected, the DG-LTFET will exhibit an equivalent ambipolar I_ds as the LTFET. Further, the impact of N_d on ambipolar I_ds was considered. Different N_d values were considered for a DG-LTFET with W_{rk_gate1} = 4.5 eV and W_{rk_gate2} = W_{rk_LTFET}, H_g1 = H_nonoffset = 40 nm, H_g2 = H_offset − t_ox = 8 nm, and T_j = 5 nm, and the results are shown in Figure 11b. A drain doping level of 10¹⁸ cm⁻³ was found to suppress ambipolar I_ds appreciably without affecting the I_ON.

4. Conclusions

The device physics of the LTFET was investigated. It was found that a large part of the subthreshold region is dominated by the parasitic, lateral, 2D BTBT from the source to R_offset with a lower G_tun. The more efficient 1D BTBT from the source to R_nonoffset, with a higher G_tun takes place at a higher bias in the subthreshold region. In other words, the condition, that is, V_{th_Rnonoffset} > V_{th_Roffset}, exists in the LTFET. With R_nonoffset not conducting the device does not utilize its channel fully during the subthreshold region. A new type of device based on the LTFET was introduced in this work. The device uses a dual gate structure with W_{rk_gate1} < W_{rk_gate2}. This increases the potential in R_nonoffset and lowers V_{th_Rnonoffset}. The DG-LTFET reverses the threshold condition of the LTFET, that is, it lowers V_{th_Rnonoffset} and makes it <V_{th_Roffset}. R_nonoffset with higher G_tun turns on earlier than R_offset in the subthreshold region in the DG-LTFET and the device exhibits an SS of less than 10 mV/dec. It was found that W_{rk_gate1} in the DG-LTFET needs to be sufficiently less than W_{rk_gate2} to achieve the sub 10 mv/dec SS. It was found that I_ds and SS are independent of H_g1/2. The DG-LTFET was further evaluated for different device dimensions including T_j and H_s while maintaining the electric field vector distribution equivalent. I_ds decreases with an increase in T_j and scales with H_s. The N_d value of 10¹⁸ cm⁻³ was found to appreciably reduce ambipolar I_ds. With the results presented in this work, the DG-LTFET could be considered as a viable potential replacement to conventional MOSFET and 3D integrations [16].