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Open AccessArticle

Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope

Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, Anseong 17579, Korea
*
Author to whom correspondence should be addressed.
Electronics 2018, 7(11), 275; https://doi.org/10.3390/electronics7110275
Received: 12 October 2018 / Revised: 20 October 2018 / Accepted: 22 October 2018 / Published: 24 October 2018
(This article belongs to the Special Issue Nanoelectronic Materials, Devices and Modeling)

Abstract

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance.
Keywords: band-to-band tunneling; L-shaped tunnel field-effect-transistor; double-gate tunnel field-effect-transistor; corner-effect band-to-band tunneling; L-shaped tunnel field-effect-transistor; double-gate tunnel field-effect-transistor; corner-effect

1. Introduction

Tunnel field-effect-transistors (TFETs) are being actively pursued as a potential replacement to conventional metal-oxide-semiconductor (MOS) technology [1]. TFETs offer a sub-thermal subthreshold slope (SS) but suffer from limited ON current ION performance [2]. To overcome the limit, different types of line tunneling type TFETs have been introduced, including L-shaped [3] (LTFETs), U-shaped [4] (UTFETs), and Z-shaped [5] TFETs (ZTFETs). Among them, only the LTFET has been experimentally demonstrated [3].
It was found using device simulations that the 2D corner effect [6] present in LTFETs degrades its subthreshold performance. In order to remove SS degradation due to the kink effect induced by the source corner, the fully depleted rounded corner with a gradual doping profile was used [6]. The LTFET still achieves a sub-thermal SS, but as shown in this work there is room for significant improvement in the subthreshold performance of LTFETs. To achieve this improvement, a new device based on the original LTFET is introduced. The new device uses a dual-gate (DG) structure and is termed the DG-LTFET. The two gates (gate1 and gate2) have different workfunctions and different heights. The DG-LTFET was thoroughly evaluated for different device parameters, including the source region height, gate1 and gate2 heights, gate1 and gate2 workfunctions, channel thickness, and drain doping levels. Optimum dimensions and drain doping level were determined for the DG-LTFET. Section 2 briefly discusses the corner-effect problem of the LTFET. Section 3 introduces the DG-LTFET and compares its results with the LTFET. Section 4 presents the conclusion.

2. The LTFET: The Corner Effect

Figure 1 shows a schematic for LTFET. The p+ (1020 cm−3) doped source region overlaps the gate with the n (1012 cm−3) channel sandwiched in between them. This sandwiched channel region is termed as Rnonoffset. There is also a part of the channel termed Roffset in which there is an offset present between the source and the gate, as indicted in Figure 1. The following parameters were used for all devices considered in this work unless otherwise specified: source height (Hs) = 40 nm, oxide thickness (tox) = 2 nm, length of Rnonoffset (Tj) = 5 nm, channel length (Lch) = 50 nm, height of Roffset (Hoffset) = 10 nm, height of Rnonoffset (Hnonoffset) = Hs, gate height (Hg1) = Hs + (Hoffsettox) = 48 nm, dielectric permittivity εox = 25, metal gate workfunction Wrk_LTFET = 4.72 eV, and drain doping (Nd) = 1020 cm−3.
Sentaurus technology-computer-aided-design tool (TCAD) was used as the simulator [7]. The following models were used in the simulation: the dynamic nonlocal band-to-band-tunneling (BTBT) model, Fermi statistics, and the constant mobility model. The dynamic nonlocal BTBT model calculates BTBT in both lateral and 1D directions. Crystal orientation is assumed to be <100> in all devices. A constant electron effective tunneling mass of 0.19 mo was used in all simulations [8]. All simulations were performed at a drain source bias Vds = 0.1 V unless otherwise specified.
For analysis to follow, drain-source current (Ids) versus gate-source bias (Vgs) characteristics of the LTFET are shown in Figure 2a. There is a direct overlap between gate and source in Rnonoffset, and the electric field in Rnonoffset is in the 1D direction. In Roffset, however, the electric field from the gate converges around the sharp source corner marked by an X in Figure 1. This increases the potential in Roffset as compared to Rnonoffset for any given bias (until potential saturates due to electron inversion). Figure 2b shows the surface potential at Vgs = 0 V. It can be seen that, because the electric field converges around the sharp source corner [6], the potential in Roffset has increased. Since the potential is higher in Roffset as compared to Rnonoffset, the threshold voltage for BTBT in Roffset (Vth_Roffset) is lower than the threshold voltage for BTBT in Rnonoffset (Vth_Rnonoffset).
Figure 3a,b show the tunneling rate (Gtun) contour plot and Gtun, respectively, at Vgs = 0.21 V which is the bias needed to generate Ids = 10−13 A (from Figure 2a). It is obvious from Figure 3 that the BTBT only takes place in Roffset, whereas Rnonoffset is completely switched off. Figure 4a shows Gtun at several Vgs values. From Figure 4a, Vth_Roffset and Vth_Rnonoffset can be found to be around Vgs = 0.17 V and 0.24 V, respectively. Figure 4b shows the Gtun contour plot at Vgs = Vth_Rnonoffset = 0.24 V. Figure 4a shows that Gtun in Rnonoffset just after it turns on, is always higher and has a much larger BTBT area (in the y direction) as compared to Roffset. Thus, whenever Rnonoffset turns on, it dominates over Roffset. The reason why Gtun is higher in Rnonoffset is simply because the BTBT paths in Roffset are laterally oriented or 2D from source to the surface in Roffset, whereas the BTBT paths in Rnonoffset are 1D. The 2D BTBT paths being naturally longer than the 1D paths result in a lower Gtun in Roffset.
From Figure 4a, it can be observed that, for a large part of the subthreshold region (Vgs < 0.24 V), only Roffset with the longer 2D BTBT paths and lower Gtun is contributing to the BTBT current and the more efficient Rnonoffset makes no contribution to the current. In other words, the LTFET underperforms in the subthreshold region. If Rnonoffset could be forced to turn on at a lower bias than Roffset, which is the condition Vth_Rnonoffset < Vth_Roffset, Rnonoffset will turn on in the subthreshold region, and with the condition Gtun in Rnonoffset > Gtun in Roffset, demonstrated in Figure 4a, a significant improvement in SS could be expected.
In other words, the Rnonoffset could be regarded as a parasitic region with a parasitic, fringing capacitance originating from the bottom of the gate to the sharp source corner. Since the potential is different in this area (Figure 2b), the capacitance associated with this region is different from the Rnonoffset region. If Vth_Rnonoffset < Vth_Roffset could be achieved, as is demonstrated below, the effect of this parasitic capacitance could be practically eliminated, and this is the purpose of the device proposed below. Since drain is not in close proximity to Roffset/Rnonoffset, where the BTBT current is generated, gate-drain capacitance fringing capacitance is not expected to influence the potential and BTBT significantly at high frequency.

3. DG-LTFET

3.1. The DG-LTFET: Basic Device Physics

In order to achieve the condition Vth_Rnonoffset < Vth_Roffset, the DG-LTFET is presented in Figure 5a. DG-LTFET uses dual material gates denoted by gate1 and gate2, each with a different workfunction (Wrk_gate1/2) and height (Hg1/2). Hg1 = Hnonoffset = Hs = 40 nm, Hoffset = 10 nm, Hg2 = HnonoffsetHg1 + (Hoffsettox) = 8 nm, and Tj = 5 nm. Wrk_gate1 is always lower than Wrk_gate2. Wrk_gate2 is fixed at Wrk_LTFET = 4.72 eV for all DG-LTFET considered in this work. The DG-LTFET process-flow is indicated in Figure 5a. The process-flow is based on the LTFET process-flow [3]. The DG-LTFET process-flow follows the LTFET process-flow until the chemical vapor deposition (CVD) of gate2 (similar to the gate deposition in the LTFET). After this, two additional steps are required. The device is masked to protect the gate oxide and channel areas, and gate2 is selectively etched according to the desired height. Gate1 is then deposited in the recess created by gate2-etching by a low-temperature atomic layer deposition process. Similar dual-material gate structures have been extensively reported in the literature including [9,10,11].
Lower Wrk_gate1 results in an increased flatband voltage [12] (Vfb) in Rnonoffset as compared to Roffset. Figure 5b shows Vfb of DG-LTFET (red symbols) with Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET. Also shown for the reference is Vfb of the LTFET (blue symbols). Expectedly, the DG-LTFET potential increases in Rnonoffset. The potential does not change abruptly from gate1 to gate2 because of the presence of 2D effects around the source corner. Electric field from the bottom of gate2 converges around the source corner. Around the middle of Roffset, equilibrium is established between the two gates and DG-LTFET potential overlaps LTFET potential since Wrk_gate2 = Wrk_LTFET. With Wrk_gate1 < Wrk_gate2, the increased potential in Rnonoffset reduces Vth_Rnonoffset. If Wrk_gate1/2 are appropriately tuned with Wrk_gate1 < Wrk_gate2, the condition Vth_Rnonoffset < Vth_Roffset = 0.17 V can be achieved. Because Wrk_gate2 = Wrk_LTFET = 4.72 eV, Vth_Roffset (in the DG-LTFET) is equal to Vth_Roffset (in the LTFET).
Figure 6a–c show Ids-Vgs characteristics at different Wrk_gate1, SS, and ION/IOFF of the DG-LTFET with constant Wrk_gate2 = Wrk_LTFET = 4.72 eV for all DG-LTFET, respectively. Also shown for the reference is the Ids-Vgs characteristics of the LTFET (black squares). ION is extracted at Vgs = 0.7 V, and IOFF is defined as Ids = 10−17 A. With Wrk_gate1 = 4.675 eV (red circles), the Vth_Rnonoffset is reduced to 0.189 V. Compared with the LTFET, Rnonoffset now turns on earlier in the subthreshold region, along with Roffset. Since the BTBT is more efficient in Rnonoffset (Figure 4a) as compared to Roffset, Ids increases more rapidly within the subthreshold region.
Hence, just at the transition point, where Rnonoffset turns on (Vgs ~ 0.189), a kink appears in the Ids-Vgs curve. With Wrk_gate1 = 4.65 eV (green triangles), Vth_Rnonoffset is reduced to Vgs = 0.167 V and the condition Vth_Rnonoffset < Vth_Roffset is achieved, and DG-LTFET exhibits a remarkable SS with values less than 10 mV/dec as seen in Figure 6b. With Wrk_gate1 = 4.625 eV (blue stars), Vth_Rnonoffset reduces further to 0.1448 V, which is < Vth_Roffset. If Vth_Rnonoffset < Vth_Roffset is established, then any increase in Vth_RoffsetVth_Rnonoffset simply shifts the Ids-Vgs to the left without any change in SS as shown by the blue stars (Wrk_gate1 = 4.625 eV) and orange diamonds (Wrk_gate1 = 4.5 eV) in Figure 6a,b, respectively. An improvement of ~16% is observed in the ION/IOFF of the DG-LTFET (with Wrk_gate1 = 4.625 eV) over the LTFET.
Figure 7a shows the Gtun contour plot of DG-LTFET at a Vgs (= 0.172 V) bias needed to achieve an equivalent Ids of 10−13 A in DG-LTFET with Wrk_gate1 = 4.65 eV. Figure 7b shows the contour plot extracted from Figure 7a. For reference, Figure 7b also shows that Gtun needed to generate an equivalent amount of Ids in the LTFET (at a Vgs bias of 0.21 V, Figure 3b). As can be seen in Figure 7b, the LTFET needs contribution only from Roffset, but generating the same amount of Ids DG-LTFET depends heavily on Rnonoffset with some contribution from Roffset. Because Gtun in Rnonoffset is more efficient (Figure 4a), as the Vgs bias increases, Gtun increases exponentially in a much larger area in Rnonoffset, which results in the DG-LTFET exhibiting a much steeper subthreshold swing, while the LTFET continues to depend only on the inefficient BTBT in Roffset until around Vth_Rnonoffset = 0.24 V.

3.2. Device Optimization

To optimize device performance, the impact of variations in key parameters including Hg1/2, Hs/Tj, and Nd was investigated. To investigate the impact of Hg1/2 values, Ids-Vgs characteristics for the DG-LTFET at different Hg1 and Hg2 = HnonoffsetHg1 + (Hoffsettox) with fixed Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hs = Hnonoffset = 40 nm, Hoffset = 10 nm, and Tj = 5 nm is presented in Figure 8. It can be seen that Ids is independent of Hg1/2.
Next, to investigate the effect of Tj on device performance, Ids-Vgs characteristics, SS, and ION/IOFF of DG-LTFET are presented for different Tj with fixed Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hg1 = Hnonoffset = 40 nm, Hoffset = 10 nm. and Hg2 = HnonoffsetHg1 + (Hoffsettox) = 8 nm in Figure 9a–c, respectively. It was found that the increasing Tj results in a degradation of the ION/IOFF ratio. It is simply because of the increase in BTBT path length with the increase in Tj. The Tj of 5 nm was found to be optimum in this work as any further reduction will bring significant quantum confinement effect into play, which is well known to degrade device performance [4,5,13,14,15].
Next, the impact of varying Hs was investigated. Ids-Vgs characteristics of the DG-LTFET for several Hs with fixed Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hg1 = Hs = Hnonoffset, Hg2 = HnonoffsetHg1 + (Hoffsettox) = 8 nm, and Tj = 5 nm is presented in Figure 10. By maintaining Hg1 = Hs, Hoffset = 10 nm, and Hg2 = 8 nm, the electric field vector distribution within the DG-LTFET remains the same as Hs is varied, and the BTBT area simply scales with Hs. An increase (decrease) in the BTBT area with Hs simply results in an increased (decreased) ION/IOFF ratio as shown in Figure 10b with no change in SS, as evident from Figure 10a.
Finally, the ambipolar current of the DG-LTFET is discussed. Ambipolar Ids of TFET depends on the drain-channel junction. In the DG-LTFET, the drain-channel junction is controlled by gate2 with Wrk_gate2 = Wrk_LTFET. With the same workfunction, the electrostatics of the drain-channel junction in the DG-LTFET is exactly the same as that in the LTFET. Figure 11a shows ambipolar Ids of the DG-LTFET compared with the LTFET. Any change in Wrk_gate1 in the DG-LTFET does not affect the drain-channel junction. The same argument applies for any other design parameter variation in DG-LTFET including Hs, Hg1/2, and Tj; that is, as long as the electrostatics of the drain-channel junction remains unaffected, the DG-LTFET will exhibit an equivalent ambipolar Ids as the LTFET. Further, the impact of Nd on ambipolar Ids was considered. Different Nd values were considered for a DG-LTFET with Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET, Hg1 = Hnonoffset = 40 nm, Hg2 = Hoffsettox = 8 nm, and Tj = 5 nm, and the results are shown in Figure 11b. A drain doping level of 1018 cm−3 was found to suppress ambipolar Ids appreciably without affecting the ION.

4. Conclusions

The device physics of the LTFET was investigated. It was found that a large part of the subthreshold region is dominated by the parasitic, lateral, 2D BTBT from the source to Roffset with a lower Gtun. The more efficient 1D BTBT from the source to Rnonoffset, with a higher Gtun takes place at a higher bias in the subthreshold region. In other words, the condition, that is, Vth_Rnonoffset > Vth_Roffset, exists in the LTFET. With Rnonoffset not conducting the device does not utilize its channel fully during the subthreshold region. A new type of device based on the LTFET was introduced in this work. The device uses a dual gate structure with Wrk_gate1 < Wrk_gate2. This increases the potential in Rnonoffset and lowers Vth_Rnonoffset. The DG-LTFET reverses the threshold condition of the LTFET, that is, it lowers Vth_Rnonoffset and makes it <Vth_Roffset. Rnonoffset with higher Gtun turns on earlier than Roffset in the subthreshold region in the DG-LTFET and the device exhibits an SS of less than 10 mV/dec. It was found that Wrk_gate1 in the DG-LTFET needs to be sufficiently less than Wrk_gate2 to achieve the sub 10 mv/dec SS. It was found that Ids and SS are independent of Hg1/2. The DG-LTFET was further evaluated for different device dimensions including Tj and Hs while maintaining the electric field vector distribution equivalent. Ids decreases with an increase in Tj and scales with Hs. The Nd value of 1018 cm−3 was found to appreciably reduce ambipolar Ids. With the results presented in this work, the DG-LTFET could be considered as a viable potential replacement to conventional MOSFET and 3D integrations [16].

Author Contributions

Conceptualization, F.N. and Y.S.Y.; methodology, F.N. and Y.S.Y.; investigation, F.N. and Y.S.Y.; data curation, F.N.; writing—original draft preparation, F.N.; writing—review and editing, F.N., and Y.S.Y.; supervision, Y.S.Y.; project administration, Y.S.Y.; funding acquisition, Y.S.Y.

Funding

This research was funded by Ministry of Trade, Industry & Energy (MOTIE), project number 10054888 and Korea Semiconductor Research Consortium (KSRC) support program for the development of future semiconductor devices.

Acknowledgments

This work was supported by IDEC (EDA tool).

Conflicts of Interest

The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

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Figure 1. Schematic of the L-shaped tunneling field-effect-transistor (LTFET).
Figure 1. Schematic of the L-shaped tunneling field-effect-transistor (LTFET).
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Figure 2. (a) Ids-Vgs transfer characteristics of the LTFET. Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Potential along the cutline shown in the inset at Vgs = 0 V. Potential is higher in Roffset.
Figure 2. (a) Ids-Vgs transfer characteristics of the LTFET. Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Potential along the cutline shown in the inset at Vgs = 0 V. Potential is higher in Roffset.
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Figure 3. (a) Gtun contour plot at Vgs = 0.21 V, which is the bias needed to generate Ids = 10−13 A and (b) Gtun extracted from (a).
Figure 3. (a) Gtun contour plot at Vgs = 0.21 V, which is the bias needed to generate Ids = 10−13 A and (b) Gtun extracted from (a).
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Figure 4. (a) Gtun at different Vgs. (a) Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Gtun contour plot at Vgs = Vth_Rnonoverlap = 0.24 V. In (b), yellow arrow indicates the height of Rnonoffset.
Figure 4. (a) Gtun at different Vgs. (a) Vth_Rnonoffset = 0.24 V and Vth_Roffset = 0.17 V. (b) Gtun contour plot at Vgs = Vth_Rnonoverlap = 0.24 V. In (b), yellow arrow indicates the height of Rnonoffset.
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Figure 5. (a) Schematic of DG-LTFET with process-flow indicated alongside and (b) Vfb of DG-LTFET (red symbols) compared with that of the LTFET (blue symbols). In the DG-LTFET, Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET = 4.72 eV were used.
Figure 5. (a) Schematic of DG-LTFET with process-flow indicated alongside and (b) Vfb of DG-LTFET (red symbols) compared with that of the LTFET (blue symbols). In the DG-LTFET, Wrk_gate1 = 4.5 eV and Wrk_gate2 = Wrk_LTFET = 4.72 eV were used.
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Figure 6. (a) Ids-Vgs characteristics of DG-LTFET with different Wrk_gate1s and fixed Wrk_gate2 = Wrk_LTFET. Also shown are Ids-Vgs characteristics of the LTFET (black squares). (b) SS extracted from Ids-Vgs characteristics in Figure 8a. (c) ION/IOFF ratio extracted from Ids-Vgs characteristics in Figure 8a. Red circles: Wrk_gate1 = 4.675 eV; green triangles: Wrk_gate1 = 4.65 eV; blue stars: Wrk_gate1 = 4.625 eV; orange diamonds: Wrk_gate1 = 4.5 eV.
Figure 6. (a) Ids-Vgs characteristics of DG-LTFET with different Wrk_gate1s and fixed Wrk_gate2 = Wrk_LTFET. Also shown are Ids-Vgs characteristics of the LTFET (black squares). (b) SS extracted from Ids-Vgs characteristics in Figure 8a. (c) ION/IOFF ratio extracted from Ids-Vgs characteristics in Figure 8a. Red circles: Wrk_gate1 = 4.675 eV; green triangles: Wrk_gate1 = 4.65 eV; blue stars: Wrk_gate1 = 4.625 eV; orange diamonds: Wrk_gate1 = 4.5 eV.
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Figure 7. (a) Gtun contour plot of DG-LTFET at Vgs = 0.172 V, which is needed to generate Ids = 10−13 A and (b) Gtun extracted from (a) (red symbols). Also shown for reference is Gtun (blue symbols) of the LTFET at a Vgs bias needed to generate Ids = 10−13 A. In (a), yellow arrow indicates the height of Rnonoffset.
Figure 7. (a) Gtun contour plot of DG-LTFET at Vgs = 0.172 V, which is needed to generate Ids = 10−13 A and (b) Gtun extracted from (a) (red symbols). Also shown for reference is Gtun (blue symbols) of the LTFET at a Vgs bias needed to generate Ids = 10−13 A. In (a), yellow arrow indicates the height of Rnonoffset.
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Figure 8. Ids-Vgs characteristics for several Hg1/2s with Wrk_gate1/2 = 4.5 eV and Wrk_gate2 = Wrk_LTFET. Red squares, green circles, and blue triangles: Hg1 = 35, 37, and 40 nm, respectively.
Figure 8. Ids-Vgs characteristics for several Hg1/2s with Wrk_gate1/2 = 4.5 eV and Wrk_gate2 = Wrk_LTFET. Red squares, green circles, and blue triangles: Hg1 = 35, 37, and 40 nm, respectively.
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Figure 9. (a) Ids-Vgs characteristics of the DG-LTFET with different Tj and fixed Wrk_gate1 = 4.5 eV, Wrk_gate2 = Wrk_LTFET, and Hg1 = Hs = Hnonoffset = 40 nm, Hg2 = Hoffset (10 nm) − tox = 8 nm. (b) The SS of Ids-Vgs shown in Figure 8a. (c) ION/IOFF ratio of Ids-Vgs characteristics shown in Figure 8a. Red squares, green circles, and blue triangles: Tj = 5, 6 and 7 nm, respectively.
Figure 9. (a) Ids-Vgs characteristics of the DG-LTFET with different Tj and fixed Wrk_gate1 = 4.5 eV, Wrk_gate2 = Wrk_LTFET, and Hg1 = Hs = Hnonoffset = 40 nm, Hg2 = Hoffset (10 nm) − tox = 8 nm. (b) The SS of Ids-Vgs shown in Figure 8a. (c) ION/IOFF ratio of Ids-Vgs characteristics shown in Figure 8a. Red squares, green circles, and blue triangles: Tj = 5, 6 and 7 nm, respectively.
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Figure 10. Ids-Vgs characteristics of DG-LTFET with different Hs, fixed Wrk_gate1 = 4.5 eV, Wrk_gate2 = Wrk_LTFET, and Hg1 = Hs = Hnonoffset, Hg2 = Hoffset (=10 nm) − tox = 8 nm. (b) An ION/IOFF ratio of Ids-Vgs characteristics shown in (a). Red squares, green circles, blue triangles, magenta diamonds, and orange stars: Hs = 30, 35, 40, 45, and 50 nm, respectively.
Figure 10. Ids-Vgs characteristics of DG-LTFET with different Hs, fixed Wrk_gate1 = 4.5 eV, Wrk_gate2 = Wrk_LTFET, and Hg1 = Hs = Hnonoffset, Hg2 = Hoffset (=10 nm) − tox = 8 nm. (b) An ION/IOFF ratio of Ids-Vgs characteristics shown in (a). Red squares, green circles, blue triangles, magenta diamonds, and orange stars: Hs = 30, 35, 40, 45, and 50 nm, respectively.
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Figure 11. (a) Ids-Vgs characteristics of DG-LTFET at Vds = 0.5 V with different Wrk_gate1 and Wrk_gate2 = Wrk_LTFET, Hg1 = Hoffset = 10 nm, Hg2 = 8 nm, Tj = 5 nm and Nd = 1020 cm−3. Red circles, green triangles, blue diamonds, magenta stars, and orange right triangles: Wrk_gate1 = 4.7, 4.675, 4.65, 4.625, and 4.5 eV. (b) DG-LTFET Ids with different Nd. Nd = 1018 cm−3 demonstrates almost negligible ambipolar Ids. Red squares, green circles, blue triangles, magenta diamonds, and orange stars: Nd = 1018, 5 × 1018, 1019, 5 × 1019, and 1020 cm−3.
Figure 11. (a) Ids-Vgs characteristics of DG-LTFET at Vds = 0.5 V with different Wrk_gate1 and Wrk_gate2 = Wrk_LTFET, Hg1 = Hoffset = 10 nm, Hg2 = 8 nm, Tj = 5 nm and Nd = 1020 cm−3. Red circles, green triangles, blue diamonds, magenta stars, and orange right triangles: Wrk_gate1 = 4.7, 4.675, 4.65, 4.625, and 4.5 eV. (b) DG-LTFET Ids with different Nd. Nd = 1018 cm−3 demonstrates almost negligible ambipolar Ids. Red squares, green circles, blue triangles, magenta diamonds, and orange stars: Nd = 1018, 5 × 1018, 1019, 5 × 1019, and 1020 cm−3.
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