Phase Margin Circuit Design Based on Cascaded DC-DC Converter and Two-Stage Op-Amp with Cascode Compensation

Abstract

This paper proposes a Cascode phase compensation network structure for controlling Buck–Boost converters to achieve wide-bandwidth and high-speed operation. The proposed scheme relocates the compensation capacitor (C_C) from the traditional position “across the first-stage output and the second-stage output” to a new position “between the source of the first-stage Cascode common-gate transistor and the second-stage output.” By integrating their high common-mode rejection ratio and power supply rejection ratio, a global system loop with robust interference immunity is constructed. The results indicate that a dominant-pole frequency of 10 kHz is achieved with our proposed structure compared to the circuit without Cascode compensation, representing a tenfold increase. As a result, a phase margin (PM) of up to 58.36° is achieved, which is improved by 9.1%. This work can provide an effective reference for achieving stable and rapidly responsive power conversion.

1. Introduction

To promote the adoption of clean energy, renewable energy sources, represented by photovoltaic and wind power, are being widely utilized worldwide [1,2]. However, the inherent dynamic variability of these sources leads to fluctuations in their output power [3,4,5]. As a result, the power generated from renewables often fails to meet the load demand. The integration of energy storage systems with renewable sources has been recognized as an effective approach to compensate for these shortcomings and maintain stable load power [6,7,8,9]. Consequently, DC-DC converters have found widespread applications in various fields—including electric-vehicle charging systems, renewable energy integration, and portable electronics—playing a crucial role in this context [10,11,12]. Among them, the Buck–Boost converter offers significant advantages for both step-up and step-down voltage conversion [13]. Nevertheless, conventional silicon-based Buck–Boost converters are constrained by considerable semiconductor losses, which greatly limit their performance and efficiency [14].

To address the aforementioned challenges, researchers have conducted a series of studies focusing on DC-DC converters. A consistent conversion efficiency above 96% was achieved while maintaining a high output power range from 200 W to 500 W, by replacing Si-IGBT devices with cascaded GaN-FETs in a bidirectional Buck–Boost DC-DC converter [15,16]. Separately, a six-switch reconfigurable DC-DC converter was designed for thermoelectric energy harvesting interfaces. An instantaneous linear extrapolation-based maximum power point tracking technique was developed, ultimately achieving a peak end-to-end efficiency of 90.48% under operating conditions with a load current exceeding 500 μA [17]. To further enhance the conversion efficiency of DC-DC converters, a hybrid pulse-width modulation/pulse-frequency modulation (PWM/PFM) control scheme was proposed. When applied to a Buck DC-DC converter, seamless transition between PWM and PFM modes was achieved, with peak efficiencies reaching 97% and 94% in the respective modes [18]. In the structural design of Buck–Boost converters, the PM directly affected system stability and dynamic response. Generally, maintaining a PM between 45° and 60° was considered an ideal range [19]. In recent years, to enhance the PM of DC-DC converters, new control methods and technologies have been proposed. For instance, a self-loop function derivation technique based on AC conservation was introduced. By optimizing the power stage design through the addition of an LC harmonic trap filter, system stability was effectively improved and ripple was reduced. This approach increased the system’s PM from 46° to 49°, and decreased the ripple from 11 mVpp to 5 mVpp (a reduction of approximately 54%) [20]. To achieve a higher PM, methods such as compensation network optimization and improved control strategies were employed. For example, a novel phase lead compensation circuit structure was proposed. By integrating a capacitance multiplier with an input differential pair, a step-down converter design featuring both a high negative-power supply rejection ratio and a compact size was realized. Compared to traditional phase compensation schemes, this structure achieved superior transient response and stability with a PM of 60°, utilizing ultra-small passive components (3.7 pF + 600 kΩ). The negative-power supply rejection ratio was also significantly improved to 75 dB [21]. However, current research on the PM of DC-DC converters primarily concentrates on normal light-load conditions, often neglecting heavy-load scenarios [22]. Furthermore, the structures employed were relatively singular, predominantly relying on either Buck or Boost topologies. This resulted in a narrow voltage adaptation range and an inability to achieve polarity inversion.

This study focuses on the theoretical analysis and simulation-based validation of the proposed Cascode compensation structure, with physical implementation and experimental verification planned as subsequent work. Using a Buck–Boost converter as the validation platform, a cascaded architecture integrating a compensated two-stage operational amplifier with the Buck–Boost converter is developed. By comparing the optimized Miller Compensation with the proposed Cascode compensation scheme, the investigation centers on the enhancements in PWM modulation characteristics and system PM achieved by this combined structure under extreme heavy-load conditions. The paper was organized as follows: Section 2 introduces the principles and limitations of conventional compensation methods. Section 3 details the working principles and advantages of the cascaded topology employing a Cascode-compensated two-stage op-amp and a Buck–Boost converter. Section 4 presents and discusses the system results.

2. Basic Circuit

In the open-loop state, a two-stage operational amplifier, due to its internal multi-stage gain structure, is typically characterized by multiple low-frequency poles. Especially when the frequencies of the two dominant poles are close, the phase of its open-loop frequency response drops rapidly within the 0 dB bandwidth, resulting in a very poor open-loop PM. In closed-loop applications, the negative-feedback system constructed without frequency compensation becomes highly susceptible to self-oscillation due to the critically low loop PM. In switching power supply design, directly cascading such an uncompensated amplifier as the error amplifier with a dynamic power stage like Buck–Boost can further destabilize the entire voltage control loop, leading to the eventual collapse of the closed-loop system. The conventional core solution involves introducing Miller Compensation and its improved variants into the operational amplifier design. By leveraging the capacitor’s Miller effect, a high-frequency pole is pushed to a higher-frequency domain while a low-frequency dominant pole is created, thereby achieving “pole splitting.” Consequently, near the designated loop crossover frequency, the open-loop gain rolls off at a stable −20 dB/decade slope. Sufficient PM is thus provided at this frequency point to ensure the stable operation of the entire closed-loop system.

2.1. Miller Compensation

Based on the Miller effect’s characteristic of significantly reducing input impedance, a C_C is often bridged across the output and input of the second stage in a two-stage operational amplifier to improve the amplifier’s frequency response, as shown in Figure 1.

When the two-stage operational amplifier is integrated as a local loop into the system and global stability is achieved, the input voltages of the input differential pair M₄ and M₅ become equal. Consequently, the drain voltages of M₆ and M₇ are equal, allowing the further derivation that V_GS6 = V_GS7. Since the gate and drain of M₆ are connected, and the gate of M₈ is connected to the drain of M₇, the relationship V_GS6 = V_GS8 is obtained. This leads to the derivation of the relationship between the corresponding currents and the aspect ratios (W/L) for M₆ and M₈ as

$${\displaystyle \frac{I_{D6}}{{(W/L)}_6}}={\displaystyle \frac{I_{D8}}{{(W/L)}_8}}$$

(1)

Given that transistor M₂ serves as the tail current source for the first-stage amplifier, the current through M₆ is half of that through M₂, while the operating current of M₈ equals that of M₃. The relationships between M₂ and M₆, and between M₃ and M₈, are consolidated through Equation (1) to yield

$${\displaystyle \frac{{(W/L)}_8}{{(W/L)}_6}}={\displaystyle \frac{I_{D8}}{I_{D6}}}={\displaystyle \frac{2I_{D8}}{I_{D2}}}={\displaystyle \frac{2I_{D3}}{I_{D2}}}$$

(2)

Additionally, the currents for M₂ and M₃ are supplied by a current mirror from transistor M₁, and their current ratio equals the corresponding channel aspect ratios. Based on this relationship, the current ratio between M₂ and M₃ in Equation (2) can be directly represented by their respective aspect ratios.

$${\displaystyle \frac{{(W/L)}_8}{{(W/L)}_6}}={\displaystyle \frac{2{(W/L)}_3}{{(W/L)}_2}}$$

(3)

Equation (3) represents the current balance condition for the two-stage operational amplifier, designed to prevent M₈ or M₃ from entering the linear region.

Figure 2 presents the small-signal model of the two-stage operational amplifier with introduced Miller Compensation. The node equations for node 1 and node 2 are respectively given as Equations (4) and (5).

$$G_{m1}{V}_{in}+{\displaystyle \frac{V_X}{R_1}}+V_X{C}_{1}s-(V_{out}-V_X)C_{C}s=0$$

(4)

$${\displaystyle \frac{V_{out}}{R_2}}+V_{out}{C}_{L}s+G_{m2}{V}_X+(V_{out}-V_X)C_{C}s=0$$

(5)

Through simplification, the transfer function from V_out to V_in is obtained.

$${\displaystyle \frac{V_{out}(s)}{V_{in}(s)}}={\displaystyle \frac{G_{m1}{R}_1{G}_{m2}{R}_2(1-\frac{s{C}_C}{G_{m2}})}{1+s[R_1(C_1+C_C)+R_2(C_C+C_L)+G_{m2}{R}_1{R}_2{C}_C]+s^2(C_1{C}_C+C_C{C}_L+C_L{C}_1)R_1{R}_2}}$$

(6)

It can be determined that in the transfer function, the denominator contains a second-order term and the numerator contains a first-order term, thus indicating that the system has two poles and one zero. For the numerator, the zero can be expressed as

$$Z_{1,miller}={\displaystyle \frac{G_{m2}}{C_C}}$$

(7)

For the denominator in Equation (6), it can be rearranged as

$$1+({\displaystyle \frac{1}{p_1}}+{\displaystyle \frac{1}{p_2}})s+{\displaystyle \frac{1}{p_1{p}_2}}{s}^2$$

(8)

Based on the Miller effect, where p₂ >> p₁, the 1/p₂ term in the first-order term can be neglected. Subsequently, the specific values of p₁ and p₂ can be obtained by comparing the denominator expression. Within p₁, the third term is significantly larger than the first two; therefore, p₁ can be approximated as

$$p_{1,miller}={\displaystyle \frac{1}{R_1(C_1+C_C)+R_2(C_C+C_L)+G_{m2}{R}_1{R}_2{C}_C}}\approx {\displaystyle \frac{1}{G_{m2}{R}_1{R}_2{C}_C}}$$

(9)

In the expression for p₂, since C₁ represents the parasitic capacitance at the output of the first stage and is considerably smaller than both the load capacitor and the C_C, the first two terms can therefore be neglected. Consequently, p₂ can be expressed as

$$p_{2,miller}={\displaystyle \frac{G_{m2}{C}_C}{C_1{C}_C+C_C{C}_L+C_L{C}_1}}\approx {\displaystyle \frac{G_{m2}}{C_L}}$$

(10)

For Equation (8), it can be expanded into

$$({\displaystyle \frac{s}{p_1}}+1)({\displaystyle \frac{s}{p_2}}+1)$$

(11)

At this point, p₂ must be retained as a non-negligible term in the expansion. Consequently, the two system poles are solved as s₁ = −p₁ and s₂ = −p₂. Based on their values, both poles are located in the left half of the complex plane, while the zero resides in the right-half plane.

Due to the Miller effect of the C_C, a very large equivalent capacitance is presented at the input of the second stage in the two-stage operational amplifier. This significantly increases the load capacitance of the first gain stage, thereby pushing its dominant-pole frequency to a very low value. Consequently, the dominant pole and the non-dominant pole are effectively separated, ultimately achieving a satisfactory PM. However, the bridging capacitor inherently possesses bidirectional conductivity, establishing not only the feedback path necessary for the Miller effect but also creating a concurrent feedforward path. This feedforward path directly couples the input signal to the output, which introduces a right-half-plane zero into the system. Given that a right-half-plane zero severely deteriorates the system’s PM, merely applying basic Miller Compensation to a two-stage operational amplifier might not only be ineffective in optimizing the PM but could also adversely affect stability.

2.2. Miller Compensation with a Source Follower

To address the right-half-plane zero problem introduced by Miller Compensation, an effective improvement method involves inserting a source follower into the C_C path, with its structure shown in Figure 3. Specifically, the input terminal of this source follower is connected to the output terminal of the second-stage operational amplifier, while its output terminal drives the right plate of C_C. In this configuration, the forward signal path from the input to the output of the source follower remains conductive, thereby preserving the essential feedback loop. Conversely, the reverse path from the output back to the input is effectively blocked due to the inherent unidirectional gain characteristic of the source follower, which severs the feedforward path responsible for generating the right-half-plane zero. Consequently, this structure eliminates the stability issue caused by the right-half-plane zero while retaining the frequency response-shaping advantage of Miller Compensation.

Notably, the input of the source follower is directly taken from the output of the second-stage operational amplifier, so its output swing is strictly constrained by the input voltage range. Excessively high output voltage from the second-stage amplifier may cause the source follower to exit its normal operating region, leading to functional failure.

2.3. Miller Compensation with a Nulling Resistor

To address the output swing limitation introduced by the source follower, the compensation network can be redesigned by replacing the source follower with a nulling resistor. The improved structure is shown in Figure 4.

The corresponding small-signal model is shown in Figure 5. Based on the calculation method described in Section 2.1, node equations are formulated for the two nodes and the corresponding transfer function is derived.

$$G_{m1}{V}_{in}+{\displaystyle \frac{V_X}{R_1}}+V_X{C}_{1}s-(V_{out}-V_X){\displaystyle \frac{C_{C}s}{1+C_{C}s{R}_Z}}=0$$

(12)

$${\displaystyle \frac{V_{out}}{R_2}}+V_{out}{C}_{L}s+G_{m2}{V}_X+(V_{out}-V_X){\displaystyle \frac{C_{C}s}{1+C_{C}s{R}_Z}}=0$$

(13)

$${\displaystyle \frac{V_{out}(s)}{V_{in}(s)}}={\displaystyle \frac{G_{m1}{R}_1{G}_{m2}{R}_2[1-s{C}_C(\frac{1}{G_{m2}}-R_Z)]}{1+s\alpha +s^2\beta +s^3\gamma }}$$

(14)

$$\alpha =R_1(C_1+C_C)+R_2(C_C+C_L)+G_{m2}{R}_1{R}_2{C}_C+R_Z{C}_C$$

(15)

$$\beta =(C_1{C}_C+C_C{C}_L+C_L{C}_1)R_1{R}_2+(R_1{C}_1+R_2{C}_L)R_Z{C}_C$$

(16)

$$\gamma =R_1{R}_2{R}_Z{C}_1{C}_L{C}_C$$

(17)

The parasitic zero can subsequently be obtained by observing the numerator expression.

$$Z_{1,zr}=-{\displaystyle \frac{1}{C_C(R_Z-\frac{1}{G_{m2}})}}$$

(18)

When the nulling resistor R_Z is set slightly larger than 1/G_m2, the original right-half-plane zero is migrated to the left-half plane and positioned at a higher frequency, thereby significantly weakening its negative impact on the PM. This phenomenon indicates that the essential function of introducing the nulling resistor lies in attenuating the influence of the feedforward path. However, the transconductance G_m2 is often difficult to determine precisely, which directly affects the accuracy in selecting the closely related nulling resistor R_Z.

3. Circuit Design

To effectively address the current issues of slow load transient response, narrow voltage adaptation range, and inability to achieve polarity inversion in DC-DC converters, this paper proposes a wide-bandwidth, high-speed circuit architecture based on Cascode phase compensation. A Buck–Boost structure is employed to achieve polarity inversion capability for the converter, as illustrated in Figure 6. This architecture consists of two primary design sections: a bandwidth-optimized Cascode-compensated two-stage operational amplifier serving as the control front-end, and a high-speed PWM-driven Buck–Boost power stage acting as the execution back-end.

3.1. Cascode-Compensated Two-Stage Op-Amp Control for Bandwidth Optimization

An inherent right-half-plane zero problem exists in traditional Miller Compensation networks. To resolve this issue, a wide-bandwidth, high-speed-response compensation scheme based on the Cascode structure is designed in this paper, with its core configuration shown in Figure 7. In this scheme, the C_C is moved from its traditional position “bridging the first-stage output and the second-stage output” to a new location “between the source of the first-stage Cascode common-gate transistor (i.e., the constructed virtual ground) and the second-stage output,” thereby accomplishing a critical reconstruction of the conventional compensation path. Simultaneously, a controlled current source is introduced between the virtual ground and the first-stage output, ensuring its current value precisely and instantaneously replicates the current flowing through C_C. Based on this virtual ground construction and current replication mechanism, a compensation circuit capable of simultaneously maintaining feedback and blocking feedforward is implemented.

The small-signal model of the two-stage operational amplifier with introduced Cascode compensation is presented in Figure 8. Based on the calculation method outlined in Section 2.1, node equations are formulated for the two nodes, and the corresponding transfer function is derived.

$$G_{m1}{V}_{in}+{\displaystyle \frac{V_X}{R_1}}+V_X{C}_{1}s-V_{out}{C}_{C}s=0$$

(19)

$${\displaystyle \frac{V_{out}}{R_2}}+V_{out}{C}_{L}s+G_{m2}{V}_X+V_{out}{C}_{C}s=0$$

(20)

$${\displaystyle \frac{V_{out}(s)}{V_{in}(s)}}\approx {\displaystyle \frac{G_{m1}{R}_1{G}_{m2}{R}_2}{1+s{G}_{m2}{R}_1{R}_2{C}_C+s^2{R}_1{R}_2{C}_1(C_C+C_L)}}$$

(21)

For Equation (21), the numerator is considered as originating from the combination of the first-stage gain G_m1R₁ and the second-stage gain G_m2R₂ of the two-stage operational amplifier. The denominator constitutes a quadratic expression in s, from which the poles p₁ and p₂ are then derived.

$$p_{1,Cascode}={\displaystyle \frac{1}{G_{m2}{R}_1{R}_2{C}_C}}$$

(22)

$$p_{2,Cascode}={\displaystyle \frac{C_C}{C_1}}{\displaystyle \frac{G_{m2}}{C_L+C_C}}$$

(23)

When the output voltage V_out changes, the varying current is directed through the proposed circuit configuration and is injected via the C_C into the source (virtual ground) node of the Cascode transistor. This current subsequently merges with the static bias current at that node and flows into the Cascode transistor. This design process is equivalent to directly sourcing the current from C_C into the output node of the first stage, thereby fully preserving the feedback path of the loop.

Regarding the first pole, the principle of the Cascode compensation employed in this work aligns with that of classical Miller Compensation. Both utilize the Miller effect to amplify C_C by approximately the gain of the second-stage amplifier (G_m2R₂C_C), thereby forming a large time constant in the denominator of the transfer function to effectively lower the dominant-pole frequency. For the second pole, under the proposed Cascode compensation structure where C_L is much larger than C_C, the non-dominant-pole expression can be derived as

$$p_{2,Cascode}\approx {\displaystyle \frac{C_C}{C_1}}{\displaystyle \frac{G_{m2}}{C_L}}={\displaystyle \frac{C_C}{C_1}}{p}_{2,miller}$$

(24)

Here, C₁ represents the equivalent parasitic capacitance at the output node of the first stage, the value of which is typically significantly smaller than the C_C. Consequently, the proposed structure not only completely eliminates the right-half-plane zero but also enhances the non-dominant-pole frequency by a factor of C_C/C₁, thereby greatly extending the separation between the dominant and non-dominant poles. This characteristic allows the system to achieve a higher unity-gain bandwidth (UGBW) compared to traditional Miller Compensation while targeting an identical PM.

Additionally, compared to the issue in traditional Miller Compensation where C_C directly forms a feedforward path, the design introduces the Cascode transistor into the compensation loop. Any feedforward signal attempting to pass through C_C is forced to traverse the low-gain path (approximately 1/g_mR_ds) from drain to source of the Cascode transistor, thus being significantly attenuated. This design thereby fundamentally translates the functional blocking of the feedforward path into reality.

In summary, the Cascode compensation structure adopted in this work, by pushing the non-dominant pole to higher frequencies and completely blocking the feedforward path, fundamentally resolves the conflict between gain-bandwidth product and PM while preserving the dominant pole separation advantage of Miller Compensation. This structural design ensures that the error amplifier can respond to transients rapidly, smoothly, and without overshoot, thereby guaranteeing the excellent dynamic performance of the PWM control loop at its source.

3.2. High-Speed PWM-Controlled Buck–Boost Power Converter

To achieve system-level high dynamic response, a high-speed PWM-driven Buck–Boost power stage execution back-end is constructed, as shown in Figure 9. To precisely match the control speed of the high-bandwidth Cascode-compensated operational amplifier at the front-end, the PWM modulator of the Buck–Boost execution unit is co-optimized: a fast ramp generation and low-latency comparator circuit design is adopted to support higher switching frequency and reduce loop delay. This design enables the front-end output control voltage V_C to be compared with the internal ramp signal in real-time and with high precision, thereby dynamically generating switching pulses with highly corresponding duty cycles and ensuring the control signal is converted into power output with high efficiency and low latency. The design core of this “high-speed-response” power back-end lies in ensuring that the speed of its PWM modulation and switching dynamics is not lower than the bandwidth of the front-end signal chain, thereby eliminating any speed bottlenecks throughout the entire link. Ultimately, through the matched design of bandwidth and speed between the front-end and back-end, system-level performance synergy and transfer are achieved. This approach significantly enhances dynamic response capability and voltage regulation accuracy while ensuring stability.

3.3. The Effect of PWM Modulator Delay on Loop Gain

In closed-loop control systems for switching power supplies incorporating a PWM modulator, delay is one of the key factors affecting loop stability. Unlike ideal continuous-time systems, the processes of signal sampling, algorithm computation, and PWM register updates in digital control architectures inevitably introduce discrete-time delay into the loop. From the perspective of frequency-domain modeling, this delay is typically described in the form of e^−sTd, where T_d represents the total delay time from the sampling instant to the actual application of the PWM duty cycle. This component affects only the phase-frequency response of the system without altering the magnitude response. The phase lag introduced by this delay can be quantified as

$$\Delta \varphi (f)=-360°\times f\times T_d$$

(25)

In the equation, f represents the analysis frequency. In a typical digital control system, the total delay T_d generally ranges from 1.5 to 2 times the switching period T_s, and is primarily determined by the timing arrangement of ADC sampling and hold, controller computation, and PWM update.

This phase lag plays a critical role in influencing the loop gain T(s). When the loop achieves unity-gain at the crossover frequency fc, i.e., |T(j2Πfc)| = 1, the additional phase shift Δ(f_c) introduced by the delay accumulates with the inherent phase lag from stages such as the operational amplifier, power stage, and LC filter, directly leading to a compression of the system’s PM. If the total accumulated phase lag exceeds the sum of 180° and the target design margin, the loop faces a risk of oscillation. For systems pursuing high bandwidth, an increase in fc makes the phase degradation caused by delay more pronounced, thereby imposing stricter requirements on the design of the compensation network.

In the cascaded architecture of this study, the delay effect of the PWM modulator is particularly noteworthy. The front-end Cascode-compensated operational amplifier achieves high-bandwidth output through pole splitting and zero cancelation, and this output signal must be converted into switching actions of the power stage via the PWM modulator. To ensure that the high-bandwidth advantage of the front-end is not counteracted by the delay of the back-end, targeted optimization of the PWM modulator is required—such as employing fast ramp generation and low-latency comparator circuits—to minimize the value of T_d as much as possible, thereby maintaining sufficient PM throughout the entire link. Therefore, when modeling the loop gain T(s) and designing the compensation network, the PWM delay should be incorporated as a significant non-ideal factor to ensure that theoretical analyses and simulation results can accurately reflect the stability boundaries of the actual system.

3.4. Loop Gain and UGBW Definition

In switching power supply control loop design, the loop gain T(s) is regarded as a core metric for evaluating system stability and dynamic performance. For a voltage-mode-controlled Buck–Boost cascaded system, the loop gain is defined as the product of the cascaded transfer functions of the error amplifier, the PWM modulator, the power stage, and the feedback network. Consequently, the loop gain can be expressed as

$$T(s)=A(s)\cdot \beta \cdot G_{PWM}(s)\cdot G_{LC}(s)$$

(26)

$$G_{LC}(s)={\displaystyle \frac{1}{1+\frac{2}{Q{\omega }_0}+{(\frac{s}{{\omega }_0})}^2}}$$

(27)

Here, A(s) is denoted as the open-loop transfer function of the error amplifier (two-stage operational amplifier), the specific form of which depends on the adopted compensation structure. β = R_f2/(R_f1 + R_f2) is defined as the feedback division factor, which is generally independent of frequency. G_PWM(s) represents the transfer function of the PWM modulator. In a continuous-domain approximation, the PWM modulator can be regarded as a proportional element with a gain of 1/V_ramp. However, in an actual digital control system, the inherent sampling and update delay must be modeled using e^−sTd, where T_d is the total delay time. G_LC(s) is expressed as the transfer function of the LC filter in the Buck–Boost power stage operating in Continuous Conduction Mode (CCM).

For UGBW, it is defined as the crossover frequency f_c at which the loop gain magnitude is unity. A higher f_c corresponds to a faster system response to input or load variations. Once the analytical expression of T(s) is known, f_c can be determined. For multi-pole systems, numerical methods or approximate formulas are typically required for estimation. The four compensation structures investigated in this work exhibit distinct pole-zero configurations; consequently, the estimation approach for their UGBW differs accordingly.

Table 1. Summary of key pole locations and approximate UGBW expressions for each compensation structure.

Compensation Scheme	Dominant Pole p1	Second Pole p2	Approximate UGBW Expression
Traditional Miller Compensation	1/gm2R1R2CC	Gm2/CL	$f_c\approx {\displaystyle \frac{g{m}_1}{2\pi C_C}}\cdot {\displaystyle \frac{1}{\sqrt{1+{(f_c/p_2)}^2}}}$
Miller Compensation with Source Follower	1/gm2R1R2CC	Gm2/CL	$f_c\approx {\displaystyle \frac{g{m}_1}{2\pi C_C}}\cdot k_{buf},k_{buf}>1$
Miller Compensation with Nulling Resistor	1/gm2R1R2CC	Gm2/CL	Zero moved to LHP; fc slightly higher (if RZ > 1/gm2RZ)
Cascode Compensation with Virtual Ground (This work)	1/gm2R1R2CC	CC/C1 × Gm2/CL	$f_c\approx {\displaystyle \frac{g{m}_1}{2\pi C_C}}\cdot \sqrt{{\displaystyle \frac{C_C}{C_1}}}$

summarizes the key pole locations and approximate UGBW expressions for each structure. The validity of the aforementioned estimation methods is verified in subsequent sections of this paper, where the UGBW results obtained from different compensation structures are presented and discussed in conjunction with specific simulation data.

4. Results and Discussion

4.1. Setup

To systematically evaluate the impact of different local compensation structures on the stability of the cascaded Buck–Boost system, a comparative analysis is conducted between the proposed Broadband High-Speed Buck–Boost Architecture with Cascode Phase Compensation and three typical compensation schemes: Traditional Miller Compensation, Miller Compensation with Source Follower, and Miller Compensation with Nulling Resistor. The structures corresponding to each compensation scheme are illustrated in Figure 10.

In the circuit configuration, the aforementioned various two-stage operational amplifier compensation structures are cascaded with the DC-DC converter, and key components and signal parameters are explicitly defined. These include transistor dimensions (the width-to-length ratios of M₁~M₁₅), resistors (R_B, R_S, R_Z, R_load), and capacitors (C₀, C_C, C_L), as well as input signals and the duty cycle. The specific parameters are listed in

Table 2. Key components and signal parameters.

Parameter	Value	Unit	Parameter	Value	Unit
(W/L)1	37/1	µm	RS	1	KΩ
(W/L)2	37/1	µm	RZ	1	KΩ
(W/L)3	22/1	µm	Rload	1	Ω
(W/L)4	22/1	µm	C0	10	µF
(W/L)5	10/1	µm	CC	10	pF
(W/L)6	180/1	µm	CL	4	pF
(W/L)7	40/1	µm	VA	5	V
(W/L)8	40/1	µm	VB	−VA × D/(1 − D)	V
(W/L)9	40/1	µm	VIN	5	V
(W/L)10	40/1	µm	VIN_ac	500	µV
(W/L)11	40/1	µm	VIN_CM	900	mV
(W/L)12	36/1	µm	E0	VA − VB	V
(W/L)13	36/1	µm	I1	IC	/
(W/L)14	16/1	µm	I2	−IC	/
(W/L)15	20/1	µm	IC	−VB/Rload/(1 − D)	/
(W/L)16	15/1	µm	D	0.2	/
(W/L)17	15/1	um	(n1/n2) K0	1/D	/
L0	1	µH	(n1/n2) K1	1/(1 − D)	/
R0	5	mΩ	PDK	tsmcN65	/
RB	8.06	KΩ	Model File	toplevel.scs	/

. The simulations are performed using Virtuoso (version IC6.1.8-64b.83).

4.2. Load-Dependent Regulation of PM in Miller Compensation

The regulating effect of load on PM constitutes a crucial aspect in switching power supply control loop design. To investigate this characteristic, tests are initially conducted on a Buck–Boost loop employing traditional Miller Compensation under two distinct conditions: heavy load (R_load = 1 Ω) and light load (R_load = 10 Ω). The corresponding gain and phase frequency-domain characteristics are presented in Figure 11. Following the determination of the crossover frequency where the loop gain magnitude is 0 dB, the PM is calculated by measuring the difference between the phase value at this frequency and the critical phase of −180°. The results indicate that when the load changes from 1 Ω (heavy load) to 10 Ω (light load), the system PM increases significantly from 43.98° to 97.37°. Conversely, the UGBW decreases from 1.50 MHz to 1.02 MHz. The observations indicate that a Buck–Boost loop under light load can achieve a high PM, but at the cost of reduced bandwidth and slower response. Conversely, while a higher bandwidth can be maintained under heavy load, the PM (43.97°) approaches the stability threshold, indicating insufficient margin. The corresponding frequency-domain characteristics are listed in

Table 3. Frequency-domain characteristics under different load conditions.

Load Condition	−3 dB BW	PM	UGBW
heavy load	14.62 kHz	43.98°	1.50 MHz
light load	15.27 kHz	97.37°	1.02 MHz

. These data demonstrate the difficulty for traditional Miller Compensation networks to simultaneously achieve high stability and fast dynamic response across a wide load range, particularly due to the insufficient PM under heavy load conditions. Consequently, a trade-off between stability and dynamic response is required.

From the perspective of pole migration analysis, the variation in the load resistor R_load directly modulates the output pole frequency, expressed as f_p,out =1/(2πR_loadC_L). Under heavy-load conditions, f_p,out shifts toward higher frequencies, altering its spacing from the dominant pole and the non-dominant pole, thereby affecting the phase accumulation at the crossover frequency f_C. From the analysis of inherent system trade-offs, light-load conditions provide ample PM at the cost of limited bandwidth, while heavy-load conditions enhance bandwidth potential at the expense of reduced PM. This trade-off poses a fundamental challenge to the design of compensation networks, where an ideal compensation structure should be capable of actively reconciling this contradiction under load variations.

4.3. PM Optimization of the C_C

The pole-splitting effects in both Miller Compensation and Cascode compensation are regulated by the C_C. To investigate the regulatory role of the C_C on the frequency characteristics and system performance of traditional compensation networks, the gain and phase frequency-domain characteristics under different Miller C_C values are presented in Figure 12. The results indicate that increasing C_C significantly affects system performance: the PM is enhanced from 43.98° to 55.25°, indicating a marked improvement in stability; correspondingly, both the −3 dB BW and the UGBW decrease. Similarly, a trade-off relationship between “stability and bandwidth” exists in compensation design. The corresponding frequency-domain characteristics are listed in

Table 4. Frequency-domain data under different C_C.

Compensation Capacitance	−3 dB BW	PM	UGBW
1.5 pF	14.62 kHz	43.98°	1.50 MHz
10 pF	1.80 kHz	55.25°	631.44 kHz

. To address the insufficient PM of Miller Compensation under heavy-load conditions, the C_C is increased to 10 pF through parameter optimization. This adjustment effectively elevates the PM to a safer level (greater than 55°), though a sacrifice in partial bandwidth is still required as a trade-off.

In the closed-loop system formed by cascading a Miller-compensated two-stage operational amplifier with a Buck–Boost converter, the sensitivity of the PM to the load capacitor C_L is observed to exhibit a trend opposite to that obtained from standalone op-amp simulations. System-level simulations demonstrate that in standalone open-loop or unity-gain closed-loop configurations, an acceptable PM can still be achieved when C_L >> C_C. However, when C_L exceeds C_C in the cascaded system, the global PM deteriorates significantly and fails to meet design expectations. This discrepancy arises from the fundamentally different roles played by C_L in the two scenarios. When the op-amp is tested alone, C_L merely serves as the output load of the second stage (common-source stage), primarily influencing the output pole frequency determined by the output impedance Rout, expressed as f_p,out = 1/(2πR_outC_L). In this context, increasing C_L lowers this pole frequency; if it approaches the UGBW f_u, the PM of the op-amp itself decreases. In the cascaded system, however, C_L is no longer merely a load for the op-amp but becomes a critical component of the power stage output LC filter. Together with the power inductor L, it determines the double-pole frequency f_LC of the LC filter. If an increase in C_L causes f_LC to drop close to or below the loop crossover frequency f_C, the system is subjected to a superposition of the phase lag from the op-amp itself and the phase lag from the LC double pole at fc, inevitably leading to a sharp degradation of the total PM. A key constraint for system-level design is derived from this analysis: to ensure sufficient PM, the condition f_LC >> f_C must be satisfied. This requirement translates into a combined restriction on component parameters, meaning that a specific relationship between C_L and C_C must be maintained. The empirical observation from simulation results in this design—that “C_L cannot exceed C_C”—is precisely a numerical manifestation of the aforementioned theoretical constraint under the given parameter set.

4.4. PM Comparison of Different Structures

To ensure a fair and systematic comparison, all four compensation schemes were evaluated under an identical set of conditions. The C_C was fixed at 10 pF, as this value was determined from the parametric analysis in Section 4.3 to provide a satisfactory PM for the Miller-compensated baseline. The load was set to the heavy-load condition of R_Load = 1 Ω to focus on the most challenging scenario for stability. This controlled approach allows the inherent frequency characteristics—specifically the pole-zero configurations—of each distinct topology to be revealed and compared directly, without the confounding effects of individual retuning to different performance targets.

Under heavy-load conditions, a comparative analysis is conducted between the proposed broadband high-speed Buck–Boost circuit architecture with Cascode phase compensation and three alternative compensation schemes: “Traditional Miller Compensation,” “Miller Compensation with Source Follower,” and “Miller Compensation with Nulling Resistor.” The results are presented in Figure 13. In terms of −3 dB BW, the proposed Cascode compensation structure demonstrates outstanding performance, achieving a −3 dB BW of 60.34 kHz. This value is approximately 33 times that of the traditional Miller Compensation and the Miller Compensation with a Nulling Resistor scheme, and about 12 times that of the Miller Compensation with a Source Follower scheme. These results directly confirm that the Cascode structure, through its superior pole-splitting capability, can significantly extend the effective operating bandwidth of the system while ensuring stability. Regarding PM, all four structures provide adequate stability margins (all exceeding 53°). Among them, the PM of the Cascode compensation is 58.36°, which is comparable to that of the structure with a nulling resistor (57.41°). Furthermore, while achieving the highest bandwidth, the Cascode compensation does not exhibit a reduction in PM, validating its capability to balance bandwidth and stability. From the perspective of the UGBW, the scheme incorporating the source follower achieves the highest UGBW (985.83 kHz) due to its buffering effect, while concurrently exhibiting the lowest PM (53.211°) among the four schemes, indicating a compromise in stability. The UGBW of the Cascode compensation is 729.36 kHz, which is slightly lower than that of the source follower scheme. However, when combined with its exceptionally high −3 dB BW and excellent PM, the Cascode compensation demonstrates more balanced and overall advantageous frequency characteristics, as summarized in

Table 5. Frequency-domain data under different op-amp configurations.

Compensation Structure	−3 dB BW	PM	UGBW
Traditional Miller Compensation	1.80 kHz	55.25°	631.44 kHz
Miller Compensation with Source Follower	5.01 kHz	53.21°	985.83 kHz
Miller Compensation with Nulling Resistor	1.81 kHz	57.41°	629.90 kHz
Self-loop function derivation technique [19]	/	49°	/
Cascode Compensation with Virtual Ground (This work)	60.34 kHz	58.36°	729.36 kHz

.

4.5. Load Transient Response Analysis

To evaluate the dynamic regulation capability under load transients, load transient simulations are conducted for the four compensation schemes. The simulation conditions are as follows: the load current steps between 10 mA and 1 A (large-signal step) and between 125 mA and 126.25 mA (1% small-signal step under light-load condition, R_load = 10 Ω), with rise and fall times set to 1 ns. The steady-state output voltage is V_steady = −1.25 V. The recovery time is defined as the time required for the output voltage to enter and remain within a ±1% error band around its steady-state value. The transient response waveforms and key performance metrics are presented in Figure 14.

Under the large-signal step, all four compensation schemes exhibit nearly identical transient characteristics. This consistency arises from power stage-dominated transient behavior. Under such a large-signal step, the transient process is governed by the energy storage and release characteristics of the LC filter, rather than by the bandwidth of the error amplifier. At the instant of load current surge, charge is provided by the output capacitor C_L, and the initial undershoot depth is determined by ΔV ≈ ΔI_load × ESR + ΔI_load × Δt/C_L. The recovery time is primarily constrained by the inductor current slew rate ΔI_L/(V_in/L). These physical processes are identical for all compensation schemes, masking any differences arising from the compensation networks. Under the small-signal step, the output voltage deviation is extremely small, and the transient responses of the four schemes remain nearly indistinguishable. This further confirms that even under small perturbations, the power stage physical limitations continue to dominate the time-domain behavior, preventing the direct observation of compensation network differences in transient waveforms.

To reveal the inherent performance differences among the compensation structures, frequency-domain analysis is performed under both heavy-load and light-load conditions, with results summarized in

Table 6. Frequency-domain performance summary.

Condition	Compensation Structure	−3 dB BW	PM	UGBW
Heavy Load (1 Ω)	Traditional Miller Compensation	1.80 kHz	55.25°	631.44 kHz
	Miller Compensation with Source Follower	5.01 kHz	53.21°	985.83 kHz
	Miller Compensation with Nulling Resistor	1.81 kHz	57.41°	629.90 kHz
	Cascode Compensation with Virtual Ground (This work)	60.34 kHz	58.36°	729.36 kHz
Light Load (10 Ω)	Traditional Miller Compensation	1.81 kHz	97.00°	546.59 kHz
	Miller Compensation with Source Follower	5.03 kHz	101.24°	759.42 kHz
	Miller Compensation with Nulling Resistor	1.81 kHz	98.86°	541.49 kHz
	Cascode Compensation with Virtual Ground (This work)	62.13 kHz	108.97°	602.76 kHz

. Under heavy load, the proposed Cascode compensation achieves a −3 dB BW of 60.34 kHz—33 times higher than that of traditional Miller Compensation—while maintaining the highest PM. Under light load, the output pole naturally shifts to higher frequencies, reducing bandwidth differences among schemes; nevertheless, the Cascode structure still provides the best PM. Frequency-domain metrics are widely accepted indicators of dynamic response: a higher crossover frequency directly corresponds to faster response to small-signal disturbances. Therefore, the significant frequency-domain improvements of the proposed Cascode compensation substantiate its superior “rapid response” capability, even though this advantage is not directly observable in large-signal transient waveforms due to power stage dominance.

In summary, all four compensation schemes demonstrate satisfactory dynamic regulation capability in large-signal transients, with their similar responses arising from power stage physical limitations. The superiority of the Cascode compensation is clearly manifested in the enhancement of frequency-domain metrics, providing a fundamental guarantee for fast response and stable operation under heavy-load conditions.

5. Conclusions

Through theoretical analysis and simulation-based validation, this work demonstrates the superior performance of the proposed Cascode compensation architecture in achieving high bandwidth and high PM under heavy-load conditions. The results indicate that, compared to circuit designs without Cascode compensation, the proposed structure extends the gain roll-off point of the frequency response from 1 kHz to 10 kHz (a tenfold improvement), while achieving a PM of 58.36°, representing a 9.1% enhancement over the compared schemes. It should be noted that experimental validation has not been included in the current work and will be the focus of subsequent research. This study provides an effective design reference for achieving high-stability, fast-response power conversion systems.