A MPC and Novel 3D-SVPWM Modulation Coordinated Strategy for Zero-Sequence Circulating Current Suppression in Three-Phase Four-Leg Parallel-Inverter Systems

Abstract

The three-phase four-leg (3P4L) parallel-inverter system has been increasingly applied in the field of new energy power generation due to its capability of feeding single-phase loads. However, zero-sequence circulating current (ZSCC) can jeopardize the stable operation of the parallel-inverter system. To address this issue, this paper proposes a ZSCC suppression strategy based on the coordination of Model Predictive Control (MPC) and an improved 3D-SVPWM technique. Firstly, an overall methodology is established by introducing a regulation factor into each switching cycle of the inverter modulation. This introduction enables flexible adjustment of the zero-sequence duty cycle difference between the two inverters, laying the foundation for ZSCC suppression. Secondly, the MPC algorithm is applied to construct a transfer function model of the parallel system incorporating the regulation factor. Closed-loop feedback of ZSCC is introduced, using the deviation between the actual ZSCC and zero as the cost function, and the zero-vector duty cycle adjustment margin as the constraint. The optimal regulation factor is calculated and injected into the improved 3D-SVPWM. Through receding horizon optimization within MPC, disturbances are actively predicted and compensated, achieving precise ZSCC suppression. Finally, simulation results based on Matlab and hardware-in-the-loop (HIL) verify the effectiveness of the proposed strategy.

1. Introduction

In recent years, the strategic goal of constructing new-type power systems has been proposed globally, with notable achievements made in the development of new energy represented by wind and photovoltaic power generation [1,2,3]. Power electronic inverters enable efficient energy exchange between primary energy sources and the external grid in renewable energy systems [4], ensuring stable output and reliable grid integration of new energy power. As the installed capacity of renewable energy continues to expand, the penetration rate of power electronic inverters in the grid has been increasing year by year, leading to increasingly pronounced characteristics of power electronics in grid infrastructure [5]. Compared to three-phase three-leg inverters, the three-phase four-leg(3P4L) inverter provides a zero-sequence path for unbalanced loads through the addition of a fourth leg [6], thereby effectively overcoming the limitations of the three-leg structure when dealing with asymmetric loads. Furthermore, the four-leg inverter offers greater control freedom, enhanced load capability, and improved suppression of double-frequency power fluctuations on the grid side [7], contributing to its widespread application.

The introduction of an additional control degree of freedom in 3P4L inverters renders the conventional two-dimensional space vector modulation method inadequate, necessitating the adoption of 3D-SVPWM [8]. Traditional 3D-SVPWM typically employs the αβγ coordinate system [9,10] to determine the positions of space vectors. However, the use of this coordinate system requires complex matrix operations and square root calculations, which inevitably impose a significant computational burden on both software and hardware. Consequently, an improved method has been proposed that involves transforming the αβγ coordinate system into the abc coordinate system. Within this abc framework, voltage vector positions are determined. This approach effectively eliminates complex computational steps, significantly simplifies the calculation process, and is more conducive to digital implementation [11].

In new energy power generation systems, the increasing grid capacity and rising power levels have made single inverters insufficient to meet such demands. Therefore, to enhance the reliability and scalability of power generation systems, inverters are typically operated in parallel. This configuration reduces component stress while simultaneously increasing system capacity and reliability [12]. Among various parallel configurations, systems utilizing common AC and DC buses offer advantages in terms of cost-effectiveness, convenience, and equipment size. Consequently, this topology has gained widespread application and adoption across numerous scenarios [13]. However, parallel inverter systems with common AC and DC buses face the issue of zero-sequence circulating current(ZSCC). This circulating current can lead to harmonic distortion, unbalanced output power, and increased power losses, thereby compromising system stability [14,15].

To address this issue, improved high-impedance LCL filters are adopted as a hardware modification to suppress circulating currents. However, the added components inevitably increase the overall device volume and weight, thereby raising system costs. [16,17]. As an alternative, a hybrid modulation method has been proposed [18], which partitions the modulation process according to the magnitude of voltage vectors. While this approach demonstrates certain effectiveness in performance improvement, it inevitably introduces additional complexity into the control system, resulting in higher computational demands and more intricate implementation in practical applications. In contrast, a refined nonlinear control strategy introduced in [19] incorporates feedforward compensation to mitigate the impact of total disturbance on ZSCC. While effective, the associated algorithm remains relatively complex and requires further simplification to facilitate practical implementation. In comparison, interleaved pulse width modulation is adopted as an alternative strategy in [20]. While contributing to reduced total current harmonic distortion, this method simultaneously leads to an inevitable increase in system switching frequency.

In the field of controller research, Model Predictive Control (MPC) represents a significant and emerging direction. This approach optimizes system dynamic behavior through three core components: a prediction model, rolling optimization, and feedback correction. At each sampling instant, the controller predicts the system behavior over a finite future horizon based on the current state and calculates an optimal control sequence by solving a constrained optimization problem online. Only the first control action of this sequence is then implemented. At the next sampling instant, the process is repeated using updated measurement information, thereby forming closed-loop control. This mechanism endows MPC with advantages such as fast dynamic response and ease of engineering implementation [21], and it has now been extensively studied and applied across various fields.

In light of these considerations, a ZSCC suppression strategy is proposed in this paper, which coordinates MPC with an improved 3D-SVPWM technique. Within the 3D-SVPWM scheme implemented in the abc coordinate system, a modulation adjustment factor is introduced into each switching cycle of one inverter. This enables flexible regulation of the zero-sequence duty-cycle difference between the parallel inverters, thereby minimizing the zero-sequence voltage difference. Simultaneously, an MPC controller is employed to establish a model of the entire zero-sequence loop of the parallel system that incorporates the adjustment factor. Closed-loop feedback control of the ZSCC is thus achieved, leading to its effective suppression. Compared with other circulating current suppression methods, this approach applies the model predictive control algorithm to the ZSCC suppression strategy based on 3D-SVPWM. By leveraging the favorable predictive capability and disturbance rejection of MPC, it achieves enhanced adaptability to variations in system parameters and unknown disturbances, along with improved steady-state and dynamic performance. Consequently, more accurate and adaptable adjustment factors are generated under diverse operating conditions. This contributes to reduced switching device stress and system losses, optimized output current quality, and lower harmonic content. Thus, the overall effectiveness of the 3D-SVPWM-based ZSCC suppression method is enhanced, meeting the application requirements of various scenarios.

2. Three-Phase Four-Leg Parallel Inverter System and the Generation Mechanism of Zero-Sequence Circulating Current

2.1. Three-Phase Four-Leg Parallel Inverter System

The topology of the 3P4L inverter system adopted in this paper is shown in Figure 1. Both inverters share the same DC voltage and are connected to the same three-phase load after passing through respective LC filters.

In the three-phase coordinate system, the output voltage of each inverter can be defined as a function of the DC bus voltage and the average duty cycle, as shown in the following equation:

$$\left[\begin{array}{l}{V}_{fax}\\ V_{fbx}\\ V_{fcx}\\ V_{fnx}\end{array}\right]=V_{dc}\left[\begin{array}{l}{d}_{ax}\\ d_{bx}\\ d_{cx}\\ d_{nx}\end{array}\right]$$

(1)

where V_f represents the output voltage of each inverter, V_dc denotes the DC voltage, and the duty cycle of the upper switch in phase k (k = a, b, c, n) of inverter x (x = 1, 2) is expressed as d_kx.

According to Kirchhoff’s laws, the following is obtained:

$$\left\{\begin{array}{c}{L}_{fx}{\displaystyle \frac{d{i}_{fax}}{dt}}=d_{ax}{V}_{dc}-V_{acx}-L_{fx}{\displaystyle \frac{d{i}_{fnx}}{dt}}\\ L_{fx}{\displaystyle \frac{d{i}_{fbx}}{dt}}=d_{bx}{V}_{dc}-V_{bcx}-L_{fx}{\displaystyle \frac{d{i}_{fnx}}{dt}}\\ L_{fx}{\displaystyle \frac{d{i}_{fcx}}{dt}}=d_{cx}{V}_{dc}-V_{ccx}-L_{fx}{\displaystyle \frac{d{i}_{fnx}}{dt}}\end{array}\right.$$

(2)

$$i_{dc}=d_{a1}{i}_{fa1}+d_{b1}{i}_{fb1}+d_{c1}{i}_{fc1}+d_{n1}{i}_{fn1}$$

(3)

where L_f is the filter inductor of each inverter, if represents the phase current of the inverter, and V_ac, V_bc, V_cc denote the filter capacitor voltages of each inverter.

For the control of the 3P4L inverter, the split-sequence control method is employed. The inductor current and load voltage are first extracted and decomposed into positive components, negative components, and zero-sequence components. Each component is then transformed from the abc coordinate frame to the dq coordinate frame. Due to their equal magnitude and identical direction, the zero-sequence components require a modified transformation approach. Specifically, based on the zero-sequence component of phase A, the zero-sequence component of phase B is lagged by 120°, and that of phase C by 240°, thereby converting the zero-sequence components into representations within the abc frame. A schematic diagram of the modified zero-sequence components is provided in Figure 2. Subsequently, separate voltage and current double closed-loop control loops are implemented for each sequence. The resulting modulation signals are fed into the PWM modulation stage to generate PWM signals, which are then delivered to the inverter, thereby establishing closed-loop control of the entire 3P4L inverter.

The block diagram of the voltage-current closed-loop control for the zero-sequence components is shown in Figure 3. This loop also contributes to the suppression of the ZSCC in the system. To facilitate the subsequent analysis, only the transfer function of the current loop is considered in the establishment of the MPC model in this paper, as expressed in the following equation:

$$G_{PI,i}=K_{ip}+{\displaystyle \frac{K_{ii}}{s}}$$

(4)

2.2. Zero-Sequence Circulating Current Generation Mechanism Analysis

Under ideal conditions, no circulating current is generated if the parameters and operating states of the two inverters are identical. However, due to the presence of a ZSCC path in the parallel configuration, a zero-sequence voltage difference arises between the inverters when discrepancies exist in their control methods, hardware parameters, or line impedance characteristics. This voltage difference induces a ZSCC, which leads to output current distortion, increased power loss, reduced system stability, and negatively impacts system efficiency, reliability, and operational lifespan.

Specifically, for example, modulation mismatch is manifested as carrier wave asynchrony or modulation command deviations. Phase or frequency deviations in the carrier wave directly lead to misaligned switching instants and generate high-frequency pulse-type zero-sequence voltage differences. Meanwhile, the zero-sequence components present in amplitude or phase errors of the reference voltage cannot be canceled by the load, thereby directly transforming into voltage differences that drive the zero-sequence loop. Their spectrum typically exhibits characteristics of high-frequency switching ripples superimposed on low-frequency fundamental components.

Additionally, the dead-time effect introduces zero-sequence voltage differences through nonlinear mechanisms. This is reflected in the fact that during the dead-time period, the output voltage is determined by the current direction and freewheeling path, making the voltage error current-dependent. Even if the dead-time settings are identical across units, current disparities can lead to inconsistent output voltage distortion, thereby forming zero-sequence voltage differences. Moreover, this effect injects significantly low-order zero-sequence harmonic components into the system, predominantly third-order harmonics.

Similarly, sampling and computational delays cause response inconsistencies in dynamic timing. During transient processes, differences in control loop delays among units can trigger response asynchrony, resulting in transient zero-sequence voltage differences. Under steady-state conditions, fixed delay differences are equivalent to introducing constant phase offsets into each modulation wave, and their zero-sequence components similarly produce sustained zero-sequence voltage differences, manifested as transient spikes during dynamics and fixed phase deviation components related to the fundamental wave in steady state. Therefore, differences in modulation or control between the two inverters in the parallel system generate zero-sequence voltage differences between the parallel converters. These differences drive significant ZSCC through the low-impedance zero-sequence loop, which can lead to output current distortion, increased power losses, reduced system stability, and adversely affect system efficiency, reliability, and operational lifespan.

According to the definition of ZSCC, the zero-sequence currents in the two parallel inverters are equal in magnitude and opposite in direction. Thus, the following relationship can be derived:

$$\left\{\begin{array}{c}{i}_{z1}=i_{fa1}+i_{fb1}+i_{fc1}+i_{fn1}\\ i_{z2}=i_{fa2}+i_{fb2}+i_{fc2}+i_{fn2}\end{array}\right.$$

(5)

$$i_z=i_{z1}=-i_{z2}$$

(6)

where i_z1 and i_z2 represent ZSCC of inverter1 and 2.

Based on the topology of the 3P4L parallel inverter system, relationship (7) can be derived from Kirchhoff’s laws and further simplified to (8).

$$(L_{f1}+L_{f2}){\displaystyle \frac{d{i}_z}{dt}}=(d_{z2}-d_{z1})V_{dc}=V_{zsv2}-V_{zsv1}$$

(7)

$$I_{z(s)}={\displaystyle \frac{\Delta V_{zsv(s)}}{(L_{f1}+L_{f2})s}}$$

(8)

where L_f1 and L_f2 represent filter inductances of two inverter circuits, and d_z1 and d_z2 represent the zero-sequence duty ratio of two inverters, V_zsv1 and V_zsv2 represent the zero-sequence voltages of inverter1 and inverter2, respectively, and ΔV_zsv(s) represents the difference between zero-sequence voltages of the two inverters. The derivation of these formulas is based on the topology of a 3P4L inverter and conducted in accordance with Kirchhoff’s laws. Components such as capacitors are excluded from the analytical circuit. Moreover, this method retains the characteristics of the 3P4L inverter and remains effective under unbalanced and nonlinear load conditions.

The above expression indicates that the zero-sequence voltage difference between the two inverters is the primary cause of ZSCC. Therefore, effective suppression of the ZSCC can be achieved by controlling and eliminating this voltage difference. Furthermore, since the ZSCC in parallel inverters are equal in magnitude and opposite in direction, controlling the ZSCC of only one inverter can effectively suppress the ZSCC in the entire system. This feature implies that by adjusting the modulation strategy of a single inverter, the goal of suppressing ZSCC in the parallel system can be accomplished, thereby simplifying the complexity of the control system.

3. Proposed 3D-SVPWM Modulation Strategy

3.1. 3D-SVPWM in the abc Coordinate System

As discussed previously, the 3D-SVPWM modulation strategy can be implemented in two coordinate systems: the αβγ frame and the abc frame. In comparison, the abc-frame approach more effectively eliminates complex computational steps, significantly improves operational efficiency, and is more conducive to digital implementation. Therefore, in this study, the 3D-SVPWM modulation strategy is improved and optimized based on the abc coordinate system. This chapter briefly outlines the fundamental aspects of the 3D-SVPWM modulation strategy in the abc coordinate system.

According to the topology of the 3P4L inverter, the inverter is composed of four legs, resulting in 16 switching states that correspond to 16 voltage vectors. These voltage vectors collectively form a dodecahedron structure. Geometrically, this dodecahedron can be regarded as being composed of two cubes with a side length of 1, where the side length represents the per-unit value of the DC bus voltage, U_dc. Based on the switching logic of the inverter, the voltage vector table shown in

Table 1. Output Voltage Vectors in the abc Coordinate System.

Number	Switch Status (SaSbScSf)	UafUbfUcf
V1	0000	0 0 0
V2	0010	0 0 1
V3	0100	0 1 0
V4	0110	0 1 1
V5	1000	1 0 0
V6	1010	1 0 1
V7	1100	1 1 0
V8	1110	1 1 1
V9	0001	−1 −1 −1
V10	0011	−1 −1 0
V11	0101	−1 0 −1
V12	0111	−1 0 0
V13	1001	0 −1 −1
V14	1011	0 −1 0
V15	1101	0 0 −1
V16	1111	0 0 0

can be constructed. In this table, S_a, S_b, S_c, and S_f represent the switching states of the four legs of the inverter, where “1” indicates that the upper switch is on and the lower switch is off, and “0” indicates the opposite. The voltage vector U_af, U_bf, U_cf describes the voltage relationship between the legs. Among these vectors, V₁ and V₁₆ are two zero-voltage vectors, while the remaining 14 vectors represent non-zero voltage vectors.

To facilitate calculation, switching functions are defined to represent the on/off states of the switches, as expressed in the following equation:

$$S=\left\{\begin{array}{c}0\hspace{1em}\hspace{1em}(\mathrm{the} \mathrm{upper} \mathrm{switch} \mathrm{off} \mathrm{and} \mathrm{lower} \mathrm{switch} \mathrm{on})\\ 1\hspace{1em}\hspace{1em}(\mathrm{the} \mathrm{upper} \mathrm{switch} \mathrm{on} \mathrm{and} \mathrm{lower} \mathrm{switch} \mathrm{off})\end{array}\right.$$

(9)

Based on Table 1, the spatial voltage vector distribution in the abc coordinate system can be obtained, with the specific spatial vector diagram shown in Figure 4. In this coordinate system, the 16 voltage vectors are divided into 24 small tetrahedra. The exact position of a voltage vector is determined by identifying the tetrahedron in which the reference voltage vector is located. Specifically, the three non-zero voltage vectors that synthesize the reference voltage vector are first identified. Their respective dwell times are then calculated. Finally, these vectors are combined in a predetermined sequence to realize the three-dimensional space vector pulse width modulation (SVPWM) strategy in the abc coordinate system. The detailed procedure is outlined as follows:

(1) Reference Position Determination

The voltage reference in the 3D-SVPWM modulation strategy based on the abc coordinate system is determined by the pointer function. Six m values and a pointer function RP must first be defined as shown in Equations (10) and (11).

$$\begin{array}{l}{m}_1=\left\{\begin{array}{c}1 (U_{a\_ref}\ge 0)\\ 0 (U_{a\_ref}<0)\end{array}\right.\hspace{1em}\hspace{1em}{m}_4=\left\{\begin{array}{c}1 (U_{a\_ref}-U_{b\_ref}\ge 0)\\ 0 (U_{a\_ref}-U_{b\_ref}<0)\end{array}\right.\\ m_2=\left\{\begin{array}{c}1 (U_{b\_ref}\ge 0)\\ 0 (U_{b\_ref}<0)\end{array}\right.\hspace{1em}\hspace{1em}{m}_5=\left\{\begin{array}{c}1 (U_{b\_ref}-U_{c\_ref}\ge 0)\\ 0 (U_{b\_ref}-U_{c\_ref}<0)\end{array}\right.\\ m_3=\left\{\begin{array}{c}1 (U_{c\_ref}\ge 0)\\ 0 (U_{c\_ref}<0)\end{array}\right.\hspace{1em}\hspace{1em}{m}_6=\left\{\begin{array}{c}1 (U_{a\_ref}-U_{c\_ref}\ge 0)\\ 0 (U_{a\_ref}-U_{c\_ref}<0)\end{array}\right.\end{array}$$

(10)

$$RP=1+{\displaystyle \sum _{i=1}^6{m}_i·2^{(i-1)}}$$

(11)

In the above equations, the values of m₁ to m₆ are either 0 or 1. The pointer function RP is calculated to identify 24 distinct RP values, each corresponding to one of the 24 possible tetrahedra, thereby determining the voltage vector combination that constructs the reference voltage value. In the theoretical model, although scenarios where all three phase voltages are simultaneously positive or negative can be envisioned, such cases are not feasible in practical operation. Therefore, tetrahedra associated with these unrealistic conditions are identified as invalid. Through detailed analysis, combinations where U_af, U_bf, and U_cf are all positive or all negative are excluded, ultimately confirming 12 valid RP values (5, 7, 13, 14, 19, 23, 42, 46, 51, 52, 58, 60) [22]. The voltage vectors corresponding to these valid RP values, as listed in

Table 2. Voltage Vectors Corresponding to Effective RP.

RP	Voltage Vector	RP	Voltage Vector
5	V2V10V12	42	V5V13V14
7	V2V4V12	46	V5V6V14
13	V2V10V14	51	V3V11V15
14	V2V6V14	52	V3V7V15
19	V3V11V12	58	V5V13V15
23	V3V4V12	60	V5V7V15

, are essential for the voltage synthesis process.

(2) Calculation of Voltage Vector Dwell Times

Once the synthesized voltage vector is determined, it is necessary to calculate the dwell time for each vector. The specific calculation method for tetrahedron 5 is as follows:

$$U_{ref}{T}_s=\left[\begin{array}{l}{U}_{a\_ref}\\ U_{b\_ref}\\ U_{c\_ref}\end{array}\right]T_s=\left[\begin{array}{ccc}{V}_{2a}& V_{10a}& V_{12a}\\ V_{2b}& V_{10b}& V_{12b}\\ V_{2c}& V_{10c}& V_{12c}\end{array}\right]\left[\begin{array}{l}{T}_1\\ T_2\\ T_3\end{array}\right]$$

(12)

$$\left[\begin{array}{l}{T}_1\\ T_2\\ T_3\end{array}\right]={\left[\begin{array}{ccc}{V}_{2a}& V_{10a}& V_{12a}\\ V_{2b}& V_{10b}& V_{12b}\\ V_{2c}& V_{10c}& V_{12c}\end{array}\right]}^{-1}\left[\begin{array}{l}{U}_{a\_ref}\\ U_{b\_ref}\\ U_{c\_ref}\end{array}\right]T_s$$

(13)

In the equations, V_2a, V_2b, and V_2c represent the components of voltage vector V₂ in the three-phase coordinate system. Similarly, the components of other voltage vectors can be expressed in the same manner. T₁, T₂, and T₃ denote the dwell times corresponding to the three vectors, while U_{a_ref}, U_{b_ref}, and U_{c_ref} are defined as the reference voltage values in the three-phase system.

For tetrahedron 5, as indicated in the previous table, the projections of V₂, V₁₀, and V₁₂ on the abc axes are (0, 0, 1), (−1, −1, 0), and (−1, 0, 0), respectively. Based on this, the final duty cycles within this tetrahedron can be derived.

(3) Determining the Switching Sequence of Voltage Vectors and Generating PWM Signals

After the dwell times of the voltage vectors are determined, the switching sequence of the vectors corresponding to the tetrahedron for each RP value must be established. The following fundamental principles must be adhered to when defining this sequence: First, to reduce switching losses, the timing and placement of the vectors should be symmetric about the midpoint of the switching cycle. Second, sequentially adjacent vectors should be prioritized to minimize changes in switching states.

Once the vector sequence is optimized, the final PWM signals are generated by calculating the effective on-time for each phase. Taking the tetrahedron with RP = 5 as an example, as shown in Figure 5, the corresponding voltage vectors V₁, V₂, V₁₀, V₁₂, and V₁₆ are arranged according to the principles above. The sequence begins with a combination of V₂ and V₁₀, transitions to a combination of V₁₀ and V₁₂, and finally returns to a zero vector. This approach achieves optimal switching performance while maintaining the accuracy of the output voltage.

In this 3D-SVPWM modulation strategy, the sum of all vector duty ratios satisfies the following relation,

$$d_{1x}+d_{2x}+d_{3x}+d_{0x}=1$$

(14)

where x denotes the inverter (x = 1 or 2), d_1x, d_2x, d_3x, d_0x represent duty ratios of non-zero vectors and zero-vectors.

This is obtained by defining the zero-sequence duty ratios and simplifying it according to the above equation:

$$\begin{array}{c}{d}_{zx}=d_{ax}+d_{bx}+d_{cx}+d_{nx}\\ \hspace{1em}\hspace{1em} =d_{1x}+2d_{2x}+3d_{3x}+2d_{0x}\\ \hspace{1em}\hspace{1em} =-d_{1x}+d_{3x}+2\end{array}$$

(15)

3.2. The Proposed Modified 3D-SVPWM

As derived from the previous analysis, the magnitude of the ZSCC in a parallel system is influenced by the value of the zero-sequence voltage difference, which is in turn determined by the zero-sequence duty cycle. Therefore, modifying the zero-sequence duty cycle can suppress the ZSCC. Moreover, in theory, variations in the duty cycle of the zero vectors do not affect the control objectives or output quality of the parallel system. Meanwhile, changes in the zero-sequence duty cycle alter the dwell times of the zero vectors. Thus, the effect of zero-sequence duty-cycle variation can be reflected by changes in the zero-vector dwell times.

In light of this, an improved 3D-SVPWM modulation method is proposed in this paper. Through closed-loop feedback control of the ZSCC, the value of an adjustment factor is obtained. This adjustment factor is introduced into the switching cycle of the modulation strategy to regulate the difference in zero-sequence duty cycles, thereby driving the zero-sequence voltage difference to zero and achieving suppression of the ZSCC.

Figure 6 shows the distribution of state vectors and their duty cycles in each switching cycle of the modulation strategy before and after adjustment (taking the tetrahedron with RP = 5 as an example). An adjustment variable k is added to the zero-sequence duty cycle in each switching cycle. At this point, the dwell times of the two zero vectors V₁ and V₁₆ become (T₀/2 − 2kT_s) and (T₀/2 + 2kT_s), respectively. Consequently, the zero-vector duty cycles d_0x change to (d_0x/2 − 2k) and (d_0x/2 + 2k).

After the zero-sequence vector duty cycle is adjusted, the corresponding relationship also changes, as shown in the following equation:

$$\begin{array}{l}{d^{\prime }}_{zx}={d^{\prime }}_{ax}+{d^{\prime }}_{bx}+{d^{\prime }}_{cx}+{d^{\prime }}_{nx}\\ =d_{1x}+2d_{2x}+3d_{3x}+2d_{0x}-8k\\ =-d_{1x}+d_{3x}+2-8k\end{array}$$

(16)

Therefore, the zero-sequence voltage difference is expressed as:

$$\begin{array}{l}\Delta d_{zx}={d^{\prime }}_{z2}-{d^{\prime }}_{z1}\\ =d_{11}-d_{12}+d_{32}-d_{31}-8k\end{array}$$

(17)

Also because,

$$\Delta V_{zsv}=\Delta d_{zx}{V}_{dc}$$

(18)

So the expression for the ZSCC can also be written as:

$$I_{z(s)}={\displaystyle \frac{\Delta d_{zx(s)}{V}_{dc}}{(L_{f1}+L_{f2})s}}$$

(19)

As can be seen from the above equation, the adjustment factor can effectively alter the zero-sequence voltage difference, thereby suppressing the ZSCC.

4. Derivation Method of the Adjustment Factor Based on Model Predictive Control

In this paper, the value of the adjustment factor k is determined and dynamically adjusted using the MPC method. It is then fed into the 3D-SVPWM scheme, enabling dynamic regulation of the zero-sequence voltage difference and thereby further suppressing the ZSCC.

4.1. Fundamental Principles and Design Strategies of MPC

MPC is an advanced control strategy based on a predictive model, rolling optimization, and feedback correction. Its core concept lies in utilizing a predictive model of the controlled object to simulate the system’s dynamic behavior over a finite future horizon at each current time step. An optimal control sequence is then determined by solving a constrained optimization problem online. Only the first control action of this sequence is implemented. At the next sampling instant, the entire process is repeated based on the latest measured information. A detailed control block diagram is shown in Figure 7.

(1) Prediction Model

MPC operates by utilizing a mathematical model of the process to forecast future system outputs. This predictive model can be formulated through various representations, including state-space equations, transfer functions, step responses, or impulse responses. The accuracy and complexity of the model are of paramount importance, as they directly govern both controller performance and computational demand. In the methodology presented herein, the overall system control structure is analyzed. The transfer function derived from the system model is adopted as the foundational predictive model for the MPC design. A key consideration arises from the implementation of a sequence-decoupled control strategy within the 3P4L inverter. Specifically, the zero-sequence current closed-loop exerts a significant influence on the overall MPC performance. Consequently, a comprehensive analysis must account for the interaction between this zero-sequence control loop and the modified 3D-SVPWM suppression strategy. The corresponding transfer function model is shown in Figure 8.

The forward path corresponds to the Laplace-domain expression of the ZSCC in the main circuit. Within the feedback path, the parameters K_ip and K_ii respectively denote the proportional and integral gains of the PI controller in the zero-sequence current closed-loop, followed by the transfer function of the 3D-SVPWM stage. Accordingly, the overall system transfer function is derived as follows:

$${\displaystyle \frac{V_{dc}(T_{s}s+1)s}{K_{PWM}(K_{ip}s+K_{ii})V_{dc}-(T_{s}s+1)(L_1+L_2)s^2}}$$

(20)

where the DC-side voltage V_dc is 560 V, the parameters K_ip and K_ii in the feedback path are set to 6 and 0.001, respectively, the gain KPWM in the 3D-SVPWM transfer function is approximately 1, the switching period T_s equals 1 × 10⁻⁴ s, and the filter inductances L₁ and L₂ may vary depending on the application scenario.

In addition, the model incorporates the PWM delay, which is explicitly represented by introducing a time constant T_s into its transfer function. Structurally, the transfer function corresponds to a model containing a first-order inertial element. The adoption of this first-order inertial representation allows for a more faithful characterization of the system dynamics. As a result, the predictive model achieves improved correspondence with the physical system in both the frequency and time domains, thereby enhancing the prediction accuracy of the MPC.

(2) Receding Horizon Optimization

Within the rolling horizon control framework, an optimization problem over a finite time horizon is solved online during each sampling period based on the current system state. The objective function is designed as a quadratic cost function, which aims to balance output tracking performance with the cost associated with control input adjustments. The cost function formulated in this paper consists of two terms. The first term is the squared deviation between the predicted ZSCC and its reference value, serving to evaluate current tracking accuracy. The second term is the squared change in the control input between consecutive time steps, functioning to restrict excessive variations in the control action. Corresponding weighting coefficients are applied to regulate the relative importance of these two terms within the optimization process. Its mathematical representation is provided as follows:

$$J=q{(I_{z(n+1)}-I_{zref})}^2+r{(k_{(n+1)}-k_{(n)})}^2$$

(21)

where q denotes the weighting coefficient for the tracking error and r represents the penalty coefficient for the control increment, effective suppression of the ZSCC is achieved by setting the reference value I_zref to zero. The value of q is maximized according to the admissible control range and dynamic characteristics of the system to prioritize circulating current rejection. The coefficient r is selected to ensure the constraints on the control increment are satisfied, thereby guaranteeing smooth control actions and realizing the optimization objective without excessive system excitation.

Within the rolling optimization scheme of MPC, the entire future control sequence is not applied to the plant in a single instance. According to the fundamental principle of receding horizon control, only the first control action k(n) from this sequence is implemented as the actual system output. At the next sampling instant, the system state is updated with the latest measurement of the ZSCC, and the complete process of prediction, optimization, and solution is repeated. Simultaneously, the optimization horizon is shifted forward by one step. The key advantage of this mechanism lies in its periodic execution of finite-horizon optimization based on the most recent state information. This enables the system to continuously counteract model uncertainties, compensate for external disturbances, and strictly adhere to constraints, thereby achieving closed-loop optimal control that exhibits both robustness and real-time performance in dynamic environments.

However, this rolling optimization step also introduces an increased computational load. Compared with PI control, which is a typical linear feedback strategy requiring only proportional and integral operations on the error with a fixed structure and low computational burden, MPC must repeatedly execute online prediction and constrained optimization in each control cycle, leading to higher computational complexity. Nevertheless, MPC demonstrates superior dynamic performance and multi-constraint handling capability in suppressing ZSCC. Although its real-time computational demand is greater, no significant impact on overall system performance has been observed; instead, the suppression effect is notably enhanced. Therefore, this computational cost is acceptable in engineering practice.

(3) Feedback Correction

As an integral mechanism of MPC, feedback correction constitutes the essential link for realizing closed-loop optimization. In the proposed approach, the discrepancy between the actual and predicted ZSCC at each sampling instant is leveraged to perform corrective feedback. This involves updating the initial conditions of the prediction model to adjust the subsequent multi-step trajectory in real time, thereby effectively attenuating prediction inaccuracies stemming from model mismatch, parameter drift, and external disturbances. By continuously incorporating real-time measurements into the prediction initialization phase, a closed-loop corrective structure is embedded within the rolling optimization process. This mechanism substantially enhances both the robustness and the control accuracy of the overall system.

4.2. Overall Control Structure

Figure 9 illustrates the overall control block diagram of this study. For the parallel inverter system, the conventional control framework is retained. Specifically, three-phase load voltages and inductor currents are sampled from the circuits of both inverters. The sequence components are then extracted from these signals, and each component is transformed from the abc frame to the dq frame. Separate voltage and current double closed-loop controllers are applied to each component. After control, the signals are inversely transformed back to synthesize the sequence components, generating the modulation voltages. These modulation voltages are fed into the 3D-SVPWM generation modules of the two inverters, respectively. Finally, the generated PWM signals are delivered to the two inverters to complete the closed-loop control. Figure 9 illustrates the system architecture: the blue section denotes the control part, the yellow section the PWM signal generation part, and the orange section the improved MPC control part, with arrows indicating the direction of signal flow.

In this study, an additional closed-loop feedback control for ZSCC is incorporated into the PWM signal generation stage following the modulation voltage synthesis. Based on the zero-sequence current control loop of the second inverter, along with the DC-side voltage and the inductor parameters of both inverters, an MPC-based predictive control model is established. This model is fed into the MPC control module to generate an adjustment factor. The adjustment factor is then input to the 3D-SVPWM signal generation module of the second inverter. As a result, the modulation strategy of the second inverter is enhanced: while retaining the advantages of the original abc-frame-based 3D-SVPWM, the improved scheme adds the capability to suppress ZSCC in the parallel system, thereby increasing the practicality of the modulation strategy.

5. Simulation Results

To verify the feasibility of the improved 3D-SVPWM modulation strategy proposed in this paper, a simulation model of a 3P4L parallel inverter system was built on the MATLAB/Simulink platform R2023a. In this simulation, the sampling frequency was set to 10 kHz, and the solver was configured as an automatic solver. The two inverters adopt a common AC/DC bus topology, with a DC-side voltage of 560 V and a filter inductance of 0.01 H. The three-phase load is a balanced resistive load of 10 Ω. According to the definition of ZSCC, the ZSCC of two parallel-connected inverters is equal in magnitude and opposite in direction. For the measurement of ZSCC with reference to Equations (5) and (6), the second inverter was selected as the target for improvement in the simulation. The sum of the phase currents of the second inverter was measured to represent the ZSCC in the system. To further evaluate the dynamic suppression effect of ZSCC, a corresponding simulation was performed. In the initial stage, no circulating current suppression strategy was applied so that the initial waveform characteristics could be observed. Subsequently, to facilitate the observation of dynamic variations, the suppression strategy was activated at t = 0.608 s, thereby enabling comparative analysis of the dynamic changes and suppression effects of the ZSCC.

For the second inverter, both MPC and PI control strategies are implemented, each combined with the improved 3D-SVPWM modulation to suppress ZSCC. This comparative setup is designed to highlight the superior performance of the MPC-based approach. Furthermore, to simulate circulating current issues caused by parameter mismatch in practical systems, scenarios with different filter inductances and unbalanced loads are analyzed. Specifically, the filter inductance of the second inverter is deliberately set to 0.005 H, and the load is configured as 10 Ω, 15 Ω, and 20 Ω across the three phases to introduce ZSCC.

Simulation results shown in Figure 10 indicate that significant ZSCC is present in the system when different filter inductances are used. After the proposed circulating current suppression strategy is applied, the ZSCC is notably suppressed. As shown in (a) and (b), the circulating current amplitude is greatly reduced and can be confined within the range of ±0.15 A. Compared with the PI controller, the MPC controller achieves approximately 25% improvement in suppression effectiveness, as shown in (c). The improved three-phase voltage waveforms are shown in (d), where each color represents the waveform of one phase voltage, demonstrating that the three-phase voltage output is maintained without substantial distortion. Furthermore, in (e)–(g), the output current THD of the second inverter is measured at 5.77% before suppression, decreases to 3.18% with PI-based suppression, and is further reduced to 2.63% under MPC suppression, showing a clear decline in THD and indicating improved output current quality. For the dynamic suppression performance, in (h) and (i), when PI control was applied, the ZSCC stabilized at 0.60812 s with a settling time of 0.00012 s. Its RMS value remained around 0.2 A. With MPC control, the settling time was also 0.00012 s while the RMS value stabilized around 0.15 A. No overshoot is observed in either control algorithm; the ZSCC is rapidly reduced to within the permissible range. Thus, it can be concluded that the proposed suppression method achieves favorable dynamic performance.

As shown in Figure 11, under unbalanced load conditions, a circulating current of about 1 A remains in the system. As shown in (a) and (b), the proposed method still exhibits suppression capability for such low-amplitude circulating current, restricting the ZSCC within ±0.05 A. Compared with traditional PI control, the adoption of the MPC algorithm further enhances the circulating current suppression effect by about 30%, as shown in (c). The improved three-phase voltage waveforms are shown in (d), where each color represents the waveform of one phase voltage. In addition, in (e)–(g), the output current THD of the second inverter is 1.69% before suppression, 1.37% after PI suppression, and further decreases to 1.30% with MPC suppression, demonstrating that output current quality is also improved. For dynamic suppression performance, in (h) and (i), PI control enabled the ZSCC to stabilize at 0.608025 s, with a settling time of 0.000025 s. Its RMS value was maintained around 0.08 A. With MPC control, the settling time was 0.00009 s while the RMS value stabilized around 0.05 A. No overshoot is observed in either control algorithm; the ZSCC is rapidly reduced to within the permissible range. Thus, the proposed suppression method demonstrates favorable dynamic performance. In summary, the ZSCC suppression method based on MPC and the improved 3D-SVPWM offers a wide suppression range and exhibits good suppression capability under different operating conditions.

Furthermore, to further validate the effectiveness of the proposed method for suppressing ZSCC, hardware-in-the-loop (HIL) simulations were implemented with the Modeling Tech MT 6020 real-time simulator under Matlab. The tests examined scenarios with different filter inductances in the two inverters, comparing the ZSCC waveforms under PI control and under the proposed model predictive control strategy. Results from a simulation with a 2 × 10⁻⁵ s step size are provided in Figure 12, where (a) shows the HIL simulation setup, and the red dashed lines in (b)–(e) denote reference lines that can be ignored. The figure indicates that without suppression, the ZSCC varies between −13 A and 10 A. Application of PI control narrows this range to −2.25 A to 2.75 A. In contrast, the MPC suppression restricts the current to a range of −1.1 A to 1 A. This confirms that the 3D-SVPWM method incorporating MPC offers more effective suppression of the ZSCC.

6. Conclusions

This paper addresses the ZSCC in 3P4L parallel inverters by proposing a suppression strategy based on MPC and an improved 3D-SVPWM modulation scheme. A regulatory factor k is introduced into the 3D-SVPWM modulation strategy in the abc coordinate system to flexibly adjust the zero-sequence duty cycle difference, thereby eliminating the zero-sequence voltage difference. Furthermore, a closed-loop feedback of the ZSCC is incorporated to establish a ZSCC suppression model for the parallel inverter system. The MPC controller generates the regulatory factor, which is integrated into the modulation strategy of the second inverter, enabling effective suppression of the ZSCC. Relevant results are validated through Matlab and hardware-in-the-loop (HIL) simulations.

The improved 3D-SVPWM modulation strategy not only avoids complex coordinate transformations and matrix operations—thereby significantly reducing the computational burden and facilitating engineering implementation—but also, through the online solution of the regulatory factor via MPC, fully utilizes its rolling optimization mechanism to continuously correct prediction deviations caused by disturbances. This effectively suppresses the system’s ZSCC, further enhancing the flexibility and stability of the overall suppression strategy. This method is therefore well-suited for addressing circulating current issues in parallel 3P4L inverters within data centers or renewable energy microgrids.