SymXplorer: Symbolic Analog Topology Exploration of a Tunable Common-Gate Bandpass TIA for Radio-over-Fiber Applications

Abstract

While circuit parameter optimization has matured significantly, the systematic discovery of novel circuit topologies remains a bottleneck in analog design automation. This work presents SymXplorer, an open-source Python framework designed for automated topology exploration through symbolic modeling of analog components. The framework enables a component-agnostic approach to architecture-level synthesis, integrating stability analysis and higher-order filter exploration within a streamlined API. By modeling non-idealities as lumped parameters, the framework accounts for physical constraints directly within the symbolic analysis. To facilitate circuit sizing, SymXplorer incorporates a multi-objective optimization toolbox featuring Bayesian optimization and evolutionary algorithms for simulation-in-the-loop evaluation. Using this framework, we conduct a systematic search for differential Common-Gate (CG) Bandpass Transimpedance Amplifier (TIA) topologies tailored for 5G New Radio (NR) Radio-over-Fiber applications. We propose a novel, orthogonally tunable Bandpass TIA architecture identified by the tool. Implementation in 65 nm CMOS technology demonstrates the efficacy of the framework. Post-layout results exhibit a tunable gain of 30–50 dBΩ, a center frequency of 3.5 GHz, and a tuning range of 500 MHz. The design maintains a power consumption of less than 400 μW and an input-referred noise density of less than 50 pA/$\sqrt{\mathrm{Hz}}$ across the passband. Finally, we discuss how this symbolic framework can be integrated into future agentic EDA workflows to further automate the analog design cycle. SymXplorer is open-sourced to encourage innovation in symbolic-driven analog design automation.

1. Introduction

Increasing data rates in optical and radio-over-fiber (RoF) networks place stringent demands on receiver front-end circuits [1,2]. Transimpedance amplifiers (TIAs) form the critical interface between current-domain photodiodes and subsequent voltage-mode processing, and must therefore provide high gain, low noise, and efficient use of area and power [3,4]. Contemporary TIA designs emphasize broadband operation and gain programmability to accommodate varying signal conditions, as demonstrated by regulated-cascode and multi-stage variable-gain architectures targeting multi-GHz bandwidths [5]. Another key application for optical circuits is microwave-photonics, which involves the integration of photonic components into microwave architectures [6,7,8]. In RoF small-cell receivers, however, purely wideband transimpedance responses are often suboptimal, since front-end selectivity is required to suppress out-of-band interference before subsequent amplification and mixing stages [9]. This motivates integrating frequency-selective behavior directly at the transimpedance interface, particularly in architectures where receiver channelization is performed at, or close to, the photodiode interface [10].

Transimpedance bandpass filters address this requirement by combining current-to-voltage conversion and band-pass filtering within a single transfer function. Active transimpedance band-pass formulations support a wide range of Q values through biquadratic synthesis [11], while MOS-C and MOS-only realizations offer compact, IC-compatible implementations where tunability is achieved through transconductance control and integrated capacitors [12]. These prior formulations serve as useful benchmarks; however, many reported tunable band-pass TIA implementations exhibit limited orthogonality between tuning parameters. In particular, adjusting the center frequency often results in concurrent variations in transimpedance gain and bandwidth. In addition, several reported designs rely on relatively high power consumption, often in the range of 5–30 mW, which is undesirable for dense RoF small-cell deployments [13]. These observations motivate a symbolic synthesis flow that captures the coupling between center frequency, gain, and Q-factor while supporting power-efficient, post-layout verified designs. This work therefore investigates the symbolic synthesis and optimization of a tunable transimpedance band-pass filter for 5G RoF small-cell front-end applications.

The demand for area-efficient, low-power, and tunable filter topologies has driven the adoption of symbolic exploration as a rigorous methodology for circuit synthesis. Elamien et al. utilized this approach to systematically investigate minimal-transistor architectures, leading to the development of novel first-order [14] and second-order all-pass filters [15,16], some of which were successfully fabricated and validated in 65 nm CMOS. Furthermore, symbolic techniques have proven effective in synthesizing more complex structures such as quadrature-phase oscillators [17]. A key advantage of symbolic exploration is that it yields closed-form expressions that enable rapid topology pruning, parametric sensitivity analysis, and explainable trade-off reasoning prior to computationally expensive simulation campaigns.

Recent advancements in Electronic Design Automation (EDA) have increasingly combined machine learning (ML) with circuit abstractions to accelerate early-stage design exploration [18]. For example, frameworks based on Graph Neural Networks and Variational Autoencoders can learn structural priors and generate candidate topologies that are subsequently mapped to transistor-level implementations [19]. However, SPICE simulations remain computationally expensive, and scalable exploration therefore benefits from symbolic analysis during the earliest stages of topology selection and sizing. While symbolic solvers have been utilized in research, they are frequently constrained by proprietary licenses or limited to educational contexts [20]. The lack of interoperable open-source tooling often forces researchers to implement custom data structures, expression handling, and validation logic, reducing code reusability and complicating integration with modern optimization and ML toolchains. Moreover, quantitative comparison between symbolic expressions remains challenging.

To address these limitations, Figure 1 summarizes the workflow of SymXplorer, an open-source framework for symbolic topology exploration and circuit sizing with SPICE-consistent validation. The main contributions of this work are threefold: (i) a modular symbolic exploration engine for systematically enumerating and analyzing candidate topologies, (ii) an integrated sizing toolbox that supports optimization-driven tuning of design variables, and (iii) a unified characterization flow that aligns symbolic transfer functions with transistor-level and post-layout SPICE verification. SymXplorer is designed to be simulator-agnostic and optimization-agnostic, enabling integration with standard SPICE engines and a wide range of optimization strategies [21,22] while remaining usable out of the box. This modularity also positions SymXplorer as a practical backend for emerging agent-based EDA workflows, where symbolic representations provide an efficient interface between reasoning agents, learning-based optimizers, and transistor-level verification.

The remainder of this paper is organized as follows: Section 2 details the algorithmic architecture of SymXplorer, focusing on the symbolic exploration logic and the integrated circuit sizing toolbox. Section 3 presents a case study of a tunable band-pass TIA implemented in 65 nm CMOS, including post-layout results. Section 4 explains the effects of physical non-idealities through symbolic analysis, discusses methodologies for synthesizing transistor-level implementations from symbolic results, and outlines a roadmap for integrating agentic AI into autonomous EDA workflows. Finally, the paper concludes with a summary of key findings and future research directions.

2. Methods

This section details the operational logic and functional architecture of SymXplorer. The framework comprises two core components: Symbolic Exploration and Circuit Sizing Assistant. Symbolic computations are performed using the SymPy Python library [23]. The circuit sizing toolbox facilitates the validation of selected topologies and provides a means to visualize performance boundaries.

2.1. Related Work

Various methodologies have been proposed to streamline analog design exploration. Recker et al. [24] introduced an early web-based tool for exploring design tradeoffs and analyzing the impact of device mismatch in ICs. To address the computational complexity of symbolic expressions in larger circuits, Shi [25] developed a Graph-Pair Decision Diagram approach, providing an efficient data structure for topological symbolic circuit analysis. Building upon these symbolic foundations, Xie et al. [26] proposed the idea that most small-signal parameters can be achieved from $g_m/I_D$ lookup tables, formulating a method for the systematic exploration of multi-stage op-amps through symbolic modeling and initial $g_m/I_D$ sampling. Additionally, Abel et al. developed a hierarchical performance library to support structured op-amp design [27].

The comparative overview in

Table 1. Comparison of symbolic circuit analysis and design tools.

Tool	Netlist	Freq.	Time	Syst.	Opt.	Perf.	Sim.	GUI	Open
	Input	An.	An.	Expl.	Supp.	Vis.	Intf.		Src.
This work	✓	✓	✗	✓	✓	✓	✓	✗	Yes
Lcapy [20]	✓	✓	✓	✗	✗	✗	✗	✓	Yes
SLiCAP [28]	✓	✓	✓	✗	✗	✗	✓	✗	Yes
CircuitNAV [29]	✓	✓	✗	✗	✗	✗	✗	✓	No
SCAM [30]	✓	✓	✗	✗	✗	✗	✗	✗	No

Abbreviations: Netlist: SPICE Netlist Support; Freq. An.: Frequency Analysis; Time An.: Time-domain Analysis; Syst. Expl.: Systematic Exploration; Opt. Supp.: Circuit Optimisation Support; Perf. Vis.: Performance Boundary Visualisation; Sim. Intf.: SPICE Simulator Interface.

illustrates that most symbolic analysis tools focus on examining a fixed, user-defined netlist. For example, Lcapy and SLiCAP accept SPICE-like netlists and provide DC, AC and transient analysis, but they neither enumerate circuit topologies nor offer built-in design optimization. CircuitNAV is an online service that generates algebraic expressions for node voltages and branch currents from a submitted netlist; it lacks time-domain analysis, optimization support and open-source availability. SCAM uses MATLAB to symbolically solve modified nodal equations from a netlist, but it remains dependent on a proprietary environment. In contrast, SymXplorer combines symbolic analysis with a systematic topology exploration engine and a multi-objective optimization toolbox based on Bayesian and evolutionary algorithms. The framework prunes sub-optimal topologies, visualizes performance boundaries and interfaces directly with open-source SPICE simulators. These capabilities enable designers not only to analyze but also to automatically generate and fine-tune circuit architectures, giving SymXplorer a more comprehensive workflow than existing symbolic design tools.

2.2. SymXplorer Workflow

The architecture and functional summary of SymXplorer are shown in Figure 1. The tool is implemented as a collection of Python classes designed for use within Jupyter Notebooks to ensure scalability and ease of adoption. A dedicated module handles report logging and checkpointing for experimental tracking to manage the large datasets generated during symbolic analysis and optimization. The input to the symbolic exploration tool is a circuit blueprint, as illustrated in Figure 2, along with a set of constraints on the impedance blocks, the target transfer function, and the desired filter type. The tool processes these inputs to generate a database where RLC-equivalent impedance combinations serve as keys, and the corresponding transfer functions and filter parameters are stored as values.

SymXplorer supports the transition from theoretical circuit analysis to high-fidelity design. While designers typically use analytical intuition to determine initial component sizes, the “Sizing Assist” toolbox automates this by utilizing the transfer functions and filter parameters stored during the “Symbolic Exploration” phase. This allows for the pruning of suboptimal topologies and the visualization of performance boundaries before moving to SPICE-level verification. As shown in Figure 1, the framework supports open-source simulators through the Spicelib library [31], while commercial simulators require the definition of a custom interface class.

2.3. Symbolic Exploration

The symbolic exploration engine automates the discovery of optimal circuit topologies by evaluating mathematical permutations of impedance blocks within a defined circuit template. By abstracting active and passive components into a nodal analysis, the algorithm derives exact transfer functions. The program algorithm details are explained in depth in [32]. The following are the main steps in the algorithm, where a differential common-gate circuit is used for illustration.

2.3.1. Defining the Circuit Abstraction

The differential common-gate circuit blueprint illustrated in Figure 2 serves as the primary input for the symbolic exploration engine. Within this framework, the topology is abstracted into a nodal network where active devices are characterized by their n-port network equivalent matrices. Each impedance block in the blueprint can be constrained to various series or parallel combinations of resistive, capacitive, and inductive elements. For instance, a MOSFET can be represented by its transmission matrix at varying levels of fidelity, as shown in Equation (1):

$$\left[T\right]=\left[\begin{array}{cc}0& -{\displaystyle \frac{1}{g_m}}\\ 0& 0\end{array}\right]$$

(1a)

$$\left[T\right]=\left[\begin{array}{cc}-{\displaystyle \frac{1}{g_m{r}_o}}& -{\displaystyle \frac{1}{g_m}}\\ 0& 0\end{array}\right]$$

(1b)

$$\left[T\right]=\left[\begin{array}{cc}{\displaystyle \frac{(1/r_o)+s{C}_{gd}}{s{C}_{gd}-g_m}}& {\displaystyle \frac{1}{s{C}_{gd}-g_m}}\\ {\displaystyle \frac{(C_{gd}{C}_{gs}{r}_{o}s+C_{gd}{g}_m{r}_o+C_{gs}+C_{gd})s}{s{C}_{gd}-g_m}}& {\displaystyle \frac{(C_{gs}+C_{gd})s}{s{C}_{gd}-g_m}}\end{array}\right].$$

(1c)

This multi-level modeling approach ensures that high-frequency parasitics, such as $C_{gs}$ and $C_{gd}$, and finite output resistance $r_o$ are incorporated into the symbolic derivation, which is essential for accuracy in the GHz frequency range. Similarly, discrete-component circuits can be modeled using their two-port network equivalents, such as a gain-bandwidth-limited model for an operational amplifier. Once the impedance blocks are assigned and the topology is defined, the symbolic derivation process remains agnostic to whether the implementation utilizes integrated circuits or discrete components.

2.3.2. Setting the Exploration Target

The exploration target is set by specifying the required transfer function characteristics and probing points within the nodal network. In this study, the symbolic engine is configured to extract the general transimpedance transfer function, $Z_{TIA}\left(s\right)=V_{out,diff}\left(s\right)/I_{in,diff}\left(s\right)$, by solving the nodal equations in terms of the variable impedance blocks ($Z_1,Z_2,\dots ,Z_L$).

Table 2. Symbolic transfer functions and the number of identified bandpass topologies (#) for various impedance block combinations.

Set	$\mathit{H}\left(\mathit{s}\right)$	#	Set	$\mathit{H}\left(\mathit{s}\right)$	#	Set	$\mathit{H}\left(\mathit{s}\right)$	#
$Z_1{Z}_2$	$Z_1{Z}_2{g}_m+Z_1$	1	$Z_4{Z}_5$	${\displaystyle \frac{Z_4{Z}_5{g}_m-Z_4}{2Z_4{g}_m+2Z_5{g}_m+2}}$	2	$Z_1{Z}_5{Z}_L$	${\displaystyle \frac{Z_1{Z}_5{Z}_L{g}_m-Z_1{Z}_L}{Z_1{Z}_5{g}_m+2Z_1{Z}_L{g}_m+Z_1+Z_5+Z_L}}$	6
$Z_1{Z}_3$	${\displaystyle \frac{Z_1{Z}_3{g}_m}{Z_1{g}_m+1}}$	4	$Z_4{Z}_L$	${\displaystyle \frac{Z_4{Z}_L{g}_m}{Z_4{g}_m+2Z_L{g}_m}}$	13	$Z_2{Z}_3{Z}_4$	${\displaystyle \frac{Z_2{Z}_3{Z}_4{g}_m+Z_3{Z}_4}{2Z_2{Z}_3{g}_m+Z_2{Z}_4{g}_m+2Z_3+Z_4}}$	13
$Z_1{Z}_4$	${\displaystyle \frac{Z_1{Z}_4{g}_m}{2Z_1{g}_m+2}}$	4	$Z_5{Z}_L$	${\displaystyle \frac{Z_5{Z}_L{g}_m-Z_L}{Z_5{g}_m+2Z_L{g}_m+1}}$	2	$Z_2{Z}_3{Z}_5$	${\displaystyle \frac{Z_2{Z}_3{Z}_5{g}_m-Z_2{Z}_3+Z_3{Z}_5}{2Z_2{Z}_3{g}_m+Z_2{Z}_5{g}_m+Z_2+4Z_3+Z_5}}$	2
$Z_1{Z}_5$	${\displaystyle \frac{Z_1{Z}_5{g}_m-Z_1}{2Z_1{g}_m+1}}$	2	$Z_1{Z}_2{Z}_3$	${\displaystyle \frac{Z_1{Z}_2{Z}_3{g}_m+Z_1{Z}_3}{Z_1{Z}_2{g}_m+Z_1+Z_2+Z_3}}$	6	$Z_2{Z}_3{Z}_L$	${\displaystyle \frac{Z_2{Z}_3{Z}_L{g}_m+Z_3{Z}_L}{Z_2{Z}_3{g}_m+Z_2{Z}_L{g}_m+Z_3+Z_L}}$	13
$Z_1{Z}_L$	${\displaystyle \frac{Z_1{Z}_L{g}_m}{Z_1{g}_m+1}}$	4	$Z_1{Z}_2{Z}_4$	${\displaystyle \frac{Z_1{Z}_2{Z}_4{g}_m+Z_1{Z}_4}{2Z_1{Z}_2{g}_m+2Z_1+2Z_2+Z_4}}$	6	$Z_2{Z}_4{Z}_5$	${\displaystyle \frac{Z_2{Z}_4{Z}_5{g}_m-Z_2{Z}_4+Z_4{Z}_5}{2Z_2{Z}_4{g}_m+2Z_2{Z}_5{g}_m+2Z_2+4Z_4+2Z_5}}$	2
$Z_2{Z}_3$	${\displaystyle \frac{Z_2{Z}_3{g}_m+Z_3}{Z_2{g}_m+1}}$	8	$Z_1{Z}_2{Z}_5$	${\displaystyle \frac{Z_1{Z}_2{Z}_5{g}_m-Z_1{Z}_2+Z_1{Z}_5}{2Z_1{Z}_2{g}_m+4Z_1+Z_2+Z_5}}$	2	$Z_2{Z}_4{Z}_L$	${\displaystyle \frac{Z_2{Z}_4{Z}_L{g}_m+Z_4{Z}_L}{Z_2{Z}_4{g}_m+2Z_2{Z}_L{g}_m+Z_4+2Z_L}}$	13
$Z_2{Z}_4$	${\displaystyle \frac{Z_2{Z}_4{g}_m+Z_4}{2Z_2{g}_m+2}}$	8	$Z_1{Z}_2{Z}_L$	${\displaystyle \frac{Z_1{Z}_2{Z}_L{g}_m+Z_1{Z}_L}{Z_1{Z}_2{g}_m+Z_1+Z_2+Z_L}}$	6	$Z_2{Z}_5{Z}_L$	${\displaystyle \frac{Z_2{Z}_5{Z}_L{g}_m-Z_2{Z}_L+Z_5{Z}_L}{Z_2{Z}_5{g}_m+2Z_2{Z}_L{g}_m+Z_2+Z_5+4Z_L}}$	2
$Z_2{Z}_5$	${\displaystyle \frac{Z_2{Z}_5{g}_m-Z_2+Z_5}{2Z_2{g}_m+4}}$	0	$Z_1{Z}_3{Z}_4$	${\displaystyle \frac{Z_1{Z}_3{Z}_4{g}_m}{2Z_1{Z}_3{g}_m+Z_1{Z}_4{g}_m+2Z_3+Z_4}}$	22	$Z_3{Z}_4{Z}_5$	${\displaystyle \frac{Z_3{Z}_4{Z}_5{g}_m-Z_3{Z}_4}{2Z_3{Z}_4{g}_m+2Z_3{Z}_5{g}_m+2Z_3+Z_4{Z}_5{g}_m+Z_4}}$	16
$Z_2{Z}_L$	${\displaystyle \frac{Z_2{Z}_L{g}_m+Z_L}{Z_2{g}_m+1}}$	8	$Z_1{Z}_3{Z}_5$	${\displaystyle \frac{Z_1{Z}_3{Z}_5{g}_m-Z_1{Z}_3}{2Z_1{Z}_3{g}_m+Z_1{Z}_5{g}_m+Z_1+Z_3+Z_5}}$	6	$Z_3{Z}_4{Z}_L$	${\displaystyle \frac{Z_3{Z}_4{Z}_L{g}_m}{Z_3{Z}_4{g}_m+2Z_3{Z}_L{g}_m+Z_4{Z}_L{g}_m}}$	91
$Z_3{Z}_4$	${\displaystyle \frac{Z_3{Z}_4{g}_m}{2Z_3{g}_m+Z_4{g}_m}}$	13	$Z_1{Z}_3{Z}_L$	${\displaystyle \frac{Z_1{Z}_3{Z}_L{g}_m}{Z_1{Z}_3{g}_m+Z_1{Z}_L{g}_m+Z_3+Z_L}}$	22	$Z_3{Z}_5{Z}_L$	${\displaystyle \frac{Z_3{Z}_5{Z}_L{g}_m-Z_3{Z}_L}{Z_3{Z}_5{g}_m+2Z_3{Z}_L{g}_m+Z_3+Z_5{Z}_L{g}_m+Z_L}}$	16
$Z_3{Z}_5$	${\displaystyle \frac{Z_3{Z}_5{g}_m-Z_3}{2Z_3{g}_m+Z_5{g}_m+1}}$	2	$Z_1{Z}_4{Z}_5$	${\displaystyle \frac{Z_1{Z}_4{Z}_5{g}_m-Z_1{Z}_4}{2Z_1{Z}_4{g}_m+2Z_1{Z}_5{g}_m+2Z_1+Z_4+2Z_5}}$	6	$Z_4{Z}_5{Z}_L$	${\displaystyle \frac{Z_4{Z}_5{Z}_L{g}_m-Z_4{Z}_L}{Z_4{Z}_5{g}_m+2Z_4{Z}_L{g}_m+Z_4+2Z_5{Z}_L{g}_m+2Z_L}}$	16
$Z_3{Z}_L$	${\displaystyle \frac{Z_3{Z}_L{g}_m}{Z_3{g}_m+Z_L{g}_m}}$	13	$Z_1{Z}_4{Z}_L$	${\displaystyle \frac{Z_1{Z}_4{Z}_L{g}_m}{Z_1{Z}_4{g}_m+2Z_1{Z}_L{g}_m+Z_4+2Z_L}}$	22

presents the computed transfer functions for various block combinations, incorporating the transconductance ($g_m$) of the transistors. To maintain manageable topological complexity, the exploration is limited to combinations of two and three impedance elements. Any impedance blocks excluded from a specific set are treated as open circuits during the symbolic derivation.

2.3.3. Classifying the Transfer Functions

The combinatorial design space is explored by populating the variable impedance blocks with permutations of resistive, inductive, and capacitive networks. To focus the search on physically realizable and functional circuits, users can apply constraints to specific blocks. For instance, $Z_2$ may be restricted to resistive or capacitive networks to ensure valid DC biasing paths.

Table 3. Permissible Impedance Combinations for Valid Transistor Biasing Based on Tool Configuration. (+: series, ‖: parallel).

Component	Permissible Network Configurations
$Z_1,Z_2$	$R_i,C_i,(R_i\Vert C_i),(R_i+C_i),(L_i+C_i)$
$Z_{3,4,5}$	$R_i,C_i,L_i,(R_i\Vert C_i),(R_i+C_i),(L_i+C_i),(L_i\Vert C_i)$
$Z_L$	$R_L,C_L,L_L,(R_L\Vert C_L),(L_L\Vert C_L)$

Note: i corresponds to the respective impedance index (1, 2, 3, 4, 5).

details the permissible network configurations for each block as defined in the tool configuration. The count in Table 2 represents the number of specific component configurations that satisfy the criteria for a second-order bandpass response within each symbolic set. Symbolic extraction of the transfer functions required 30 min of execution time on an Apple M1 with 8 GB of RAM.

Table 4. Samples of Possible Biquad Bandpass Filters Based on Various Impedance Choices. $BW$: Bandwidth, $A_0$: Gain, ${\omega }_0$: Center Frequency.

Z Impedances	Filter	$\mathbf{BW}$	${\mathit{A}}_0$	${\mathit{\omega }}_0$
$L_1\Vert C_1,R_2,R_L$	BPF-1	${\displaystyle \frac{R_2{g}_m+1}{C_1(R_2+R_L)}}$	$R_L$	${\displaystyle \sqrt{\frac{1}{C_1{L}_1}}}$
$L_1,R_L\Vert C_L$	BPF-2	${\displaystyle \frac{C_L{R}_L+L_1{g}_m}{C_L{L}_1{R}_L{g}_m}}$	${\displaystyle \frac{L_1{R}_L{g}_m}{C_L{R}_L+L_1{g}_m}}$	${\displaystyle \sqrt{\frac{1}{C_L{L}_1{R}_L{g}_m}}}$
$L_1,R_5,C_L$	BPF-3	${\displaystyle \frac{C_L{R}_5+2L_1{g}_m}{C_L{L}_1(R_5{g}_m+1)}}$	${\displaystyle \frac{L_1(R_5{g}_m-1)}{C_L{R}_5+2L_1{g}_m}}$	${\displaystyle \sqrt{\frac{1}{C_L{L}_1(R_5{g}_m+1)}}}$
$R_1,R_5,L_L\Vert C_L$	BPF-4	${\displaystyle \frac{2R_1{g}_m+1}{C_L(R_1{R}_5{g}_m+R_1+R_5)}}$	${\displaystyle \frac{R_1(R_5{g}_m-1)}{2R_1{g}_m+1}}$	${\displaystyle \sqrt{\frac{1}{C_L{L}_L}}}$
$R_1,C_3,L_L\Vert C_L$	BPF-5	${\displaystyle \frac{1}{(C_3+C_L)(R_1{g}_m{r}_o+R_1+r_o)}}$	$R_1(g_m{r}_o+1)$	${\displaystyle \sqrt{\frac{1}{L_L(C_3+C_L)}}}$

summarizes some sample bandpass TIA circuits identified by the tool along with their filter parameters. The results always contain LC components; however, as mentioned in Section 4.2, these components can be replaced with equivalent active circuits. The next step is to evaluate the classifications based on tunability and achievable ranges of center frequency, gain, and bandwidth. For instance, BPF-1 and BPF-5 offer gains that are more isolated from other circuit parameters, while BPF-2 and BPF-3 offer center frequencies that are scaled by non-LC components, resulting in smaller LC component sizes for low-frequency applications. Section 2.4.1 studies these performance boundries more rigorously.

2.3.4. Computational Scalability and Pruning Strategies

Symbolic exploration based on impedance-block permutation can, in principle, lead to a combinatorial growth in candidate circuits. In practice, the scalability of the proposed framework is governed less by symbolic capacity and more by computational strategy. While modern symbolic engines can manipulate thousands of symbolic variables, the naïve formulation of circuit equations leads to unnecessary computational overhead.

To address this, the framework adopts several implementation-level optimizations. Large symbolic operations are decomposed into smaller sub-expressions, intermediate results are cached, and expressions are simplified incrementally during evaluation. In particular, symbolic transfer functions are derived at the circuit-blueprint level before substituting detailed device models. This avoids repeatedly solving structurally similar nodal systems and enables reuse of intermediate symbolic results across different impedance-block combinations. As a result, higher-order circuits benefit from previously computed lower-order solutions, substantially reducing per-instance runtime during systematic exploration.

Beyond computational optimizations, the framework incorporates multiple pruning mechanisms to limit unnecessary enumeration. For instance, device modeling fidelity can be progressively refined, allowing initial screening using simplified transconductance-based models before introducing parasitic effects. In addition, early stopping criteria can be applied during transfer-function evaluation. Candidate circuits are discarded if their symbolic expressions exceed a specified order, exhibit unstable pole locations, or violate sign constraints implied by physically meaningful device parameters. Since most symbolic elements (e.g., resistance, capacitance, inductance, and transconductance) have well-defined signs, symbolic sign analysis is used to eliminate infeasible configurations at an early stage.

These strategies collectively mitigate combinatorial growth while preserving generality. Detailed implementation choices and optimization strategies are documented in the open-source repository to ensure reproducibility and extensibility beyond the scope of this manuscript.

2.4. Circuit Sizing

This section details the systematic characterization and sizing of selected topologies within an optimization framework. The sizing procedure is driven by the performance boundaries identified during symbolic exploration, ensuring that component values are optimized to meet specific design targets while maintaining physical realizability.

2.4.1. Characterizing the Performance Boundaries

Let the Design Space be defined as $\mathcal{X}\subseteq {\mathbb{R}}^n$, where a vector $\mathbf{x}\in \mathcal{X}$ represents a set of design variables. Let the Performance Metric Space be $\mathcal{Y}\subseteq {\mathbb{R}}^m$. The system performance is governed by a transformation function $f:\mathcal{X}\to \mathcal{Y}$, which maps design parameters to performance outcomes. The Performance Boundary $\mathcal{P}$ is the image of the design space under f, defined as:

$$\mathcal{P}=\{\mathbf{y}\in \mathcal{Y}\mid \mathbf{y}=f(\mathbf{x}),\forall \mathbf{x}\in \mathcal{X}\}$$

For multi-objective optimization, the analysis focuses on the Pareto Front ${\mathcal{P}}^{*}\subset \mathcal{P}$, which represents the set of non-dominated points where one metric cannot be improved without degrading another. To analyze specific trade-offs, the m-dimensional performance space is projected onto 2D planes. Let ${\mathbf{y}}_{i,j}\in {\mathbb{R}}^2$ be a projection onto the plane defined by metrics $p_i$ and $p_j$. The 2D performance boundary ${\mathcal{P}}_{i,j}$ is defined as:

$${\mathcal{P}}_{i,j}=\{(y_i,y_j)\in {\mathbb{R}}^2\mid \mathbf{y}=f\left(\mathbf{x}\right),\mathbf{x}\in \mathcal{X}\}$$

The design space $\mathcal{X}$ is bounded by the practical constraints of CMOS fabrication. For a design vector $\mathbf{x}={[C,L,R]}^T$, the search space is defined by the following box constraints:

$$\mathcal{X}=\{\mathbf{x}\in {\mathbb{R}}^3\mid 100\mathrm{fF}\le C\le 1\mathrm{nF},100\mathrm{pH}\le L\le 1\mathrm{nH},100\Omega \le R\le 10\mathrm{k}\Omega \}$$

Active device parameters are similarly constrained, with transconductance $g_m$ bounded between $1\mathrm{mS}$ and $100\mathrm{mS}$ and a fixed drain-source resistance $r_o=100\mathrm{k}\Omega$. Characterization of ${\mathcal{P}}_{i,j}$ is performed via a data mining approach using a population of ${10}^4$ design points. The mapping $f\left(\mathbf{x}\right)$ is computed through a symbolic evaluation engine, though the framework remains agnostic to the solver and can support standard SPICE simulators.

The resulting performance boundaries for the BPF-3 and BPF-5 topologies, derived under these constraints, are illustrated in Figure 3. A comparison of the bandwidth versus center frequency plots in Figure 3a and Figure 3b reveals that BPF-3 operates at significantly higher 3 dB bandwidths compared to BPF-5 for the same center frequencies. While both topologies provide gain, BPF-3 enters an attenuation regime ($K_{BP}<1$) within a specific subspace of the design space (Figure 3d), whereas BPF-5 maintains consistently high gain across all center frequencies (Figure 3c). Furthermore, the inherent gain-bandwidth tradeoff is clearly illustrated in Figure 3e,f for BPF-3, where the maximum achievable bandwidth decreases as the gain increases. Therefore, BPF-5 is a promising candidate for a tunable bandpass filter in the GHz range since the performance boundaries are closer to a square.

BPF-5 is well-suited for GHz-range tunable filters as its performance boundaries exhibit greater uniformity across the design space. However, the case study in Section 3 utilizes BPF-1 because it offers similar decoupled metric advantages with lower component complexity, particularly since BPF-1 behavior converges to BPF-5 when accounting for drain-source resistance ($r_o$) and drain-gate capacitances ($C_{gd}$).

2.4.2. Framing the Optimization Problem

The optimization framework in SymXplorer treats circuit sizing as a search for a parameter vector $\mathbf{x}$ that satisfies a set of performance targets $\mathbf{T}$. The problem is first formulated as a Constraint Satisfaction Problem (CSP), where the fitness function $F\left(\mathbf{x}\right)$ is driven primarily by a penalty term $P\left(\mathbf{x}\right)$. For each performance metric $m_i$, a raw penalty $p_i$ is first calculated based on its specific optimization goal:

• EXCEED: $p_i=max(0,T_i-m_i)$, for metrics like gain or bandwidth where a minimum threshold is required.
• MINIMIZE: $p_i=max(0,m_i-T_i)$, for metrics such as power consumption or noise.
• EXACT: $p_i=|m_i-T_i|$, for specific impedance matching or center frequency targets.

To manage the wide dynamic range of circuit metrics (e.g., $\mathrm{dB}\Omega$ vs. GHz), penalties undergo a layered normalization process. First, target-based normalization is applied to produce a unitless relative error ${\widehat{P}}_i$:

$${\widehat{P}}_i={\displaystyle \frac{p_i}{S_i}}$$

where $S_i$ is a normalization constant defined as either the target magnitude $|T_i|$ or a user-specified range. This range allows the designer to decouple the penalty from the absolute scale of the target and instead amplify sensitivity based on the application’s requirements. For example, if a center frequency target is 3.5 GHz, a user might define $S_i$ as 500 MHz if they consider that deviation to be a critical failure. By doing so, the optimizer treats a 500 MHz error with the same “weight” as a 100% error in a different metric, ensuring the search is driven by sensitivity to variation rather than just the numerical magnitude of $T_i$.

Second, a sigmoid-based layer is optionally applied to squash these relative errors into a bounded range $[0,1)$. The final normalized penalty $P_i$ is defined as

$$P_i={\displaystyle \frac{2}{1+e^{-\alpha {\widehat{P}}_i}}}-1$$

In this formulation, $\alpha$ is a scaling coefficient that determines how quickly the penalty saturates. This secondary layer ensures that extreme outliers (i.e., metrics that are far from their targets) do not saturate the loss function or dominate the total fitness score, allowing the optimizer to maintain sensitivity to other metrics that are closer to satisfaction.

In the CSP implementation (represented by the Spice _Constraint_Satisfaction class), the total fitness is defined as the sum of weighted penalties $F\left(\mathbf{x}\right)=-\sum w_i{P}_i\left(m_i\right)$. If all constraints are satisfied, the penalty term becomes zero. To facilitate optimization beyond basic constraint satisfaction, the framework is extended to a single-objective formulation via the Spice_Single_Objective class. In this mode, the aggregate fitness function $F\left(\mathbf{x}\right)$ is defined as a piecewise function of the weighted penalties $P_i$ and rewards $R_i$:

$$F\left(\mathbf{x}\right)=\left\{\begin{array}{cc}\sum w_i{R}_i\left(m_i\right)\hfill & \mathrm{if}\sum P_i\left(m_i\right)\approx 0\hfill \\ -\sum w_i{P}_i\left(m_i\right)\hfill & \mathrm{otherwise}\hfill \end{array}\right.$$

This formulation ensures the optimizer prioritizes meeting all design specifications before attempting to improve metrics beyond the target thresholds (e.g., maximizing gain). The final fitness score is clipped to a defined range to prevent gradient explosion during the search process. More detail regarding reward function engineering and its application in EDA environments is found in [18,33].

2.4.3. Sizing with Symbolic Expressions

Circuit sizing can be executed via two primary symbolic methodologies: direct symbolic inversion or symbolic-driven optimization. In the direct approach, a fully symbolic solver derives closed-form analytical expressions for design variables as functions of target performance metrics. The direct inversion method is used by the SLiCAP software [28]. However, this method frequently encounters feasibility issues, as specific performance targets may yield non-physical solutions, such as negative component values, when the requirements exceed the topology’s capabilities. Therefore, the designers need to first know if a target specification is achievable, and if not, what are the trade-offs needed to achieve similar circuit performance.

Alternatively, symbolic expressions can be utilized as a computationally efficient black-box model within a numerical optimization framework. By formulating the sizing task as a CSP, the optimizer explores the design space using symbolic equations rather than iterative SPICE simulations. If a target cannot be achieved, then the optimizer will find the solution that is closest to the target. This hybrid approach allows for a comprehensive characterization of the performance boundaries associated with a selected topology and technology node to prune sub-optimal candidates.

2.4.4. Sizing with Simulation-in-the-Loop

A SPICE-in-the-loop approach incorporates a numerical solver directly into the optimization flow to leverage foundry models (e.g., BSIM or PSP). Unlike symbolic approximations, numerical simulation captures high-order device physics, including frequency-dependent losses and transistors’ operating points, providing an accurate representation of schematic-level performance. This analysis remains limited to pre-layout characterization. The influence of layout-dependent effects, such as interconnect resistance and coupling capacitance, is only quantified through parasitic extraction following the physical implementation of the design. This stage serves as a secondary verification for candidates identified during the initial symbolic pruning.

3. Case Study: Tunable Bandpass Transimpedance Amplifier

The proposed architecture is designed for a 5G NR small cell RoF front-end. The design targets a minimum transimpedance gain of 40 dBΩ and a 3 dB bandwidth of 200–400 MHz, providing a sufficient margin for accommodating a 100 MHz 5G channel. The TIA should be centered at 3.5 GHz and support sufficient frequency tuning range to compensate for post-fabrication PVT variations. The design is further validated through linearity and noise simulations.

3.1. Topology Selection

The topology shown in Figure 4a was selected due to its minimal component count and the quasi-orthogonal control it offers over gain, bandwidth, and center frequency. This is the BPF-1 in Table 4, where the $R_2$ is replaced by the transistor’s drain resistance, $r_o$. Theoretical derivations based on small-signal analysis yield the following expressions for the circuit performance, where a $1\Omega$ reference resistance is used, and the transimpedance gain is in dBΩ:

$$\mathrm{Gain}=20{log}_{10}\left(R_L\right),f_{\mathrm{c}}={\displaystyle \frac{1}{2\pi \sqrt{LC}}},\mathrm{BW}={\displaystyle \frac{r_o{g}_m+1}{C(r_o+R_L)}}$$

These equations indicate that the transimpedance gain is independent of the center frequency. While the center frequency and bandwidth are both coupled to the capacitance C, they can be adjusted independently through the inductance L and transconductance $g_m$, respectively. Furthermore, the transimpedance gain is a direct function of the load resistance, which is implemented here using a tunable active CMOS resistor to provide the necessary gain tunability.

3.2. Circuit Implementation

The load resistors are implemented using PMOS transistors, and the inductor is realized by an on-chip center-tap spiral inductor from the PDK library. The control voltages $V_{\mathrm{GM}}$, $V_{\mathrm{GAIN}}$, and $V_{\mathrm{CAP}}$ are introduced to control the bandwidth, gain, and center frequency of the TIA, respectively. The circuit schematic is illustrated in Figure 4, with device dimensions summarized in

Table 5. Summary of device dimensions and passive component values for the TIA.

Component	${\mathit{M}}_{1,2}$	${\mathit{M}}_{3,4}$	${\mathit{L}}_{\mathbf{eff}}$	${\mathit{Q}}_{\mathit{L}}$	${\mathit{C}}_{\mathbf{var}}$	${\mathit{C}}_{\mathbf{mim}}$
Parameter	($\mathbf{W}/\mathbf{L}$)	($\mathbf{W}/\mathbf{L}$)	(pH)	(@ 3.5 GHz)	(fF)	(pF)
Value	$3\mathsf{\mu }/120\mathrm{n}$	$9\mathsf{\mu }/120\mathrm{n}$	700	26.5	770/1300 †	2.00

^† Varactor range for $V_{\mathrm{CAP}}$ from 0 V to 1 V.

. To establish the 3.2 GHz to 3.6 GHz center frequency range, a high-Q Metal-Insulator-Metal (MiM) capacitor ($C_L$ in Figure 4b) provides the primary capacitance, while an integrated varactor provides precise tunability.

Figure 5 shows the circuit layout used for post-layout simulations, which is $0.192{\mathrm{mm}}^2$ in area. The layout is extremely sensitive to parasitic resistances at the source of $M_{1,2}$ as explained in Section 4.1; therefore, high-level metals are prioritized for routing at this net due to their lower sheet resistance.

3.3. Simulation Results

The following subsections analyze the AC response, input-referred noise, sensitivity to process variations, and circuit linearity. The static DC power consumption of the circuit is <400 μW. Section 3.3.1 and Section 3.3.2 demonstrate that the TIA can be orthogonally tuned to a target center frequency and transimpedance while maintaining a relatively constant bandwidth. To achieve the design specification of a 300 to 400 MHz bandwidth, the $V_{\mathrm{GM}}$ control voltage is held constant at 500 mV, though it remains available as a tuning knob. AC simulations are conducted from 10 MHz to 50 GHz to characterize the stopband rejection and wideband performance. Finally, Section 4.1 provides an in-depth analysis of the observed non-idealities and their underlying physical causes, explained by symbolic analysis.

3.3.1. Tunability: Orthogonal Control of Gain via $V_{\mathrm{GAIN}}$

Figure 6a illustrates the differential transimpedance gain of the TIA across three different control voltages. As $V_{\mathrm{GAIN}}$ increases from 0 V to 0.45 V, the effective load resistance $R_L$ increases, which results in a tunable peak gain ranging from 37.1 dB to 52.5 dB in the post-layout simulations. These results, summarized in

Table 6. Gain Tunability Results. The differential $Z_{out}$ reported in Figure 10d is equal to $2R_L$.

${\mathit{V}}_{\mathbf{GAIN}}$ (V)	$2{\mathit{R}}_{\mathit{L}}$ ($\mathbf{\Omega }$)	Theory (dB)	Post-Layout (dB)
0.0	210	40.4	37.1
0.35	496	47.9	44.5
0.45	1455	57.2	52.5

, show that the passband gain closely follows the theoretical trends calculated from the differential output impedance in Figure 10d. At low frequencies, the stopband rejection is limited to a finite level rather than following the ideal theoretical roll-off. This behavior is caused by the finite quality factor of the on-chip inductors and the routing impedance. Furthermore, the post-layout response (solid lines) deviates slightly from the pre-layout results (dashed lines). The plot reveals a parasitic peaking effect near 10 GHz. This high-frequency shoulder is attributed to layout-dependent parasitic capacitances, though it remains well outside the intended 3 dB passband.

Figure 6b illustrates the input-referred noise (IRN) spectral density of the TIA for various $V_{\mathrm{GAIN}}$ settings. The spectral response exhibits a distinct noise notch centered at 3.5 GHz, which aligns precisely with the transimpedance gain passband. Within this region, the IRN remains below 50 pA/$\sqrt{\mathrm{Hz}}$ across all settings and decreases further as the gain is increased via $V_{\mathrm{GAIN}}$. Specifically, as shown in the inset, the minimum IRN drops from approximately 45 pA/$\sqrt{\mathrm{Hz}}$ at 0 V to nearly 25 pA/$\sqrt{\mathrm{Hz}}$ at 450 mV. This performance is a direct result of the higher transimpedance gain suppressing the noise contributions from internal stages. The steep increase in noise at frequencies away from resonance is characteristic of the LC-tuned architecture, where the noise shaping effectively follows the inverse of the transimpedance gain profile.

Figure 7 provides a comprehensive summary of the performance trade-offs as $V_{\mathrm{GAIN}}$ varies. The transimpedance gain and minimum input-referred noise follow consistent, opposing trends, with post-layout results tracking the schematic predictions closely across the entire tuning range. Moreover, the results highlight the relative stability of the 3 dB bandwidth and the center frequency. While both metrics remain largely independent of the gain setting, a systematic shift is visible due to layout parasitics. Specifically, the post-layout bandwidth is higher than the schematic value by roughly 20 MHz, whereas the center frequency exhibits a downward shift of approximately 60 MHz.

3.3.2. Tunability: Control of Center Frequency via $V_{\mathrm{CAP}}$

Figure 8 illustrates the tuning range of the center frequency ($f_{\mathrm{center}}$) as the control voltage $V_{\mathrm{CAP}}$ varies from 0 V to 700 mV. $V_{\mathrm{GAIN}}$ is maintained at 400 mV to ensure a high transimpedance gain and a low IRN. By adjusting the varactor capacitance through $V_{\mathrm{CAP}}$, the TIA resonance frequency shifts downward from 3.5 GHz to approximately 3.25 GHz. As shown in the frequency response, this tuning process is accompanied by a moderate reduction in the peak transimpedance gain, which falls from 47.5 dB to 45 dB. This observed gain degradation is discussed in detail in Section 4.1. To mitigate this variation, $V_{\mathrm{GAIN}}$ can be adjusted concurrently to maintain a constant output level. For instance, the dashed line in Figure 8 demonstrates that increasing $V_{\mathrm{GAIN}}$ to 430 mV successfully compensates for the gain drop at $V_{\mathrm{CAP}}=700$ mV, restoring the transimpedance peak to its original magnitude without affecting the shifted center frequency.

Figure 9 summarizes the trends in circuit performance metrics across the $V_{\mathrm{CAP}}$ sweep. The $V_{\mathrm{GM}}$ voltage must be adjusted to maintain the bandwidth at a fixed value.

3.3.3. Input & Output Impedance

Figure 10 presents the input matching and impedance characteristics of the TIA. The input reflection coefficient ($S_{11}$) is evaluated for single-ended characteristic impedances ($Z_0$) of 50 $\Omega$ and 75 $\Omega$, corresponding to differential characteristic impedances ($Z_{0,diff}$) of 100 $\Omega$ and 150 $\Omega$, respectively. As shown in Figure 10a,b, the TIA achieves excellent matching with $S_{11}$ remaining well below $-10$ dB across the desired band, with the 150 $\Omega$ differential termination providing a notably wider bandwidth. However, the output ports would require secondary matching networks if the signals are to propagate through subsequent transmission lines. The output resistance is intentionally variable to facilitate gain tuning, which would otherwise result in significant impedance mismatches at the output interface.

Figure 10. The input reflection coefficient and output impedance for $V_{\mathrm{GAIN}}=400$ mV, $V_{\mathrm{GM}}=500$ mV, and $V_{\mathrm{CAP}}=0$ V.

Figure 10. The input reflection coefficient and output impedance for $V_{\mathrm{GAIN}}=400$ mV, $V_{\mathrm{GM}}=500$ mV, and $V_{\mathrm{CAP}}=0$ V.

3.3.4. Linearity

The linearity of the TIA is evaluated through Total Harmonic Distortion (THD), the 1 dB compression point ($P_{1 \mathrm{dB}}$), and the third-order intercept point (IIP3). As shown in Figure 11a, the THD remains below the 1% threshold for differential input currents up to 600 μA across all gain settings. The dashed line represents the pre-layout results. The $V_{\mathrm{GAIN}}=450$ mV case represents the worst-case linearity due to the larger internal voltage swings associated with higher transimpedance. Figure 11b confirms that the transimpedance gain remains flat for low input levels before undergoing compression at higher current densities. For the power-based analysis in Figure 11c,d, the input power $P_{\mathrm{in}}$ was determined by applying a $1\Omega$ reference resistance to the differential input current. At the highest gain setting ($V_{\mathrm{GAIN}}=450$ mV), the TIA achieves an input-referred 1 dB compression point ($P_{1 \mathrm{dB}}$) of approximately $-21.5$ dBm and an IIP3 of $-19.5$ dBm.

In the context of the reported linearity metrics, it is important to relate the measured $P_{1 \mathrm{dB}}$ and IIP3 values to the intended operating conditions of the TIA. The proposed circuit is designed to operate in the weak-signal regime of RoF receivers, i.e., immediately following photodetection and close to the receiver sensitivity limit. Under typical RoF receiver conditions, the expected electrical input signal power lies in the range of $-60$ to $-40$ dBm. At the highest gain setting ($V_{\mathrm{GAIN}}=450$ mV), the simulated IIP3 of $-19.5$ dBm (Figure 11d) implies, using the standard two-tone approximation $\mathrm{IM}3\left(\mathrm{dBc}\right)\approx 2(\mathrm{IIP}3-P_{\mathrm{in},\mathrm{tone}})$, an intermodulation distortion level of approximately 41 dBc for a $-40$ dBm input tone and exceeding 60 dBc for input tones below $-50$ dBm. These results indicate that third-order distortion remains well suppressed over the targeted weak-signal operating range, consistent with the low THD and compression behavior observed in Figure 11a–c. For higher input power levels outside this regime, the TIA is intended to operate at reduced gain settings, thereby preserving linearity while extending the usable dynamic range.

3.3.5. Monte Carlo Simulations

To assess the impact of process variations, 200 Monte Carlo iterations were performed for $V_{\mathrm{GAIN}}=400$ mV and $V_{\mathrm{CAP}}=0$ V. The results, illustrated in Figure 12, demonstrate that the performance metrics remain stable and well-centered. Specifically, the center frequency ($f_{\mathrm{center}}$) shows a mean value of 3490 MHz with a standard deviation of 62.3 MHz, as shown in Figure 12d. This variation range is significantly smaller than the 250 MHz tuning range provided by $V_{\mathrm{CAP}}$, confirming that the tuning mechanism can effectively compensate for process-induced shifts to maintain the 3.5 GHz target.

4. Discussion

This section analyzes the simulation results and the impact of component non-idealities on circuit performance. It also explores future research directions for integrating these findings into automated EDA workflows to improve design efficiency.

4.1. Analysis: Modeling the Effects of Non-Idealities

The $f_{\mathrm{center}}$ tunability results suggest that the transimpedance gain is a function of the center frequency. This coupling is attributed to the non-idealities of the passive components. The parasitic resistances of both the inductor and capacitor contribute to an overall lumped parallel resistance $R_p$. Figure 13b illustrates the transformation of these losses into the equivalent parallel resistance $R_p$. Figure 13a shows the updated TIA schematic with these parasitics. A symbolic analysis of this circuit reveals a bandpass response characterized by the following expressions:

$$\mathrm{Gain}={\displaystyle \frac{R_p{R}_L(g_m{r}_o+1)}{R_p{g}_m{r}_o+R_p+R_L+r_o}},f_{\mathrm{c}}={\displaystyle \frac{1}{2\pi \sqrt{C{L}_1}}},\mathrm{BW}={\displaystyle \frac{R_p{g}_m{r}_o+R_p+R_L+r_o}{C{R}_p(R_L+r_o)}}$$

To evaluate the impact of these non-idealities, we consider the limits as the components approach the ideal case ($R_p\to \infty$):

$$\underset{R_p\to \infty }{lim}\left(\mathrm{Gain}\right)=R_L,\underset{R_p\to \infty }{lim}\left(\mathrm{BW}\right)={\displaystyle \frac{g_m{r}_o+1}{C(R_L+r_o)}}$$

These limits align with the theoretical maximum gain and minimum bandwidth for the studied topology. In practical scenarios where $R_p$ is finite, the gain is reduced while the bandwidth increases. This is most evident when decomposing the bandwidth expression:

$$\mathrm{BW}={\displaystyle \frac{g_m{r}_o+1}{C(R_L+r_o)}}+{\displaystyle \frac{1}{C{R}_p}}$$

The presence of $R_p$ introduces an additive term, ${\displaystyle \frac{1}{C{R}_p}}$, which broadens the bandwidth at the direct expense of peak transimpedance gain. Furthermore, since the inductor quality factor (Q) is frequency-dependent and optimized for a specific narrow band, operating the TIA at a frequency considerably different from the inductor’s design point can yield significantly lower Q values. This reduces $R_p$, leading to a shallower gain and an even wider, less selective passband. While $R_p$ accounts for these AC performance trade-offs, the finite stopband gain at low frequencies is specifically caused by the series resistance of the inductor, $R_s$. Under DC conditions, the ideal inductor behaves as a short circuit to ground at the source of the common-gate NMOS pair. However, the presence of $R_s$ prevents a perfect short, resulting in a non-zero voltage at the source and causing a finite, non-ideal low-frequency gain.

4.2. Analysis: Topology Exploration & Synthesis

A promising path for topology discovery involves decomposing a circuit into RLC networks with dependent sources, followed by synthesis back into a transistor-level implementation. Beyond modeling fundamental gain-bandwidth limitations, two-port transistor characteristics, or passive device parasitics, this methodology has proven successful in the discovery of active inductors.

The simulation results underscore the necessity of high-Q inductors to maintain the selectivity of the bandpass TIA. Consequently, an alternative implementation of the selected topology involves leveraging active inductors. Gyrator-C-based active inductors can achieve quality factors exceeding 100 and self-resonant frequencies (SRF) beyond tens of GHz while significantly reducing on-chip area [34]. Recent works demonstrate the viability of these components for mmWave and RF applications, including single-ended implementations in 180 nm CMOS [35] and 65 nm CMOS [36]. Notably, Schmitz et al. propose a differential Gyrator-C active inductor with an 18 GHz SRF in 65 nm CMOS [37]. However, it is important to note that active inductors have higher power consumption and require precise frequency tuning to remain effective for the target application [38].

4.3. Next Steps: Circuit Sizing Strategies

The TIA case study demonstrated that layout parasitics significantly affect performance, requiring schematic-level co-optimization. Future development of SymXplorer will focus on tools that characterize performance boundaries and sensitivity to layout-induced non-idealities, rather than identifying single-point solutions.

Achieving this requires integrating automatic layout generation into the sizing loops. This can be implemented via the Berkeley Analog Generator (BAG) [39], which has been successfully utilized for layout-in-the-loop optimization by Porrasmaa et al. [40]. Furthermore, BagNet [41] demonstrates that BAG-based flows can be significantly accelerated by deep neural networks to navigate the layout-aware design space. As an alternative to template-based generators, GLayout [42] offers a PDK-agnostic framework where Python-based code automates layout construction. To improve the data efficiency of these sizing loops, Budak et al. proposed a multi-fidelity layout-aware framework that employs Bayesian Neural Networks to approximate circuit performance using fewer training points [43]. Similarly, Huang et al. [44] proposed a nested multi-fidelity modeling approach within a Bayesian optimization framework, which strategically uses low-fidelity schematic data to guide the search and minimize the number of costly high-fidelity post-layout simulations.

To further improve the sizing process, technology-specific data should be integrated into the engine. This includes tracking transistor operating points and employing the $g_m/I_D$ methodology to reduce problem dimensionality and maintain physical feasibility within the target process node. Finally, the optimization suite could incorporate reinforcement learning (RL) agents to complement existing stochastic optimizers; tools like AutoCkt [45] and trust-region RL frameworks [46] have shown that these agents excel at capturing complex parasitic effects and simplify porting designs across technology nodes.

4.4. Next Steps: Workflow Enhancement with Agentic AI

The current implementation of SymXplorer demonstrates the power of symbolic exploration in discovering high-performance topologies. However, the next evolution of this framework lies in the integration of Agentic AI workflows. An agentic framework can act as a “silicon architect,” where a collection of specialized agents supervises the entire design flow, autonomously leveraging a toolset that includes symbolic exploration engines, circuit optimizers, SPICE simulators, and automatic layout generators.

The following enhancements represent a roadmap for adding agentic intelligence into the design loop:

• Intelligent Constraint Synthesis and Topological Expansion: Beyond simple annotation, agents can autonomously parse discovered topologies to identify functional sub-blocks (e.g., current mirrors, differential pairs) and apply constraints for symmetry, $W/L$ ratios, and $g_m/I_D$ consistency. Furthermore, an agentic framework can actively propose topological variations to meet stringent specifications; for instance, swapping passive inductors for various active inductor implementations to save area, or dynamically inserting frequency compensation schemes (e.g., Miller compensation or zero-canceling resistors) to stabilize high-gain stages.
• Knowledge-Driven Initialization: By leveraging a fundamental understanding of circuit theory and previous discovery iterations, the AI can suggest optimized starting point values for the optimizer. Such “warm-starts” have been shown to significantly improve convergence speed and the quality of the final design results [47].
• Multi-Agent Tool Supervision: A multi-agent system can supervise the execution of diverse EDA tools. For instance, a “Manager Agent” coordinates between the symbolic solver and SPICE simulator, while specialized “Analyst Agents” interpret simulation waveforms to suggest topological refinements or specific device-sizing adjustments.
• Resource-Aware Decision Making: A key advantage of an agentic workflow is the strategic invocation of “expensive” computational tasks. The AI evaluates the maturity and performance of a candidate design before committing resources to time-intensive simulations, such as layout generation and parasitic extraction [48].

By shifting these heuristic and administrative tasks to an agentic layer, the designer can move from manual “tweaking” to high-level architectural oversight, significantly reducing the Time-to-Market for complex analog and RF ICs.

5. Conclusions

This paper presents SymXplorer, an open-source Python framework for automated analog circuit topology exploration based on symbolic modeling. The framework enables component-agnostic symbolic analysis and integrates a circuit sizing assistant, providing a systematic link between architecture-level synthesis and transistor-level validation. Its utility is demonstrated through the discovery and implementation of an orthogonally tunable differential common-gate bandpass TIA for 5G RoF applications in 65 nm CMOS technology. Post-layout simulations confirm competitive gain, bandwidth, noise, and power performance. The results show that the impact of layout parasitics and finite inductor quality on gain and stopband roll-off can be systematically explained using the symbolic exploration framework. Ultimately, SymXplorer is intended to enhance research productivity by streamlining complex derivations rather than replacing the designer’s creative role. Finally, directions for future integration with agentic AI-driven EDA workflows are discussed.