Design of a CMOS Self-Bootstrapping Rectifier with Latch-up Protection for Wireless Power Harvesting Systems

Abstract

This study, based on the specifications of implantable medical devices for wireless power transfer, presents a bootstrap-comparator rectifier circuit design characterized by high voltage conversion efficiency, high power conversion efficiency, and improved reliability. The design is implemented using a 0.18 µm process to achieve superior VCE and PCE performance. The input signal is a 2 MHz, 3.3 V sine wave, producing an output voltage of 2.94 V with a maximum operating current of 5 mA. At an output load of $R_L=8\mathrm{k}\Omega$, the maximum voltage conversion efficiency (VCE) reaches 89.02%, while the maximum power conversion efficiency (PCE) is 84.73% at $R_L=500\Omega$. The temperature rise ($\Delta T$) is 0.22–0.45 °C.

1. Introduction

The application of implantable medical devices (IMDs) has advanced significantly over the past two decades, particularly in the areas of nerve and muscle electrostimulation. Notable examples include pacemaker [1], cochlear implants [2,3], retinal prosthesis [4,5] and neural stimulator [6,7], etc. The energy system of an implantable device consists of three modules: a power supply, an energy storage device, and a power regulator. Depending on the application and implantation site, the power requirements and power supply vary. For example, pacemakers require power levels below 100 μW, which is considered ultra-low, and therefore typically use implantable batteries or supercapacitors as energy sources. Currently, the battery and integrated circuit board have been sealed by biocompatible materials to avoid contact with the human body. However, the size and capacity of the battery significantly limit the implantation site, making it unsuitable for applications with high power demands. Additionally, it may increase the risk and cause discomfort for the patient during replacement surgery. Therefore, wireless power transfer technology [8,9,10] offers an alternative for implantable devices by overcoming the drawbacks associated with separate, depleting power sources and providing a viable solution for applications with high power demands.

Wireless power transfer systems are particularly well-suited for applications with low power level, such as cochlear implants, retinal prostheses, and neural stimulators. The power demands for these devices are approximately 0.6–40 mW for cochlear implants, 1–100 mW for retinal prostheses, and 10–200 mW for neural stimulators, respectively. The common methods are inductive coupling [11], capacitive coupling [12] and ultrasonic coupling [13]. Inductive coupling is the most mature wireless power transfer method, approved and validated by the U.S. food and drug administration. ISO 13485 [14] specifies the limit for the Specific Absorption Rate (SAR) in the human body as 1.6 W/kg. The absorption rate of electromagnetic waves in human tissue is directly proportional to frequency; therefore, higher operating frequencies result in greater tissue absorption. The 13.56 MHz frequency band is the standard for medical applications and benefits from a well-established supply chain of related components. However, it is susceptible to impedance changes caused by the surrounding environment, necessitating additional frequency tracking and impedance matching circuits, which increase overall system complexity. In contrast, 2 MHz operates at a mid-to-low frequency. As frequency decreases, the SAR absorption rate also decreases, making it easier to comply with regulations. Regarding conversion efficiency, the switching losses of the power amplifier (PA) and rectifier are lower at 2 MHz, indicating improved efficiency. According to ISO 14708-1 [15], the temperature difference between an implant and the surrounding tissue must not exceed 2 °C. Therefore, from a safety perspective—considering thermal damage caused by power loss—2 MHz offers a more reliable advantage.

The entire wireless power transfer system, as shown in Figure 1, can be divided into two parts: the transmitter outside the body and the receiver implanted inside. The transmitter consists of a signal source, a power amplifier, and a primary coil. The power amplifier supplies sufficient power, which the primary coil uses to generate a time-varying magnetic field. The receiver comprises a secondary coil, a rectifier, and a low-dropout regulator. However, the induced voltage of the secondary coil which need to be converted into DC voltage to the implantable device is still AC voltage. The function of the rectifier is to convert the alternating current into direct current, but the output voltage has large ripples because the AC voltage cannot be eliminated completely. In order to obtain a stable DC voltage to supply the next-stage circuit, a Low-dropout regulator (LDO) can be applied after the rectifier. The rippled power supply is converted into a Smoothing DC current by a low-dropout voltage regulator.

A key metric for evaluating the performance of wireless power transfer (WPT) systems is power transfer efficiency (PAE). The total efficiency (${\eta }_{Total}$) of a wireless power transfer system can be expressed by Equation (1)

$${\eta }_{Total}={\eta }_{PA}\times {\eta }_{Coil}\times {\eta }_{Rectifier}\times {\eta }_{LDO}.$$

(1)

${\eta }_{PA}$ represents the power amplifier (PA) power transfer efficiency (PAE). Compared to linear PA, switching PA exhibit superior PAE performance. Class E PA are preferred IMD systems due to their high PAE and simple structure. ${\eta }_{Coil}$ denotes the efficiency of the inductively coupled coil link, which depends on the transmission distance (coil spacing, d), alignment, and the coil’s quality factor (Q). Before discussing the rectifier efficiency (${\eta }_{Rectifier}$), it is important to note that the low-dropout regulator (LDO) efficiency (${\eta }_{LDO}$) depends on the dropout voltage. P-type LDOs can achieve extremely low dropout voltages and are the preferred choice in IMD systems, offering a simple circuit architecture and high efficiency, similar to class E amplifiers. With well-defined PA and LDO architectures and limited coil placement, the key parameters of the WPT system are largely determined by the rectifier. The power conversion efficiency (PCE) of a rectifier can be expressed by Equation (2), where $P_{out-DC}$ is the DC output power and $P_{in-AC}$ is the received AC power.

$$PCE={\displaystyle \frac{P_{out-DC}}{P_{in-AC}}}\times 100\%$$

(2)

In addition to power conversion efficiency in rectifier circuit design, improving voltage conversion efficiency (VCE) and avoiding the latch-up effect are also critical challenges that must be addressed. Therefore, in this paper, we propose a rectifier that demonstrates enhanced voltage conversion efficiency and power conversion efficiency. Unlike traditional designs that utilize diodes to restrict current direction, our approach employs a cross-coupling configuration to achieve superior voltage conversion efficiency. A four-input comparator is implemented to minimize reverse current during input signal conversion, thereby enhancing overall energy conversion efficiency. Finally, all-NMOS transistors are used as power transistors to prevent the formation of parasitic P-N-P-N structures that can cause latch-up. High charging efficiency is achieved by eliminating the threshold voltage drop of NMOS transistors [16] through a boost circuit; however, simply increasing the voltage introduces safety risks in IMD systems due to potential breakdown issues. Therefore, we propose a rectifier circuit design that ensures both high performance and reliability.

The remainder of the paper is organized as follows: Section 2 introduces a typical rectifier structure and the challenges that must be addressed. Section 3 describes the rectifier circuit proposed in this study. Section 4 presents the simulation results and measurements of the rectifier circuit. Section 5 concludes the paper.

2. Typical Rectifier Circuits

This section introduces the fundamentals of common rectifier circuits and discusses practical considerations.

2.1. Full-Wave Diode Rectifier

The classic full-wave bridge rectifier configuration consists of four diodes. The diodes restrict the direction of the current to facilitate full-wave rectification. In CMOS technology, the diodes are typically replaced by MOSFETs, as illustrated in Figure 2a. The operational principle of this circuit is divided into the positive half-cycle and the negative half-cycle based on the AC signal. During the positive half-cycle, when $\left|V_{ac}\right|$ > ($\left|V_{TP1,2}\right|$ + $V_{TN4,3}$), diodes $M_1$ and $M_4$ are activated, while diodes $M_2$ and $M_3$ are deactivated. At this time, the load capacitor is charged by $V_{DC}$. In contrast, during the negative half-cycle, diodes $M_2$ and $M_3$ are turned on, while diodes $M_1$ and $M_4$ are turned off, and the current flowing through the load capacitor maintains the same direction as in the positive half-cycle. Thus, a full-wave rectifier can be achieved. The advantage of this structure is that the conduction current is allowed to flow in only one direction due to the characteristics of the diode. Because of its forward flow and reverse blocking characteristics, it effectively prevents the generation and consumption of reverse current. However, the threshold voltage of the diode affects the voltage conversion efficiency when it operates in forward bias. VCE is defined as the ability of an AC input peak voltage ($V_{in-Peak}$) to be converted into a DC output voltage ($V_{out-DC}$), as described by Equation (3).

$$VCE={\displaystyle \frac{V_{out-DC}}{V_{in-peak}}}\times 100\%$$

(3)

The full-wave rectifier structure contains two diodes in each half-cycle, resulting in a total threshold voltage of twice the diode’s threshold when activated. The output voltage can be expressed as Equation (4)

$$V_{DC}=\left|V_{ac}\right|-(\left|V_{TP1,2}\right|+V_{TN4,3}).$$

(4)

With the demands of advanced CMOS technology and the need for low power consumption, the impact of threshold voltage on voltage conversion efficiency has also increased. Consequently, the full-wave rectifier is being gradually replaced by alternative structures that enhance voltage conversion efficiency.

2.2. Gate Cross-Coupled Rectifier

Addressing the drawbacks of the above structure, the gate cross-coupled rectifier, which consists of four MOS switches, can effectively improve voltage conversion efficiency, as shown in Figure 2b [17]. Since the MOS switches operate in the triode region, their on-state resistance can be reduced by adjusting the aspect ratio. Additionally, the threshold voltage can be significantly lowered to further enhance voltage conversion efficiency. The circuit operates as follows: during the positive half-cycle, $M_1$ and $M_4$ are turned on, while $M_2$ and $M_3$ are turned off. $M_1$, $M_4$, and the capacitor ($C_L$) form a loop, with the charging current flowing from $V_{DC}$ through the capacitor to ground. During the negative half-cycle, $M_1$ and $M_4$ are turned off, while $M_2$ and $M_3$ are turned on. The charging current maintains the same direction as described above. However, this configuration presents a significant issue: reverse current is generated during the rectification process. This reverse current increases power consumption, thereby reducing power conversion efficiency. The reverse current occurs at the peaks on both sides of the AC signal, specifically when $\left|V_{TN,P}\right|$ < $\left|V_{ac}\right|$ < $V_{DC}$. The switch turns on when the AC signal exceeds the threshold voltage; however, the charging path then becomes a discharging path, producing reverse current. This reverse current further reduces power conversion efficiency when the AC voltage is lower than the DC voltage. The gate cross-coupled rectifier can improve voltage conversion efficiency. However, the MOS switch is less effective at preventing reverse current compared to a diode, resulting in increased power consumption.

2.3. Mixed Cross-Coupled Rectifier

The mixed cross-coupled rectifier is proposed by combining the two rectifier structures described above, as shown in Figure 2c [18]. The upper section of this structure employs MOS diodes to prevent reverse current. Since preventing reverse current requires only a single diode, the lower section can utilize a cross-coupled pair with a smaller threshold voltage. The operation is similar to the two aforementioned structures but requires only a single threshold voltage, thereby improving voltage conversion efficiency. The MOS diode only turns on when ($\left|V_{ac}\right|$− $V_{DC}$ ) > $V_{TP1,2}$, which helps prevent reverse current through the MOS switch caused by the transfer of the AC signal, thereby improving power conversion efficiency. Compared to the previous structure, this design offers good power conversion efficiency and acceptable voltage conversion efficiency, making it more suitable for chip design applications. However, CMOS technology can form parasitic BJTs during layout, leading to latch-up effects that create a short circuit between the power supply and ground. In some cases, the leakage current generated by the short circuit of latch-up effects may damage the circuit.

In CMOS technology, parasitic P-N-P-N structures [19] are formed when the PMOS transistor is in close proximity to the NMOS transistor, as illustrated in Figure 3a. Three PN junctions are created by the PMOS source $p^{+}$, the n-well $n^{+}$, the p-substrate $p^{+}$, and the NMOS source $n^{+}$. This configuration results in an equivalent circuit composed of PNP and NPN transistors, along with the parasitic resistances ($R_{n,p}$) of the n-well and the p-substrate, resembling a silicon-controlled rectifier (SCR). The equivalent circuit is shown in Figure 3b. Under normal conditions, when $V_{Rn}\le 0$ and $V_{Rp}\ge 0$, the base current is very small. The latch-up effect does not occur because both transistors are turned off. However, if one transistor enters the conducting state due to an external voltage, the other transistor is activated by a feedback current. As both transistors turn on, the base current increases further, creating a positive feedback loop. When ${\beta }_{PNP}\times {\beta }_{NPN}\ge 1$, the silicon-controlled rectifier (SCR) circuit remains in the on-state, creating a short circuit between $V_{DC}$ and $Gnd$ that causes the latch-up effect. Since the input voltage is an AC signal, setting $V_{sb}\ne 0$ makes the PMOS diode in the mixed cross-coupled rectifier prone to triggering latch-up.

3. Proposed Boost-Comparator Rectifier

Figure 4 illustrates the bootstrap-comparator rectifier architecture proposed in this study, with the primary power transistors highlighted in red.

This basic structure employs gate cross-coupling, which enables higher VCE and minimal conduction voltage drop. However, as mentioned above, gate cross-coupling results in larger reverse current and lower PCE. To address these issues, this study employs a 4-input comparator circuit to control the operation of the MOS switches, thereby suppressing reverse current and enhancing PCE. Unlike the traditional gate cross-coupled configuration shown in Figure 2b, where the PMOS transistor serves as the charging element and the NMOS transistor acts as the return path, this study proposes an rectifier architecture with all-NMOS power transistors. This approach avoids the formation of parasitic P-N-P-N structures, which can cause latch-up effects and damage the chip. However, using NMOS as the charging element results in poor charging performance, as the output voltage is limited by the threshold voltage ($V_t$). To improve NMOS charging performance, the gate voltage ($V_G$) is boosted through a bootstrap circuit, resulting in an effective gate voltage $V_G^{\prime }=V_G+V_{Boost}$. By applying this higher gate voltage, the limitation imposed by $V_t$ is overcome, thereby enhancing the charging performance.

3.1. Bootstrap Circuit

This paper adopts a bootstrap circuit, as shown in Figure 5 [20]. $M_1$ is a rectifier power transistor.

This circuit primarily boosts the gate voltage ($V_{Boost}$) of $M_1$, freeing the NMOS transistor from the threshold voltage that limits its charging function. Before the output voltage $V_{DC}$ reaches steady state, the low output voltage prevents the boost circuit from operating effectively. At this stage, $M_{P2}$ functions as a precharge diode, substituting for $M_1$. As the output voltage approaches steady state, the precharge diode turns off because the voltage difference between its terminals falls below its threshold voltage. Although this circuit operates only before steady state, a bulk control circuit regulates the bulk voltage of $M_{P2}$ to prevent latch-up caused by the proximity of the PMOS and NMOS transistors. Figure 6a [21] shows the bulk control circuit, which employs a cross-coupling configuration to maintain a high bulk voltage and thereby prevent latch-up.

As the output voltage reaches steady state, the boost circuit resumes normal operation. The operation can be divided into two phases: the charging phase and the boost phase. Figure 6b shows the voltage sequence diagram. $V_{C1}$ and $V_{C2}$ represent the voltages across the rectifier. The input voltage ($V_{in}=V_{C1}-V_{C2}$) is a 2 MHz sine wave signal. When $V_{C1}>V_{C2}$, the charging phase begins. The circuit operation can be divided into two parts. The left charging path, bounded by power transistor $M_1$, comprises transistors $M_{N1}$, $M_{N2}$, $M_{P1}$, and $M_{P3}$. The gate voltage of $M_{P3}$ is $V_{DC}$, and its conduction state depends on its drain-to-source voltage. During the charging phase, $V_{Boost}$ is reset, which turns off $M_{P3}$ and $M_{N2}$. Meanwhile, $M_{P1}$ and $M_{N1}$ conduct, establishing a charging path that charges the capacitor to voltage $V_C$. The right reset path includes transistors $M_{N3}$, $M_{N4}$, and $M_{P4}$. The conduction state of $M_{N3}$ is controlled by the inverter formed by $M_{N4}$, and $M_{P4}$. During the charging phase, $V_{C1}$ is high, turning off $M_{P4}$ and turning on $M_{N3}$ and $M_{N4}$, thereby forming the reset path. This path discharges $V_{Boost}$ and resets $M_1$.

When $V_{C1}<V_{C2}$, during the boost phase, the $V_{Boost}$ voltage is supplied sequentially by the right and left circuits. Initially, $V_{C1}$ is low, causing $M_{N4}$ to turn off while $M_{N3}$ and $M_{P4}$ turn on, allowing the $V_{Boost}$ voltage to rise to $V_{DC}$ via the right path. As the $V_{Boost}$ voltage increases, $M_{N2}$ turns on, and the left path transistors $M_{P1}$ and $M_{N1}$ turn off. $M_{P3}$ turns on because the voltage across its source and drain exceeds $V_{DC}$. At this stage, the $V_{Boost}$ voltage further increases to $V_{Boost}=V_{C2}+V_C$. Equation (5) shows that when $V_C>V_{TN}$, the NMOS transistor, acting as a switch, can make $V_{DC}\cong V_{C2}$. During the boost phase, the conduction states of $M_{P3}$ and $M_{N2}$ are determined by the path on the right. According to technology specifications, this structure is primarily designed to prevent circuit breakdown, which is more likely to occur when the voltage exceeds 10% above the supply voltage. According to Equation (6), $V_{Boost}=V_{C2}+V_{DC}-\left|V_{TP}\right|\cong 2\ast V_{C2}$. $M_{N3}$ and $M_{P3}$, as the primary charge and discharge paths for $V_{Boost}$, are most susceptible to breakdown. Therefore, $V_{DC}$ is used to protect the gate voltages of $M_{N3}$ and $M_{P3}$, while the inverters formed by $M_{N4}$ and $M_{P4}$ ensure the proper source voltage of $M_{N3}$.

$$V_{Boost}-V_{C2}>V_{TN}.$$

(5)

$$V_C=V_{DC}-\left|V_{TP}\right|.$$

(6)

3.2. 4-Input Comparator Circuit

Power conversion efficiency is a critical performance metric in rectifier design, particularly for biomedical applications involving energy harvesting systems. Implantable biomedical devices inherently demand low power consumption, making high power conversion efficiency essential for effective system implementation.

The proposed boost-comparator rectifier employs a gate cross-coupled structure to achieve high voltage conversion efficiency. However, this process is accompanied by reverse current generated during input voltage conversion, which increases power consumption and reduces power conversion efficiency. To address this, this paper employs a 4-input comparator to control the switching of power transistors, thereby achieving current direction control and minimizing the occurrence of reverse current. The circuit consists of two sets of comparator circuits, as shown in Figure 7 [22]. The reference voltages for the two comparators are $V_{DC}$ and GND, respectively. The operating mode is discussed in two parts. First, the input signal to the upper comparator is $V_{C2}$, and the reference voltage is $V_{DC}$. $M_{P1}$ is a PMOS active load that controls the gate voltage of $M_{P2}$. From (7)–(9), we know that the conduction condition for $M_{P2}$ is $V_{C2}<V_{DC}$. When $M_{P2}$ is turned on, $M_{P5}$ is turned off because its gate voltage is high. The control signal for the power transistor switch $M_4$ is $V_{Control}$. Since $M_{P5}$ is turned off, the state of $V_{Control}$ is determined by $M_{N3}$.

$$V_X=V_{C2}-\left|V_{TP}\right|.$$

(7)

$$(V_{DC}-V_X)-\left|V_{TP}\right|>0.$$

(8)

$$V_{C2}<V_{DC}.$$

(9)

The input signal and reference voltage of the lower half comparator are $V_{C1}$ and Gnd respectively. $M_{N1}$ is an NMOS active load that forms a bleeder circuit with $M_{P1}$ and $M_{P3}$. According to (10)–(12), the conduction condition for $M_{N2}$ is $V_{C1}<Gnd$. The state of $M_{N2}$ determines whether $M_{N3}$ is on. Consequently, the conduction states of $M_{P2}$ and $M_{N2}$ control the switching state of $M_4$. Reverse current in the gate cross-coupled rectifier occurs when the input signal is lower than the output signal. To prevent reverse current, $M_4$ should be turned on only when the input voltage exceeds the output voltage.

Table 1. Comparator Operation.

Comparator Operation		MOS Switch ${\mathit{M}}_4$
$V_{C2}>V_{DC}$	$V_{C1}<Gnd$	ON
$V_{C2}<V_{DC}$	$V_{C1}>Gnd$	OFF
$V_{C2}>V_{DC}$	$V_{C1}<Gnd$	OFF/ON

clearly illustrates the conduction state of $M_4$. When $V_{C2}<V_{DC}$ and $V_{C1}>Gnd$, $M_{P2}$ is turned on while $M_{N2}$ is turned off. The gate of $M_{P4}$ is grounded, keeping it on. At this point, the voltages across $M_{P4}$ are both high, causing $M_{P5}$ to turn off and $M_{N3}$ to turn on. Consequently, $V_{Control}$ discharges to ground through $M_{N3}$, forcing $M_4$ to turn off. $M_4$ turns on only when $V_{C2}>V_{DC}$ and $V_{C1}<Gnd$. At this stage, $M_{P2}$ is off, and the voltage across $M_{P4}$ discharges to $V_{C1}$ due to the conduction of $M_{N2}$. The voltage at $V_{Control}$, through the inverter formed by $M_{P5}$ and $M_{N3}$, rises to a high potential. The 4-input comparator may fail to make a correct judgment when $V_{C2}>V_{DC}$ and $V_{C1}>Gnd$ simultaneously. This occurs because both $M_{P2}$ and $M_{N2}$ are off, leaving $M_{P4}$ floating. Consequently, the conduction states of $M_{P5}$ and $M_{N3}$ become indeterminate, resulting in an ambiguous $V_{Control}$ output signal. However, this situation arises only when considering the comparator in isolation. In this paper, $V_{C1}$ and $V_{C2}$ are conjugate sine wave signals, as shown in Figure 6a. $V_{C2}>V_{DC}$ at its peak value, while $V_{C1}$ is at its valley, so $M_4$ remains off.

$$V_Y-Gnd=V_{TN}.$$

(10)

$$(V_Y-V_{C1})-V_{TN}>0.$$

(11)

$$V_{C1}<Gnd.$$

(12)

4. Simulation and Measurement

4.1. Simulation

The rectifier proposed in this paper is designed using a 0.18 μm, 3.3 V process model and operates with a 3.3 V sine wave input voltage.

Figure 8a presents the simulation results of the boost circuit. The first graph illustrates the node voltages after the input AC signal passes through the rectifier. The $V_{C1}$ and $V_{C2}$ signals are conjugate sinusoidal waveform. The red line represents $V_{C1}$, and the blue line represents $V_{C2}$. When $V_{C1}>V_{C2}$, the circuit is in the charging phase; when $V_{C1}<V_{C2}$, it is in the boost phase. The middle black line represents the voltage across the boost capacitor. During the charging phase, the capacitor is charged to 2.5 V through $M_{P1}$ and $M_{N1}$, and it is discharged at the end of the boost phase through $M_{N3}$ and $M_{N4}$. The simulation results below depict $V_{DC}$ and $V_{Boost}$ as the red and blue lines, respectively. It can be observed that $V_{Boost}$ undergoes two boosting processes. The first occurs when $M_{P4}$ and $M_{N3}$ in the right circuit boost $V_{Boost}$ to 2 V. The second boost, raising $V_{Boost}$ to 5.3 V, happens when $M_{N2}$ and $M_{P3}$ conduct. The above article addresses the protection of nodes susceptible to breakdown. The simulation results are shown in Figure 8b, which illustrates three common MOS breakdown effects [23,24]. The first is punch-through breakdown, occurring when the drain-to-source voltage difference becomes excessively large. In the boost circuit, $M_{P3}$ and $M_{N3}$ experience breakdown due to the excessively high $V_{Boost}$ voltage.

The blue and red lines in the figure represent the drain-to-source voltages of $M_{P3}$ and $M_{N3}$, respectively. The peak voltage, at 3.5 V, remains within the tolerable range. The second breakdown mode is oxide breakdown, which occurs due to the degradation of the gate oxide layer. The figure illustrates the voltages between the gate and drain/source terminals of $M_{P3}$ and $M_{N3}$ during the boost process. The blue and yellow lines represent the gate-to-source voltages of $M_{P3}$ and $M_{N3}$, respectively, while the red line indicates the common drain and gate voltage of the MOS transistor. The voltage levels remain below the breakdown threshold. Finally, junction breakdown occurs when the PN junction between the MOS device and the substrate fails. The blue and red lines correspond to the source-to-body voltages of $M_{P3}$ and $M_{N3}$, respectively. Once again, the protection mechanism prevents the voltages from reaching breakdown conditions.

Figure 9a presents the simulation results of a 4-input comparator. The five voltage signals shown are: $V_{Control}$ (blue line), $V_{C1}$ (red line), $V_{DC}$ (yellow line), $V_{C2}$ (purple line), and Gnd (black line). According to the operating logic of the comparator, $V_{Control}$ is low when $V_{C2}<V_{DC}$ and $V_{C1}>Gnd$. Under these conditions, the power transistor is turned off, thereby preventing reverse current during input voltage conversion. The power transistor turns on when the comparator output voltage is high. In the figure, the transition from low to high occurs when $V_{C2}>V_{DC}$ and $V_{C1}<Gnd$. The rectifier system is simulated as shown in Figure 9b. The yellow line represents $V_{C1}$, and the blue line represents $V_{DC}$. The NMOS gate voltage is boosted by a boost circuit, enabling the NMOS to have a charging capability equivalent to that of the PMOS. High voltage conversion efficiency is achieved through a gate cross-coupling structure. The output voltage within the red box has not yet stabilized. During this period, a precharge diode is necessary to participate in the rectifier operation. Once the output voltage reaches a stable state, the boost circuit can operate normally. At this point, $V_{DC}$ is 3.08 V, causing the precharge diode to become non-conductive and turn off.

Figure 10 and Figure 11 illustrate the VCE and PCE performance curves under various output loads. Figure 10 presents the pre-simulation results, while Figure 11 shows the post-simulation results. The Y-axis represents conversion efficiency, and the X-axis represents the output load, which ranges from 200 $\Omega$ to 10 KΩ. The VCE performance is analyzed at different input frequencies, ranging from 1 MHz to 3 MHz. The VCE curve demonstrates improved performance with increasing output load, as illustrated in Figure 10a and Figure 11a. Conversely, PCE performs better at lower output loads, as shown in Figure 10b and Figure 11b. In the pre-simulation, VCE reaches a maximum of 97% with a 10 KΩ output load and an input frequency of 2 MHz. Meanwhile, PCE attains a maximum of 84.82% with a 300 Ω output load and an input frequency of 1.5 MHz. In the post-simulation, the highest VCE is 97.08% with a 10 KΩ output load and an input frequency of 2 MHz, while the highest PCE is 84.68% with a 400 Ω output load and an input frequency of 1 MHz.

4.2. Measurement

Figure 12 [25] illustrates the circuit configuration used for measuring the rectifier chip. The transmitter circuit consists of an input signal, a power amplifier, and an RLC tank.

The input signal is generated by a function generator. For the application discussed in this paper, the function generator alone is insufficient to drive the energy harvesting systems; therefore, a power amplifier is required to enhance the driving capability. A class-D power amplifier (chip: BUF634) is employed for this purpose. The inductive coil was designed using the Texas Instruments coil designer. The specifications of the primary coil are shown in Figure 13b. The output impedance of the BUF634 power amplifier is 5 Ω. Therefore, a series RLC tank, with a Q value inversely proportional to R, is used to achieve a higher Q value and reduce energy loss. The Q value of the series RLC tank can be calculated using (13). In summary, the primary coil has an inductance (L) of 9.8 μH, a capacitance (C) of 630 pF, a resistance (R) of 5 $\Omega$, operates at a carrier frequency of 2 MHz, and has a Q factor ($Q_C$) of 24.94.

$$Q_C={\displaystyle \frac{1}{R}}\times \sqrt{{\displaystyle \frac{L}{C}}}.$$

(13)

The receiving circuit consists of an RLC tank, a rectifier circuit (as proposed in this study), and a load ($R_L$). The proposed rectifier chip has an input impedance of 600 $\Omega$; therefore, a parallel RLC tank is employed in the secondary coil design. Considering the parallel Q value calculation shown in (14), where Q is inversely proportional to L and directly proportional to C, a smaller inductance value is selected for the design. In practice, the secondary coil has L = 1.88 μH, C = 3300 pF, and R = 600 $\Omega$, as illustrated in Figure 13c, from which $Q_P$= 25.14 is obtained.

$$Q_P=R\times \sqrt{{\displaystyle \frac{C}{L}}}.$$

(14)

The coupling coefficient K represents the degree of coupling between inductive components. The value of K can be calculated using (15) and typically ranges between 0 and 1. Here, r = 7.3 mm (288 mils) is the radius of the inner coil of both the primary and secondary coils, and d = 1.5 cm is the distance between the two coils. Therefore, the value of K is calculated to be 0.327.

$$K={\displaystyle \frac{r}{r+d}}.$$

(15)

An oscilloscope serves as the primary measurement instrument. The four measurement signals are $V_{C1}$, $V_{C2}$, $V_{DC}$, and $G_{nd}$, with $G_{nd}$ representing the receiver reference voltage at 0 V. The overall PCB architecture is illustrated in Figure 13a.

Figure 14a,b show the chip layout and microphotographs, respectively. The chip layout is symmetrical from left to right, with each circuit block in the architecture enclosed within a box. The red box highlights the All-NMOS power MOS, which serves as the main power transistor of the rectifier and features a gate-crossed coupled structure. To prevent latch-up, all power transistors are NMOS devices. The yellow box indicates the Bootstrap and Comparator module, which enhances the charging performance of the NMOS transistors and controls reverse current. The orange box represents the Boost Capacitor; since its capacitance is 6.8 pF, a MOS capacitor structure is employed to save area. The blue box denotes the pre-charge power MOS transistor, which uses PMOS diodes as replacement components before the boost circuit stabilizes. The circuit’s maximum output current is 5 mA, so the power transistors occupy a relatively large area to avoid latch-up caused by components being placed too closely. Additionally, the wiring and layout are relatively sparse, resulting in a total area of 3.0096 mm².

Figure 15 presents oscilloscope measurement results. The four signal traces are as follows: red line for $V_{C1}$, green line for $V_{C2}$, blue line for $V_{DC}$, and yellow line for $I_{in}$. The input voltage $V_{in}=V_{C1}-V_{C2}$, is represented by the beige line. The input current $I_{in}$ is measured using a current probe, showing that current changes occur at the peaks of the sine wave. This confirms that the 4-input comparator effectively suppresses reverse current.

Figure 16 shows the VCE and PCE curves of the rectifier. The VCE and PCE values of the chip were measured at different output loads, ranging from 0.5 KΩ to 10 KΩ. The results indicate that VCE increases with increasing output load, and the conversion efficiency improves accordingly. After the output load exceeds 4 KΩ, VCE levels off, with the highest conversion efficiency of 89.02% achieved at $R_L$ = 8 KΩ. PCE, on the other hand, performs well at low loads but declines significantly as the output load increases, reaching a peak of 84.73% at $R_L$ = 500 $\Omega$.

Table 2. The performance of Rectifier chip.

	Pre-Simulation	Post-Simulation	Measurement
Supply voltage (V)	3.3	3.3	3.3
Operation Frequency (Hz)	2 M	2 M	2 M
Maximum current (mA)	5	5	5
Power dissipation (mW)	13.16	12.77	12.35
VCE (%) (8 KΩ)	97	96.92	89.02
PCE (%) (500 $\Omega$)	82.95	83.49	84.73

presents the overall rectifier performance using a sine wave signal with an amplitude of 3.3 V and a frequency of 2 MHz, along with a maximum operation current of 5 mA. The output load values at which VCE and PCE reach their maximum were determined through actual measurements, and the performance was compared with simulations. In the pre-simulation, the VCE reached 97% at $R_L$ = 8 KΩ, and the PCE reached 82.95% at $R_L$ = 500 $\Omega$. In the post-simulation, the VCE was 96.92% at $R_L$ = 8 KΩ, and the PCE was 83.49% at $R_L$ = 500 Ω. The power consumption of the chip was 12.35 mW at $R_L$ = 1 KΩ, compared to 13.16 mW in the pre-simulation and 12.77 mW in the post-simulation under the same conditions.

Analyzing the differences between simulation and measurement reveals that the VCE measurement is less efficient than the simulation but performs better in terms of power consumption and PCE. Since the output loads vary between light and heavy, the analysis is divided into two parts. Under heavy load, the output current is large, approaching the maximum output current. The power ($P_{PM}$) dissipated by the switching transistor can be calculated using Equation (16). The higher measurement efficiency under the same output load conditions indicates that the actual output impedance is smaller than that in the simulation, resulting in improved overall power consumption and PCE performance. However, analyzing VCE using the same method is not feasible under light load conditions because the current is very small, and the voltage drop across the on-resistance ($V_{Ds}$) is negligible, as shown in Equation (17). Therefore, the decrease in VCE is not caused by errors in on-resistance. The direct impact of the output current on the bootstrap circuit is insufficient charging of the boost capacitor. Since the output voltage is determined by the voltage division between $R_{ON}$ and the load resistance ($R_L$) in series, an increase in $R_{ON}$ causes a decrease in output voltage, which affects VCE. Referring to the PCE discussion, a smaller on-resistance corresponds to a larger transistor size. The transistor size is proportional to its total gate capacitance ($C_G$). Consequently, a larger $C_G$ further complicates the bootstrap charging of the transistor, causing the VCE performance to be slower than that predicted by the simulation.

$$P_{PM}=I_D^2\times R_L.$$

(16)

$$V_{DS}=I_D\times R_{ON}.$$

(17)

Table 3. Boost-Comparator Rectifier Benchmark.

	[26]	[27]	[28]	[29]	This Work
Technology	0.35 μm	0.18 μm	0.18 μm	0.18 μm	0.18 μm
Frequency	1.5 MHz	2.7 MHz	1–10 MHz	2 MHz	2 MHz
$V_{in}$	2.4 V	3 V	1.8 V	2.4 V	3.3 V
$V_{out}$	2.28 V	2.84 V	1.59 V	2.25 V	2.94 V
$I_{Max}$	20 mA	N/A	N/A	N/A	5 mA
VCE	97% (2 KΩ)	93.57% (500 Ω)	88.6% (300 Ω)	93.7% (500 Ω)	89.02% (8 KΩ)
PCE	87% (100 Ω)	94.51% (500 Ω)	84.4% (300 Ω)	91.7% (200 Ω)	84.73% (500 Ω)

compares relevant literature on boost comparator rectifier architectures. Our proposed design achieves the highest output voltage. Most implantable applications involve electrical stimulators that require sufficiently high-voltage pulses to effectively stimulate tissues. A higher output voltage eliminates the need for increased circuit complexity and power consumption to reach the necessary voltage levels. In energy storage applications, a higher voltage enables greater energy storage capacity ($E={\displaystyle \frac{1}{2}}C{V}^2$), facilitating device miniaturization and improved energy management. When processing weak physiological signals, low-voltage systems must carefully avoid noise interference and data loss. High-voltage systems provide better power supply rejection ratio (PSRR) for noise isolation and offer a higher dynamic range. Our proposed architecture attains VCE at 89.02% $R_L=8\mathrm{k}\Omega$ and 84.73% PCE at $R_L=500\Omega$, maintaining a high output voltage while demonstrating strong overall performance.

5. Conclusions

This study proposes a bootstrap-comparator rectifier design to achieve high VCE, high PCE, and enhanced reliability. Utilizing a gate cross-coupled architecture, the bootstrap circuit attains a rectifier VCE of $89.02\%$. A 4-input comparator is employed to suppress reverse current, resulting in a high PCE of $84.73\%$. To improve reliability, all-NMOS power transistors are used to prevent latch-up caused by parasitic P-N-P-N structures. An integrated protection mechanism ensures that no breakdown occurs at any node within the circuit. In implantable medical device (IMD) applications, the total rectifier output power ($P_{out}$) is 12.35 mW, achieving the $84.73\%$ PCE. According to Equation (18), the power loss ($P_{loss}$) is only 2.23 mW. Applying Equation (19), the temperature increase ($\Delta T$) is approximately 0.22–0.45 °C, which complies with the ISO standard limiting temperature changes to less than 2 °C for implants. The rectifier circuit is only one component of the WPT system. The complete system design will be finalized in the future, followed by construction for implantable measurement environments.

$$P_{loss}=P_{out}\times \left({\displaystyle \frac{1}{PCE}}-1\right)$$

(18)

$$\Delta T=R_{th}\times P$$

(19)