An Enhanced Fault-Tolerant Scheme for Arm-Multiplexing Modular Multilevel Converters

Abstract

The arm-multiplexing modular multilevel converter (AM-MMC) is a new compact MMC topology that is especially promising for offshore high-voltage direct current transmission systems. However, the reliable operation of AM-MMCs suffers from submodule (SM) faults. The fault-tolerant scheme is an effective measure to remedy the reliability of AM-MMCs. This paper presents an enhanced fault-tolerant scheme for SM faults. In this scheme, the fault-tolerant structure and control are proposed. Firstly, according to the pivotal constraints of AM-MMCs, the fault-tolerant structure is confirmed, as the redundant SMs distribute in each arm at the same number. Then, the fault-tolerant control composed of SM alternate launching and switching moment reset is proposed. The first method contributes to improving the defects of redundant SMs in normal operation and the second method invokes the redundant SMs in the specified arms to recover the postfault operation to the normal level. Based on the fault-tolerant structure and control, the fault-tolerant capability and performance are significantly enhanced. Moreover, the proposed fault-tolerant scheme consumes less construction cost, tolerates more SM faults and produces higher operation quality. Finally, the effectiveness of the proposed fault-tolerant scheme is validated by simulation results in MATLAB/Simulink.

1. Introduction

With the merits of modularity and flexibility [1,2,3,4], modular multilevel converters (MMCs) are the most commonly used converter topology in high-voltage direct current (HVDC) systems. For offshore HVDC systems, the converter station is highly sensitive to the power density, volume and weight [5,6], which increases the cost and difficulty of converter station platform construction. The multiplexing-type MMC can fully utilize the modulation spare capacity of the conventional MMC. By that, the number of SMs or capacitors can be sharply decreased and the compact design can be achieved.

Due to the high-voltage and high-power scenario, the remaining SM number in multiplexing-type MMCs is still large and can be up to the hundreds, even if the SM number has been significantly reduced compared with the conventional MMC. Under the high-voltage and large-current circumstance, devices such as IGBT (Insulate-Gate Bipolar Transistor) modules, capacitors and drivers are prone to the occurrence of faults. The large number of SMs indicates that the potential fault points are numerous. Thus, the fault-tolerant operation scheme is vital for multiplexing-type MMCs to ensure the reliable operation.

For MMCs, diverse fault-tolerant measures have been reported. Among them are the three following categories: 1. cold-standby redundant SM-based methods; 2. hot-standby redundant SM-based methods; 3. new SM topology-based methods. In [7,8,9,10], the cold standby redundant SM and the corresponding fault-tolerant method are introduced. The cold standby SMs are completely irrelevant to the normal operation of MMCs and stay in the bypassing state. After the definite triggering signal is given in the postfault condition, fault-tolerant methods will launch these SMs to replace faulty SMs. That way, the postfault operation of MMCs can be recovered with a simple procedure. It is obvious that the cold-standby SMs are not charged in their normal condition. Thus, a long charging interval is needed before the working of cold-standby SMs in the postfault condition. A spontaneous and drastic charging process may further deteriorate operation performance based on SM faults. Then, the charging control based on reference updating [11], three-stage charging control [12], and charging control based on a parabolic function [13] are respectively proposed to yield smooth charging processes, even though the defect of cold-standby SMs is implicit and the charging influence cannot be completely cleared.

Due to the charging defect, the hot-standby redundant SM-based methods have attracted much attention. Different from the cold-standby redundant SM, the hot-standby redundant SM is charged regardless of normal or faulty situations. Furthermore, the hot-standby redundant SM-based methods can subdivided into two types: 1. fault-tolerant methods based on voltage-increasing; 2. fault-tolerant methods based on controllers. In [14,15], the capacitor voltages are increased based on the analysis of arm energy balance. Differently from those, refs. [16,17] adjusts the capacitor voltage according to the number of faulty SMs. In addition, several dynamic voltage-increasing methods, such as voltage-increasing based on the averaging capacitor voltage tracking [18], dynamic redundancy index-based voltage adjustment [19], and piecewise flexible voltage-increasing [20], have also been proposed to serve for fault tolerance. Although the above methods can realize high-quality fault-tolerant operation, the remaining healthy SMs and the internal devices are subjected to higher voltage stress than the rated value. Similarly, based on hot-standby SMs, designated PI control [21], PR control [22,23], compensation component injection control [24], and selective harmonic mitigation control [25] have been reported to realize fault-tolerant operation. These methods based on controllers can avoid the voltage increase, but the controller structure and parameter design raise the implementation difficulty. More importantly, since the normal operation of hot-standby SMs is equal to that of ordinary SMs, the operation loss and invalidation risk of them also equal that of ordinary SMs.

The SM topologies are the other proposed solutions to the fault-tolerance issue. In [26], the switch redundancy of full-bridge SMs is utilized to handle two switches responsible for outputting zero voltage. The two switches responsible for outputting high voltage still need extra standby SMs. A novel SM was proposed in [27] and its fault-tolerant capability is also based on switch redundancy. Similarly to [26], some switch faults inside this SM still need standby SMs to tolerate. Accordingly, these methods cannot eliminate the limitations of the conventional standby modes. In [28,29], the other two fault-tolerant SM topologies were presented, which can provide a cold–hot mixed standby mode to overcome the defects of the two conventional standby modes. However, these new topologies are not compatible with the MMC stations that have put into operation.

As an improved topology based on MMCs, different multiplexing-type MMCs have been proposed. In [30,31], the numbers of SMs in the existing upper arm and lower arm are reduced to form the multiplexing arm, which can operate together with the upper or the lower arm. Besides the arm multiplexing, other multiplexing structures were reported in [32,33]. In [32], the capacitor group is connected to the three upper arms by a converter and the three lower arms have the same structure. Then, the multiplexing operation can be realized among three arms. The topology in [33] is similar to that of [32], except the capacitor group is exchanged with the SM group. Compared with that of [32], this structure possesses stronger modulation flexibility. Besides these, an SM and its counterparts in the other two phase legs share a common capacitor in [34]. Thus, the capacitor account can be effectively reduced. Although abundant fault-tolerant methods for MMCs have been presented, this field for multiplexing-type MMCs is blank; only the modulation strategies for the normal operation were reported in [30,31,32,33,34].

To ensure the operation after faults, this paper proposes a fault-tolerant scheme for the multiplexing-type MMC. The main contributions of this manuscript are as follows:

• The fault-tolerant topologies for AM-MMCs are originally explored and analyzed. According to this, the fault-tolerant structure and configuration most compatible with the lightweight target is confirmed.
• The SM alternate launching method is proposed to regulate the standby SMs to intermittently take part in the operation, which can retain the advantage and remove the disadvantage of the existing hot and cold standby modes in the normal condition.
• The switching moment reset method is proposed to promote fault-tolerant capability to cope with more faulty SMs and realize the enhanced fault-tolerant performances in the postfault condition.
• Compared with the conventional method, the proposed fault-tolerant scheme shows significant merits of simpler implementation, lower constructed cost, better operation performance and higher fault-tolerant capability and quality.

The remainder of this paper is organized as follows. The basic operation principle of multiplexing-type MMC is introduced in Section 2. The fault-tolerant structure of multiplexing-type MMC is presented in Section 3. The fault-tolerant control is proposed in Section 4. The effectiveness of the proposed fault-tolerant scheme is verified in Section 5. Finally, the conclusion is drawn in Section 6.

2. Basic Principle of Multiplexing-Type MMCs

2.1. Topology Structure

As shown in Figure 1a, each phase of an MMC is composed of upper and lower arms. Each arm is cascaded with N SMs. Moreover, as shown in Figure 1b, the modulation strategy always inserts N SMs to bear the DC voltage at each moment. This means that many SMs in an arm are spare and do not contribute to bearing the DC voltage.

As presented in [30,31], the arm-multiplexing modular multilevel converter (AM-MMC) fully utilizes the modulation spare capacity of the upper and lower arms and reduces SMs in these two arms to form the multiplexing arms (MAs). AM-MMCs can realize the lightweight target and furthest retain the topology and control feature of MMCs. Thereby, this paper focuses on the fault-tolerant scheme for AM-MMCs.

The potential topologies of AM-MMCs are shown in Figure 2. In AM-MMCs, not only the upper arm and lower arm, but also diverse Mas, exist. Moreover, the AC bus connects these arms through the selector switches K₁-K_n. As the topology structures illustrate in Figure 2, the SM is the half-bridge structure, consisting of semiconductors and capacitors. The selector switch is composed of the semiconductor combination that devices are connected to in reverse series. Moreover, the numbers of semiconductors in each direction in the selector switches are different when the selector switches are at different locations. As in the case of R = 2 in Figure 2, the outermost selector switches K₁ and K₃ only bear the unidirectional voltage. Thus, there is only one semiconductor device in a direction to control conduction and numerous devices are cascaded in the other direction to withstand the voltage. In the internal selector switch K₂ that needs to bear the bidirectional voltage, multiple devices in each direction are needed. The number of devices in each direction is determined by the bearable voltage value. Moreover, it can be inferred that the consumed devices in the two types of selector switches are almost equal and K₃ has one more device than K₂.

As mentioned, AM-MMCs are mainly built with power electronic semiconductors and capacitors. To clearly compare AM-MMCs with different structures, the power electronic semiconductors used in the SMs and selector switches are both IGBTs with the same specification. That means that all the used semiconductors have the same voltage and current ratings, and cooling and insulation requirements. With these assumptions, the cost and weight considering different operation indexes can be uniformly marked by the consumed number of IGBT modules. Moreover, according to [30,31,35,36,37], the cost of the capacitor is twice that of the IGBT module and the weight of the capacitor accounts for 80% of a whole SM. Combining this, the comparison among diverse AM-MMCs can be inferred and organized.

As shown in Figure 2, assume there are R multiplexing arms in a phase leg. Combining the upper and lower arms, there are total of R + 2 arms in each phase leg and a total of 3(R + 2) arms in an AM-MMC. Since each selector switch connects two arms, the number of selector switches in each phase leg is R + 1. Notably, the number of selector switches is also 0 when R = 0, which denotes that the AM-MMC is just the conventional MMC. To realize the identical system voltage as the conventional MMC, the R multiplexing arms must be connected to the upper arm or the lower arm to be equivalent to the upper or lower arm in the MMC, which contains N SMs. Thus, the total number of SMs in these R + 1 arms is N. Then, the N SMs are evenly distributed in the R + 1 arms. As a result, the number of SMs in each arm is N/(R + 1) and the total number of SMs in the AM-MMC is 3(R + 2)·N/(R + 1). Then, the consumed capacitors are 3(R + 2)·N/(R + 1) and the used IGBTs in the SMs are 6(R + 2)·N/(R + 1). Moreover, considering the voltage bearing capability and the blocking requirement, the needed IGBT number in each selector switch is R·N/(R + 1). Since the total number of selector switches in an AM-MMC is 3(R + 1) and the two outermost selector switches in each phase leg needs two IGBTs to realize the conduction control, the IGBTs for selector switches in an AM-MMC are 3R·N + 6. It can be further determined that the total number of the consumed IGBTs in the AM-MMC is (3R² + 9R + 12)·N/(R + 1) + 6.

To maximize the lightweight and economic efficiency for offshore converter stations, the comparison of different potential AM-MMC topologies is shown in

Table 1. Comparison of different AM-MMCs.

Topology	MA Number	C and SM Numbers	Switch Number	Cost	Weight
MMC	R = 0	1	1	1	1
AM-MMC_1	R = 1	0.75	1	0.875	0.8
AM-MMC_2	R = 2	0.667	1.167	0.917	0.767
AM-MMC_3	R = 3	0.625	1.375	1	0.775
AM-MMC_4	R = 4	0.6	1.60	1.1	0.8
AM-MMC_5	R = 5	0.583	1.833	1.208	0.833
AM-MMC_6	R = 6	0.572	2.075	1.323	0.872

. It worth noting that the comparison is based on the premise that AM-MMCs can realize the same function as MMCs. Therefore, the indexes of the MMCs are set as the base and the relative values of each index of the AM-MMCs are listed in Table 1.

As shown in Table 1, both the utilized capacitors (C) and SMs are reduced with the increase in MAs. Inversely, the number of switch devices becomes larger and larger because the selector switches that are constructed by numerous power electronic switch devices also increase. Due to this, the costs and weights of AM-MMCs do not present a monotone decreasing feature. Although the cost of AM-MMC_2 is a little higher than that of AM-MMC_1, the weight of AM-MMC_2 is the lightest, which can reduce the construction difficulty and cost of the offshore support platform. This is one of the most concerning issues of offshore HVDC systems. Considering this, it can be determined that the best comprehensive performance belongs to AM-MMC_2, which contains two MAs; namely, there are four arms in each phase leg. In addition, the fewer arms also mean that the control difficulty of AM-MMC_2 is lower. Thereby, the AM-MMC in the following description refers to AM-MMC_2.

2.2. Operation Modulation

To ensure that the AM-MMC can realize the same performance as the MMC in which each arm contains N SMs, the SM numbers of the upper arm, MA1, MA2 and the lower arm in the AM-MMC should all be N/3. Furthermore, the modulation of the AM-MMC is similar to that of the MMC, and the control algorithms that generate references and switching signals can directly inherit those of the MMC. The key is the operation modulation of the multiplexing arms, which is described as follows:

Firstly, the operation mode of the AM-MMC is divided as:

$$\mathrm{mode}=\left\{\begin{array}{cc}1,\hfill & {\displaystyle \frac{2N}{3}}<N_{on}\le N\hfill \\ 2,\hfill & {\displaystyle \frac{N}{3}}<N_{on}\le {\displaystyle \frac{2N}{3}}\hfill \\ 3,\hfill & N_{on}\le {\displaystyle \frac{N}{3}}\hfill \end{array}\right.$$

(1)

where N_on represents the number of SMs inserted in an arm of the conventional MMC and is determined by the nearest level modulation (NLM). Notably, since the case of the upper arm is taken as the example, N_on also means the number of inserted SMs in the upper arm.

According to the modes, the signals of the selector switch K_j1–3 (j = a, b, c) are further allocated as:

$$\mathrm{mode}=\left\{\begin{array}{c}1,K_{j1}=0, K_{j2}=0, K_{j3}=1\\ 2,K_{j1}=0, K_{j2}=1, K_{j3}=0\\ 3,K_{j1}=1, K_{j2}=0, K_{j3}=0\end{array}\right.$$

(2)

Combining (1) and (2), the operation modulation principle of the AM-MMC is described as follows:

(1)

Mode 1: N_on is within the range of [2N/3, N], the selector switches K_j1, K_j2 are disconnected and K_j3 is conducting. As shown in Figure 3a, the multiplexing arms MA1 and MA2 are connected in series with the upper arm, forming an equivalent upper arm with N SMs, and is identical to a conventional upper arm. Since the total number of inserted SMs in a phase leg at each moment is N, the number of SMs required for the lower arm in Mode 1 ranges from [0, N/3]. Consequently, the lower arm of the AM-MMC operates independently, and its internal N/3 SMs can meet the modulation requirements.

(2)

Mode 2: When N_on lies within the interval [N/3, 2N/3], the selector switches are configured that K_j1, K_j3 are disconnected and K_j2 is conducting. As shown in Figure 3b, MA1 and MA2 are respectively connected in series with the upper and lower arms. As a result, both the equivalent upper arm and the equivalent lower arm contain 2N/3 SMs. In this scenario, the numbers of SMs required for the upper and lower arms of the MMC also range from [0, 2N/3]. Therefore, both the equivalent upper and lower arms of the AM-MMC satisfy the modulation requirements simultaneously.

(3)

Mode 3: N_on is within the range of [0, N/3], and K_j1 is conducting while K_j2 and K_j3 are disconnected. Moreover, it can be inferred that the largest inserted SM number in the lower arm of the MMC is N. As shown in Figure 3c, the upper arm operates independently, and the shared arms MA1 and MA2 are connected in series with the lower arm. Correspondingly, the equivalent lower arm of the AM-MMC contains N SMs. Thus, both the equivalent upper and lower arms of the AM-MMC satisfy the modulation requirements.

Moreover, as the key component to realize the arm multiplexing, the practical implementation of the selector switch is as follows. Although the selector switches conduct in different modes, the current stresses of them are the same. Since all the selector switches are connected to the AC side, the currents flowing through these selector switches are AC. However, the voltage stresses on the selector switches are different. According to the on and off states in the three operation modes, the voltage stresses on K₁ and K₃ are the sum of the output voltages of MA1 and MA2, and the voltage stress on K₂ is the output voltage of MA1 or MA2, namely a single arm voltage. The selector switch contains plentiful semiconductor devices to bear the voltage and these devices may not realize the completely synchronous action, which makes some of the devices bear the whole voltage while the others do not bear any voltage. Device shoot-through caused by the transient overvoltage will occur. Moreover, the asynchronous actions of the devices in the selector switches may cause the selector switch not to achieve the expected action. For example, the switch is going to conduct, but some devices do not conduct at the same time as the others, causing the whole switch to be disconnected. More seriously, the asynchronous actions may make the commutating selector switches all stay in the off state, and current interruption will emerge. To avoid this, the safe commutations of the selector switches need two measures. The first is to reduce the output voltage of the multiplexing arm to 0. Differently from the dead time set for the complementary IGBTs, the second is to set an overlap time between the selector switches to be disconnected and connected. The operation of the AM-MMC is Mode 1, Mode 2, Mode3, Mode 2, Mode 1, …, which is a cycle. Thus, the detailed commutation process is as follows:

(1)

Mode 1 to Mode 2: At this moment, K_j1 stays disconnected. K_j2 is going to conduct and K_j3 is going to break. These two switches are connected to the two terminals of MA2. Thus, to bypass all the SMs in MA2 and make the output voltage of MA2 equal 0, the safe commutation can be realized since N_on is equal to 2N/3 at this moment and the UA and MA1 can provide 2N/3 SMs for the equivalent upper arm. Furthermore, the number of the inserted SMs in the equivalent lower arm is N/3, so the LA can also meet the requirement without MA2.

(2)

Mode 2 to Mode 3: At this moment, K_j3 stays disconnected. K_j1 is going to conduct and K_j2 is going to break. These two switches are connected to the two terminals of MA1. Thus, to bypass all the SMs in MA1 and make the output voltage of MA1 equal 0, the safe commutation can be realized. At the moment, N_on is equal to N/3 and UA is enough to provide these SMs. Meanwhile, even though MA1 is bypassed, the equivalent lower arm depending on LA and MA2 can also provide 2N/3 SMs. Thus, the operation requirement will not be affected by bypassing MA1 at the commutation moment.

Since the commutation process is realized by the power electronic semiconductor device, the duration is short. After the temporary bypassing, the SMs in the multiplexing arm can successively insert to support the operation of the AM-MMC. Based on the above, this measure will not influence the operation of the AM-MMC. With the elimination of the specific multiplexing arm voltage, the selector switches that need to change states bear no voltage. Thus, no transient overvoltage will be caused by the differences of the semiconductor devices and thereby no device shoot-through will occur. In addition, the zero voltage of the specific multiplexing arm makes the right-side terminals of the two commutating selector switches have voltage equipotential. Then, an overlap time can be set between the commutating switches and then there is always an existing conducting selector switch. With that, the three selector switches can realize seamless conductions; no interruption will occur in the AC current and the current continuity can be ensured. Moreover, the zero-voltage circumstance and the continuous current can smoothly realize the commutations of the selector switches, without the potential mode-transition chattering to frequently change states to satisfy the voltage-bearing and current-continuation requirements. For a high-voltage AM-MMC, the control cycle can be up to hundreds of microseconds and the semiconductor devices, such as IGBTs, are famous for their fast action time. Thus, to handle the asynchronous action of IGBTs, the overlap time is very small and will not influence the operation of the AM-MMC. Due to no transient overvoltage, device safety, current continuity and no mode chattering, the reliabilities of the selector switches and their commutation processes are effectively ensured.

3. Fault-Tolerant Structure of AM-MMCs

As aforementioned, the cold-standby SM will cause charging influence. It is undesirable to the converter station that sustains electric power quality. Consequently, the practical project mainly adopts hot-standby SMs to realize the fault-tolerant task. Due to this, the fault-tolerant scheme of AM-MMCs is also built based on hot-standby SMs.

In an MMC, the hot-standby SMs are directly configured in each arm. However, an AM-MMC has multiple arms, and the standby SMs can be configured at different locations and in different numbers. The diversity will derive different fault-tolerant structures. The details are shown in Figure 4, where the standby SMs and the increased devices in selector switches are marked in red.

(1)

Type 1: The standby SMs are placed in the two MAs, as illustrated in Figure 4a. It is obvious that the multiplexing of standby SMs can make the fault tolerance more flexible and raise the utilization ratio of standby SMs. Since the two extra MAs increase the SMs, the consumed devices in the selector switches also increase to bear the higher voltages yielded by the MAs.

(2)

Type 2: As shown in Figure 4b, the standby SMs locate at the upper and lower arms. According to the modulation principle, the two MAs must operate with the upper or lower arms. Thus, Type 2 can cover the faults in each arm of the AM-MMC. In addition, since the standby SMs are not added in the MAs, the configurations of the selector switches are unchanged.

(3)

Type 3: The standby SMs are distributed in each arm in Figure 4c. With this configuration, the faults can be directly tolerated without any special requirements. Similarly to Type 1, the numbers of the devices in the three selector switches also increase. The increased devices in the two outside switches K₁, K₃ are the same as that in the inside switch K₂. This is because K₂ needs to realize bidirectional voltage-bearing.

To further analyze and confirm the optimal structure, the fault-tolerant structure of MMCs is used as the standard. In an MMC, assume each arm is configured with 3M standby SMs. That means that at most 3M faulty SMs can be tolerated among the N SMs in an arm. To achieve the same fault-tolerant performance in AM-MMCs, the details of the three fault-tolerant structures are listed in

Table 2. Configurations of fault-tolerant structures.

Structure	Standby SM Number						Added Devices Number
	UA	MA1	MA2	LA	SM-C	SM-I	K1	K2	K3	Sum
Type 1	0	1.5M	1.5M	0	3M	6M	3M	3M	3M	9M
Type 2	3M	0	0	3M	6M	12M	0	0	0	0
Type 3	M	M	M	M	4M	8M	2M	2M	2M	6M

, where SM-C and SM-I denote the used capacitors and IGBTs in SMs, and UA and LA are short for upper arm and lower arm. The three types of fault-tolerant structures add different numbers of standby SMs in each arm. The added IGBTs and capacitors in the standby SMs can be easily counted by the number of standby SMs. In addition, the standby SMs in the multiplexing arms impose extra voltage stresses on the selector switches, which means that the numbers of the voltage-bearing IGBTs in the selector switches need to rise. According to the voltage bearing capability and the blocking requirement of the three selector switches, the added IGBTs in selector switches can also be derived by the number of standby SMs. Thus, the cost, number of different devices and voltage stress can be uniformly counted by the number of standby SMs. For the three types, Type 1 increases the most selector switch (K_1–3) devices and Type 2 increases the most SM devices. Combining the price relation between the capacitor and IGBT previously introduced and taking the price of a single IGBT as the unit, the costs of the three types can be represented and compared by the numbers of consumed IGBTs as 21M for Type 1, 24M for Type 2 and 22M for Type 3. In addition, Type 2 consumes the most capacitors. As previously mentioned, the capacitor accounts for the majority of the whole weight, and thus Type 2 is really unfavorable to realize lightweight. Due to the higher weight, the extra cost for the platform and base to place and support the converter station will also be increased. Therefore, Type 1 and Type 3 are superior to Type 2 in terms of the cost and lightweight.

Furthermore, the capabilities of the three fault-tolerant structures are listed in

Table 3. Capability of fault-tolerant structures.

Structure	Largest Effective Tolerable Number of Faulty SMs
	Mode 1	Mode 2	Mode 3	UA	MA1	MA2	LA
Type 1	3M	1.5M	0	0	1.5M	1.5M	0
Type 2	3M	3M	3M	3M	3M	3M	3M
Type 3	3M	2M	M	M	M	M	M

. Regardless of the tolerable number of faulty SMs for the operation mode or single arm, Type 1 is the worst option. From this perspective, Type 2 is better than Type 3.

However, comprehensively considering the cost in Table 2 and fault-tolerant capability in Table 3, Type 3 is selected in this paper. The quantitative analysis is as follows: 1. Cost advantage. As analyzed for Table 2, Type 3 is superior to Type 2 in terms of cost and lightweight. 2. Satisfaction for the basic fault-tolerance requirement. In the previous assumption for MMCs, an arm with N SMs is required to tolerate 3M faulty SMs and the fault-tolerant ratio is 3M/N. To be fully equivalent to the MMC, the AM-MMC should also meet this basic requirement. With Type 2 and Type 3, each arm with N/3 SMs can at least tolerate M faulty SMs in the AM-MMC and the fault-tolerant ratio is also 3M/N. Thus, the fault-tolerant capability is enough for the basic operation. 3. Identical advanced fault-tolerant capability. Based on the basic fault-tolerant ratio, Type 2 can provide the advanced capability to raise the fault-tolerance ratio to 9M/N. For Type 3, only some of the operation scenarios can reach that ratio. However, Type 3 can offer flexibility to the fault-tolerant control, which enhances the fault-tolerance capability. Moreover, with the subsequently proposed fault-tolerant control, the fault-tolerance capability based on Type 3 can be the same as that based on Type 2.

4. Fault-Tolerant Control of AM-MMCs

The defects of hot-standby SMs mainly occur in the normal operation stage. Thereby, the regulation for the hot-standby SMs in the fault-tolerant structure under normal operation of AM-MMCs is a key part of fault tolerance for AM-MMCs. In addition, enhancement of the fault-tolerance capability is also crucial. Thus, the proposed fault-tolerant control of AM-MMCs is presented in the normal operation and postfault operation.

4.1. Normal Operation of AM-MMCs with Fault-Tolerant Structure

In MMCs, the hot-standby SMs do not support the modulation. This indicates that the DC voltage is still undertaken by N SMs of a phase leg at each moment, rather the total N + 3M SMs. Thus, the rated capacitor voltage of both MMCs and AM-MMCs is expressed as:

$$U_{rated}=U_{dc}/N$$

(3)

However, hot-standby SMs take part in modulation. For example, if N_on is equal to X, the NLM will select X SMs with proper capacitor voltages from N + 3M SMs to operate. Then, the standby SMs can also be inserted like the ordinary SMs. In order to focus on theoretical analysis, the transient processes for the turn-on and turn-off of the semiconductor devices are ignored and the IGBTs in SMs are regarded as ideal switches. Based on the above, the average switching function is changed as:

$$S_{avg}={\displaystyle \frac{N_{on}}{N_k+kM}}$$

(4)

where N_k denotes the total number of SMs in the equivalent arm. k is equal to 1, 2 or 3. It is determined by the number of arms contained in the equivalent arm.

Due to the same insertion opportunity, the capacitor voltages in hot-standby SMs can be well charged as ordinary SMs, but the high similarity to ordinary SMs also imposes the same loss and fault risk to the standby SMs. Besides these, the circulating current will also increase under the operation mode. Although the selector switches adjust the multiplexing arms to operate together with the upper or lower arm, the equivalent arm voltages are still the superposition of the SM voltages contained in the arms. Thus, the equivalent arm model is immune to the selector switch transition effects. Combining the equivalent arm model, the circulating current can be calculated as:

$$2L_s{\displaystyle \frac{d{i}_{cirj}(t)}{dt}}=U_{dc}(t)-{\displaystyle {\displaystyle \sum _{i=1}^{N_{x\_u}}}{S}_{avg\_u}{U}_{cui}}-{\displaystyle {\displaystyle \sum _{i=1}^{N_{x\_l}}}{S}_{avg\_l}{U}_{cli}}$$

(5)

where the subscripts u and l denote the equivalent upper arm and equivalent lower arm of an AM-MMC. U_ci is the capacitor voltage, which can be expressed by arm current i_arm as:

$$U_{cxi}=U_{rated}+{\displaystyle \frac{1}{C}}{\displaystyle \int S_{avg}{i}_{arm}dt}$$

(6)

In high-voltage scenario, the AM-MMC contains plentiful SMs, but these SMs are in the same structure built by the same specification devices, and thus the SM parameters are identical. Furthermore, under the voltage-balancing algorithm, the capacitor voltages are well balanced and ripple around the rated value. Due to that, the capacitor voltages in the equivalent upper or lower arm can be deemed as equal. Then, (5) can be simplified as:

$$2L_s{\displaystyle \frac{d{i}_{cirj}(t)}{dt}}=U_{dc}(t)-N_{on\_u}{U}_{cui}-N_{on\_l}{U}_{cli}$$

(7)

In (7), N_{on_u} and N_{on_l} are yielded by NLM and NLM and confirm these N_on based on U_rated. However, the actual inserted capacitor voltage is U_cxi in (6) rather than U_rated in (3). Due to this deviation, i_cirj in (5) emerges. It is obvious that the AC component in U_cxi is larger, the deviation between U_cxi and U_rated is larger, and i_cirj will be more serious. This AC component is related to S_avg. If M is smaller in (4), the inserted opportunity is assigned to fewer SMs and each SM has higher possibility to change states. The more abundant state changes can make the capacitor voltage be more properly adjusted by i_arm and the AC component can be reduced. Then, i_cirj will be also weakened.

Based on the above analysis, the following conclusions can be drawn:

• If hot-standby SMs reduce the working duration in the arm, the operation loss and fault risk can be lowered.
• If hot-standby SMs do not participate in modulation, the circulating current will be reduced.

To realize the above, the alternate launching method is proposed. Firstly, only N_k capacitor voltages are allowed and sent to the voltage-balancing algorithm (VBA). By that, the N_on inserted SMs can only be selected from N_k SMs. The implementation method is that kM standby SMs and the same number of ordinary SMs are alternately put into the N_k SMs. Then, the number of the SMs participating in the modulation is kept as N_k and kM SMs are forbidden to join the modulation, which is equivalent to kM in (4) equalling 0. Thus, the circulating current can be reduced. In addition, the alternate launching makes the standby SMs intermittently operate, which can ensure the lower loss and risk, and keep the capacitors in the standby SMs well charged. Therefore, the alternate launching method integrates the advantages of hot-standby and cold-standby SMs. The details are shown as Figure 5.

In Figure 5, the case of Mode 2 is used to express the alternate launching operation. To simplify the control, the alternate objects of the M standby SMs in each arm are selected as the fixed SMs. Since the alternate operation can lower fault risk, the M higher fault-prone ordinary SMs confirmed by the condition-monitoring algorithm can be employed as the alternate SMs. Although M higher fault-prone ordinary SMs may distribute in the whole arm and are not serial, it is still easy to realize. That is because the condition-monitoring algorithm has confirmed M SMs, and the M standby SMs are usually the last successive M SMs in an arm. These known SM messages will be sent to the control system. According to the SM settings, the proposed method will regulate these SMs to realize the alternate operation. In Figure 5, M higher fault-prone ordinary SMs are assumed as the first M SMs in each arm. These SMs and standby SMs are alternated to incorporate to the capacitor voltage list. The alternate interval can be 1~n line cycles. Then, always 2N/3 capacitor voltages are sent to the VBA and 2N/3 + 2M switching signals are generated. Thus, 2M SMs do not join modulation and each arm has no extra loss. Meanwhile, the standby SMs are also well charged.

As shown in Figure 5, the SMs taking part in the alternate launching will stay in the bypassing state and operating state alternatively for a certain interval. As previously mentioned, the alternate interval is the crucial parameter of the proposed alternate launching and can be k times the line cycle, where k is an integer. Therefore, the two states will respectively continue k line cycles. When the capacitor voltages are in the operating state, they can balance with the capacitor voltages in the ordinary SMs that are not involved in the alternate launching. Since the bleeding resistor is connected in parallel with the capacitor in the SM, the capacitor voltage will degrade during the bypassing state if the alternate interval is too long. When the alternate interval is properly selected, the capacitor voltage values are equal or only have little deviation at the terminals of the bypassing state interval. It is the basic to maintain the capacitor voltage balancing. Furthermore, the capacitor voltages in ordinary SMs that do not join the alternate launching are periodical components and fluctuate periodically. Then, they can also be almost equal with each other at the terminals of the bypassing state interval. Moreover, the beginning of the bypassing state interval is the ending of the operating state interval. As previously mentioned, all the capacitor voltages are balanced in the operating state interval. Combining the above, the voltage balancing can be well maintained when the capacitor voltages finish bypassing states to enter operating states again. This indicates that the alternate launching has no influence on the capacitor voltage balancing if the alternate interval is properly selected. It is worth noting that capacitor voltages belonging to the bypassing state in the alternate launching will exhibit a relatively large deviation with other capacitor voltages. This deviation has no influence on the operation, since these bypassed SMs are excluded and do not join the modulation.

Differently from the capacitor voltage balancing, the switching losses are not affected by the alternate interval. Compared with the conventional standby method, the standby SMs are no different from the ordinary SMs. Therefore, the extra switching losses in the standby SMs will be yielded, i.e., a total of N_r + M times P_loss exist. N_r denotes the number of SMs in a single arm of an AM-MMC. P_loss means the switching losses of a single SM. The alternate launching method can make M standby SMs and M ordinary SMs alternatively operate. When the M standby SMs are in operating state and the selected M ordinary SMs are in the bypassing state, the standby SMs generate switching losses and the ordinary SMs have no switching losses, and vice versa. In essence, M times P_loss are allocated to the 2M SMs, and the total loss is reduced. Compared with the conventional method, the total switching losses decrease to N_r times P_loss under the proposed alternate launching method. However, regardless of the duration of the alternate interval, always N_r SMs take part in the modulation. Thus, the alternate interval has no influence on the total switching losses.

Thus, the alternate interval can be selected based on the capacitance, the bleeding resistance and the allowed range of the capacitor voltage fluctuation. In general, several line cycles will not cause serious degradations in capacitor voltages. After the alternate interval is selected, the alternate launching method can be easily realized in the control system. The condition-monitoring algorithm has confirmed the ordinary SMs to alternatively exchange states with the standby SMs. Therefore, it is sufficient that the values in the capacitor voltage sorting of the voltage-balancing algorithm update along with the specified capacitor voltages with the alternate interval. Compared with the conventional method, the data quantity in the voltage-balancing algorithm is reduced from N_k + kM to N_k under the alternate launching method, which can lower the burden of the control system. Besides these, no extra change is needed, and thus the control complexity does not rise.

4.2. Fault-Tolerant Operation of AM-MMCs

Although Type 3 has the same fault-tolerant capability as MMCs, the stronger fault-tolerant capability means stronger reliability of AM-MMCs. With the accessing of the multiplexing arms, the largest fault-tolerant number of an equivalent arm is changed and is in the range M~3M. For example, the equivalent upper arm can tolerate 0~M faults when it consists of the single upper arm, 0~2M faults when it consists of the upper arm and a multiplexing arm, and 0~3M faults when it consists of the upper arm and two multiplexing arms. If the faults distribute evenly in multiple arms, at most 3M simultaneous faults can be tolerated, such as M faults respectively occurring in the upper arm, MA1 and MA2, even though, to ensure the overall reliability, the equivalent upper arm can tolerate at most M faulty SMs since the standby SMs in multiplexing arms cannot help to cope with extra faults when the upper arm operate solely with more than M faulty SMs. Obviously, much of the fault-tolerant potential is wasted and the total fault-tolerance capability is determined by the largest fault quantity that a single arm can handle. Due to this, the switching moment reset-based fault-tolerant control is developed. Under this method, the operation reliability can be well maintained when 3M faults simultaneously occur in a single arm. With this capability, the feasible fault-tolerant boundary of the equivalent arm is enhanced to 3M. Moreover, regardless of which arm the fault is located in, the equivalent upper or lower arm can at most tolerate 3M faults. Since the conditions of the upper arm and MA1 are respectively the same for the lower arm and MA2, the fault conditions of the upper arm and MA1 are analyzed in detail.

If 3M SMs in the upper arm malfunction, the operation is shown in Figure 6, where the SMs in gray, in orange and in purple represent faulty SMs, operating SMs and leisure SMs, respectively. Since standby SMs are usually inactive, they are also purple in color. As shown in Figure 6a, the SMs are adequate in Mode 1 before switching to Mode 2. Even if the modulation requires all the ordinary SMs in the three arms to operate, the 3M standby SMs in UA, MA1 and MA2 can completely supplement the lacking SMs in Mode 1. According to the modulation rule introduced in Section 2, Mode 1 will switch to Mode 2 at the moment that N_on of the equivalent upper arm equals 2N/3. When switching to Mode 2, shown in Figure 6b, the reduced N/3 SMs and the missing 3M faulty SMs make the equivalent upper arm unable to meet modulation. Compared with Figure 6a, M SMs are lacking in Figure 6b, since only 2M standby SMs are available in Mode 2. The pre- and post-switching from Mode 2 to Mode 3 are shown in Figure 6c,d. A similar case occurs around the switching moment. Importantly, while switching to Mode 3, 2M SMs are lacking in the equivalent upper arm in Figure 6d, compared with Figure 6c.

If 3M SMs in the MA1 malfunction, the operation is shown in Figure 7. As shown in Figure 7a, 3M standby SMs in the equivalent upper arm can also the ensure the high-quality operation of an AM-MMC after faults. When Mode 1 switches to Mode 2, the fault-tolerant support changes from 3M standby SMs to 2M standby SMs. Accordingly, at the initial operation stage of Mode 2 in Figure 7b, the fault-tolerance measure cannot fully recover the postfault operation to normal level. As shown in Figure 7c, with the reduction in required SMs in the latter operation stage of Mode 2, the faults will not affect the operation of the equivalent upper arm. Moreover, at the moment that Mode 2 has switched to Mode 3, MA1 belongs to the equivalent lower arm and the 3M standby SMs can be provided again.

Based on the above analysis, the conventional fault-tolerance measure cannot handle the operation period around the mode switching. Then, the switching moment reset-based fault-tolerant control is presented in Figure 8. As shown in Figure 8a, the switching moment from Mode 1 to Mode 2 is delayed until the N_on of the equivalent upper arm is 2N/3 − M, rather than 2N/3 in Figure 6a. Thus, the equivalent upper arm does not lack SMs in Figure 8b. It is crucial that the standby SMs in the equivalent lower arm will be launched when the switching moment is reset. As shown in Figure 8c, the switching moment from Mode 2 to Mode 3 is changed at the moment that the N_on of the equivalent upper arm equals N/3 − 2M, instead of N/3 in Figure 6c. Then, the equivalent upper arm in Figure 8d also has enough SMs and no abnormality occurs.

As shown in Figure 7, the main defect occurs around the switching from Mode 1 to Mode 2, namely the initial operation stage of Mode 2. It can also be resolved by the switching moment reset method. The specific reset switching moments for the two types of faults are listed in

Table 4. Switching moments of the proposed fault-tolerant control.

Type		Faults in Upper Arm		Faults in MA1
		M1 to M2	M2 to M3	M1 to M2	M2 to M3
Conventional	Equivalent UA	2N/3	N/3	2N/3	N/3
	Equivalent LA	N/3	2N/3	N/3	2N/3
Proposed	Equivalent UA	2N/3 − M	N/3 − 2M	2N/3 − M	N/3
	Equivalent LA	N/3 + M	2N/3 + 2M	N/3 + M	2N/3

, where M1, M2 and M3 are short for Mode 1, Mode 2 and Mode 3.

With the switching moments marked by the inserted SM numbers shown in Table 4, each arm in the AM-MMC with Type 3 can tolerate 3M faulty SMs. Compared with Table 3, the fault-tolerant capability is effectively enhanced, identically to Type 2. In Table 4, the fault-tolerant cases for the largest fault quantity are shown. To be more general, the switching moment for the other fault quantity can be derived as follows. When the fault quantity h in a single arm lies in [0, M], the switching moments do not need to be reset, because the standby SMs in each arm are sufficient to handle these faults. When h lies in [M, 3M], the switching moment reset is necessary since all the h faults may occur in the same arm. If the arm operates solely, the faults cannot be fully handled by the standby SMs in this arm and the other standby SMs cannot be available. Therefore, when the fault quantity is identical, the case in which faults occur in the same arm is more serious than the case in which faults occur in multiple arms. If the most serious case can be well handled, the operation can also be maintained under other fault cases. Thus, similarly to Table 4, the cases in which all the faults occur in the upper arm and MA1 are discussed.

With the confirmed fault case, the switching moment can be formulated as the function of the actual fault quantity h. The SM quantity at the conventional switching moment is denoted as N_h. In the operation mode that is going to be switched to, the standby SM quantity of the equivalent arm that contains the faulty arm are assumed as M_h. If h is less than M_h, the switching moment does not need to be reset. Otherwise, the switching moment should be reset as N_h + M_h-h. Combining this expression, operation mode and fault message, the specific switching moment can be derived. For example, if the h faults occur in MA1 and M1 is going to switch to M2, the specific switching moment is derived as follows. According to the operation principle of the AM-MMC, N_h can be confirmed as 2N/3 and the equivalent arm that contains the fault (MA1) is the equivalent upper arm, which is composed of an MA and the upper arm. Thus, M_h is 2M. Then, the switching moment is changed from 2N/3 to 2N/3 + 2M-h. If h is equal to 3M, the reset switching moment is consistent with the value listed in Table 4.

In essence, the SM margin can ensure that the equivalent lower arm continues to operate when the conventional switching moment has come. Furthermore, the SM margin offered by the equivalent lower arm equals the SM vacancy by which the faulty SMs exceed the standby SMs in the equivalent upper arm after switching. After the multiplexing arm is removed, the remaining SMs in the equivalent upper arm can also meet the requirement and the SM lacking under conventional method is avoided. Moreover, combining the commutation process analysis in the normal operation, it can be easily derived that the equivalent upper and lower arms with the reset switching moments can also rigorously meet the SM quantity requirement without the participation of the multiplexing arm at the commutation moment. Thus, the multiplexing arm can be temporarily bypassed and the introduced two commutation measures can also be implemented under the switching moment reset method. Then, the selector switches can reliably commutate under the same proposed switching moment reset method as that of normal operation. Furthermore, smooth arm switching can be realized and the premium fault-tolerant operation can be ensured.

5. Simulation Results

To verify the effectiveness of the proposed fault-tolerant scheme, a three-phase AM-MMC model was established in MATLAB/Simulink, and the topology structure and key parameters of this model are shown as Figure 4b and

Table 5. Parameters of the three-phase AM-MMC.

Parameters	Value
SM capacitance C/mF	6.66
Rated SM capacitor voltage Uc0/kV	2
Number of SMs in upper and lower arms N1	68
Number of SMs in multiplexed arms N2	66
Number of standby SMs in each arm M	10
Number of inserted SMs in a phase leg	200
Arm inductance Ls/mH	20
Arm equivalent resistance R0/Ω	1
Voltage of DC side Udc/kV	400
Active power P/MW	400

.

5.1. Normal Operation

The normal operation performances of an AM-MMC with a fault-tolerant structure under the conventional hot-standby operation mode and the proposed alternate launching mode are shown in Figure 9. Differently from the capacitor voltages of the four arms in Figure 9a, these capacitor voltages are inserted with a certain interval in Figure 9b. Moreover, these capacitor voltages have smaller fluctuations than those in Figure 9a. Both the two operation modes can ensure that the AM-MMC has high-quality output currents. The currents are regular and denote the total harmonic distortion (THD) is very low. In terms of circulating currents, the alternate launching method is superior to the conventional method and lower circulating currents are yielded.

Based on Figure 9, the specific indexes are listed. In

Table 6. Comparison of normal operation.

Type	Uc_UA	Uc_MA1	Uc_MA2	Uc_LA	Iabc (THD)	Icir
Conventional	1	1	1	1	1	1
Proposed	0.813	0.746	0.743	0.815	0.755	0.757

, the indexes under the conventional method are used as the base, and the values under the proposed method are the ratios. Except the THD value for output current (I_abc), the ripple amplitudes of the four capacitor voltages (U_{c_UA}, U_{c_MA1}, U_{c_ MA2}, U_{c_LA}) and circulating current (I_cir) peak are shown. Obviously, the proposed method can improve the normal operation of an AM-MMC.

5.2. Fault-Tolerant Operation for SM Faults in the Upper Arm

Figure 10 shows the performances of the conventional hot-standby fault-tolerant method and the proposed switching moment reset method. When 30 SMs malfunction in the upper arm at 0.8 s, both the fault-tolerant methods initiate. Due to the lacking of SMs in the conventional method, the capacitor voltages in the upper arm obviously increase and the voltages in the other three healthy arms are also different from the normal status in Figure 10a. However, the capacitor voltages in the upper arm only have slight rises in the fluctuations in Figure 10b. The voltages in the other arms are as the same as normal. The output currents and circulating currents in Figure 10a are also more serious than those in Figure 10b, which indicates that the switching moment reset can well handle these faults.

As shown in

Table 7. Comparison of fault-tolerant operation for faults in the upper arm.

Type	Uc_UA	Uc_MA1	Uc_MA2	Uc_LA	Iabc (THD)	Icir
Conventional	1	1	1	1	1	1
Proposed	0.897	0.782	0.777	1.134	0.347	0.787

, the capacitor voltage fluctuations in the first three arms under the proposed method are all lower than those under the conventional method. The higher value in the fourth column means the capacitor voltages in the four arms have better balancing properties. Under the proposed fault-tolerant method, both the external and internal indexes of an AM-MMC are high-quality due to the lower THD and I_cir amplitudes.

5.3. Fault-Tolerant Operation for SM Faults in MA1

Figure 11 shows the fault-tolerant performances for 30 faults in MA1 under the conventional hot-standby fault-tolerant method and the proposed switching moment reset method. The two methods also work at 0.8 s. As shown in Figure 11a, the capacitor voltages in the four arms under the conventional method have smaller fluctuation amplitudes, but deviate from the normal condition. Under the proposed method, the capacitor voltages can retain their features as the normal condition in Figure 11b. It is worth noting that the capacitor voltage fluctuations in Figure 11a are still more severe than those in Figure 11b. Moreover, the output currents and circulating currents under the proposed method also present better performances than those under the conventional method. All of the above indicates that this proposed method can effectively recover the postfault operation to the normal level.

As shown in

Table 8. Comparison of fault-tolerant operation for faults in MA1.

Type	Uc_UA	Uc_MA1	Uc_MA2	Uc_LA	Iabc (THD)	Icir
Conventional	1	1	1	1	1	1
Proposed	0.945	0.939	0.94	0.956	0.357	0.762

, all the performance indexes under the proposed fault-tolerant method are lower than those under the conventional fault-tolerant method, which further demonstrates the effectiveness of the proposed switching moment reset method.

5.4. Fault-Tolerant Operation for SM Faults in Multiple Arms

Figure 12 shows the performances of the proposed fault-tolerant scheme for the case that the AM-MMC operates at 0.5 times the rated power and there are 15 faults, 5 faults, 10 faults and 5 faults, respectively, occurring in UA, MA1, MA2 and LA at 0.8 s. Compared with the previous cases, the amplitudes of the indexes in Figure 12 are different since the operation deviates from the rated status. Besides this, all the indexes are at high quality before faults. Moreover, even though multiple faults occur in different arms, the capacitor voltages in each arm, output currents and circulating currents under the proposed fault-tolerant control are almost identical with those in the normal condition. According to that, the operation performance of the AM-MMC can be effectively ensured by the proposed fault-tolerant scheme.

6. Conclusions

This paper proposes a complete fault-tolerant scheme for a new MMC topology: AM-MMC. Firstly, the fault-tolerant topology is confirmed by the structure design in which the standby SMs are evenly distributed in each arm, which contributes to lowering cost and realizing lightweight. Then, the fault-tolerant control methods—SM alternate launching and switching moment reset—are proposed for the operation regulation of the AM-MMC with fault-tolerant structure in normal and postfault conditions. Finally, the effectiveness of the proposed fault-tolerant scheme is tested and compared under three different scenarios. The results show that the proposed fault-tolerant scheme can provide stronger fault-tolerant capability and better operation quality than the conventional fault-tolerant method.