Design and Optimization of a Dynamic Test Platform for Automotive-Grade IGBT Module

Abstract

In the field of dynamic characteristic testing of automotive grade IGBT modules, high-frequency noise interference and stray inductance are universal technical challenges faced by the industry. High frequency noise and stray inductance can interfere with signal integrity, seriously reducing the testing accuracy of the platform and causing deviations in the dynamic characteristic evaluation of IGBT modules. To address this issue, this paper proposes a software hardware collaborative optimization strategy and designs a high-precision dynamic characteristic testing platform for automotive grade IGBT modules. At the software level, Savitzky–Golay filters are introduced and designed to process the test data, filter out high-frequency noise interference. After filtering, the noise mean square error and peak to peak value of the platform are generally reduced by 48–68%, and the switch ringing or peak value is reduced by about 45–53%. In terms of hardware optimization, an improved PCB laminated busbar was designed to reduce the overall stray inductance of the platform through simulation analysis of the structural parameters and via factors of the laminated busbar using ANSYS 2023 R1. The test results verification shows that the stray inductance of the testing platform is only 23 nH. The absolute error between the parameters measured by the testing platform and the reference values of the tested module is within 5%.

1. Introduction

IGBT is one of the core components of power electronics technology, which has the characteristics of high voltage resistance, large output current, high switching frequency, easy driving, and simple control [1,2]. It is widely used in fields such as rail transit, photovoltaic power generation, new energy vehicles, and aerospace [3,4]. Although many new-generation wide-bandgap semiconductor devices outperform IGBTs [5,6,7], IGBTs still possess unique technical merits and remain irreplaceable in medium–low-frequency, high-power applications—especially in the 1–20 kHz switching frequency range [8,9], where their cost-effectiveness is highly competitive. Furthermore, IGBTs exhibit a unique bipolar conduction mechanism and tail-current characteristics. Their switching behavior differs fundamentally from other power devices, necessitating dedicated testing and characterization methods. We aim to fill this research gap and provide practical solutions and reliable evaluation methods for testing the dynamic characteristics of IGBT modules, which is particularly urgent and has important engineering application value in the field of new energy vehicles [10]. In the field of new energy vehicles, the fast switching response and low switching loss of IGBT modules [11] enable highly precise dynamic control during energy conversion, thereby achieving efficient DC–AC inversion [12]. Excellent dynamic stability effectively reduces electromagnetic interference and thermal stress impact [13], ensuring reliable operation of the system under complex working conditions, thereby significantly enhancing the power performance, endurance, and driving safety of new energy vehicles. The field of new energy vehicles is currently the main growth market for power semiconductors [14,15].

Dynamic testing requirements for automotive-grade IGBT modules are more aligned with real-world vehicle operating scenarios, necessitating verification of switching characteristics under harsh conditions such as sudden load changes [16]. This ensures that IGBT modules can operate safely and reliably under frequent dynamic stresses including start–stop operations and vibration [17]. Therefore, it is very important to accurately evaluate the dynamic characteristics of IGBT modules.

However, there will be many problems when building a testing platform to test IGBT modules. For instance, voltage and current probes may introduce high-frequency noise during signal acquisition, which superimposes on useful waveform signals [18], causing severe deviations or large fluctuations in the calculated dynamic characteristic parameters and degrading the test accuracy of the platform [19]. In addition, due to the existence of stray inductance, a significant voltage spike will be induced across the stray inductance by the sudden current change at the turn-off instant, which will subject the device under test to voltage stress exceeding its rated value and threaten the safety of the device [20]. Furthermore, the parasitic inductance also forms an LC resonant circuit together with the parasitic capacitance, which causes severe waveform oscillation [21]. This makes it difficult to capture peak and valley values and compromises the accuracy of test results [22]. To address the aforementioned issues, scholars at home and abroad have conducted relevant studies. Yuan Wenqian [23] et al. established a dynamic characteristic test platform for IGBTs with a horizontal crimping structure. Although the platform can measure the dynamic parameters of IGBTs, it has a relatively high stray inductance, with the extracted stray inductance reaching as high as 110 nH. C. Wang, X [24] et al. constructed a test platform with low stray inductance for IGBT modules by designing laminated busbars and optimizing the calculation method of the current slew rate. The stray inductance of the platform is merely 50 nH. Nevertheless, high-frequency noise caused by sensors was not taken into account, leading to certain glitches in the test waveforms and affecting the test results. C.-R. Huang et al. [25] developed a double-pulse test platform simulation incorporating stray parameters by importing SPICE models into Simulink, and investigated switching loss characteristics under three distinct gate control strategies. They also analyzed the non-uniform current distribution in parallel Si-IGBT modules, which provides a useful reference for minimizing experimental errors. However, this test platform is only designed for testing and verifying devices of specific models, resulting in poor versatility. Xia et al. [26]. conducted calculations and experimental research on stray inductance for PCB dual pulse testing circuits. Based on a three-dimensional simulation model, they analyzed the stray inductance of the testing path and built a testing platform. They also used the dual pulse experimental integration method to verify the simulation results, which showed high consistency. The stray inductance of the testing circuit was only 31.52 nH, but their experimental verification was only carried out under 600 V DC voltage and fixed load conditions, lacking universality verification under different working conditions. In addition, the stray inductance value they measured was the value of the dual pulse testing circuit, not the overall stray inductance of the testing platform. The overall stray inductance of the testing platform would be larger than this value.

To address the problems existing in the above test platforms in the field of dynamic characteristics, this paper designs an improved PCB laminated busbar to reduce the stray inductance of the test platform by conducting simulation analysis on factors such as the structural parameters of the busbar and via holes. Furthermore, a Savitzky–Golay filter is designed and adopted to suppress high-frequency noise, and a high-precision dynamic test platform for automotive-grade IGBT modules is established, which supports a wide voltage range of 50 V to 800 V. Finally, testing and verification are performed on the platform. This paper provides a flexible, accurate and reusable test solution for the dynamic characteristic evaluation of automotive IGBT modules.

2. Design of Dynamic Characteristic Test Platform for IGBT Modules

2.1. Test Principle

The typical on-board three-phase full-bridge topology IGBT module integrates six IGBT chips and six freewheeling diode (FWD) chips [27], which are connected to copper layers through internal bonding wires to form a standard three-phase bridge arm. Each half-bridge outputs U, V, and W three-phase electricity separately. The internal structure diagram of the three-phase full-bridge topology IGBT module is shown in Figure 1. The drive controller controls the switching of the power transistors according to the timing sequence under specific working conditions, chopping the DC power into a series of pulses, which are then filtered to form the three-phase AC power required for driving the motor.

Since the three bridge arms inside the IGBT module are completely symmetrical in terms of material, process and structure, their dynamic characteristics are highly consistent within the same module. Therefore, measuring any one of the bridge arms is sufficient to verify the dynamic characteristics of the IGBT module. The structure of one set of bridge arms of the IGBT is shown in Figure 2. The lower half of the bridge arm is the device under test (DUT), while the upper half is the accompanying IGBT for testing. The bridge arm primarily consists of a base plate, solder layer, copper, direct bonded copper (DBC), and bonding wires [28].

The test schematic diagram designed for this specific structure is shown in Figure 3. U_DC is an adjustable DC power supply responsible for powering the platform. R1 and R2 are charge and discharge resistors, controlling the charging and discharging speed. C_bus represents the bus capacitor. L_stray signifies the stray inductance of the test platform, while L_load denotes the load inductance. The impulsator emits pulses to the gate of the IGBT to control its on/off state. Oscilloscope is used to collect the required voltage and current waveforms.

The circuit testing principle involves applying two time-sequence-controlled pulses to the gate of the IGBT under test to simulate its real-operating state, thereby extracting the dynamic parameters of the IGBT. This method is known as double-pulse testing (DPT). During the first pulse, the IGBT is turned on and causes the load inductance current to linearly rise to a set value; subsequently, when the pulse ends, the IGBT is turned off, and the inductance current freewheels through the anti-parallel diode; immediately following the arrival of the second pulse, the IGBT is turned on again, at which point the freewheeling diode undergoes reverse recovery, generating a transient large current, allowing for precise observation of the voltage and current waveforms during the turn-on and turn-off processes of the IGBT [29,30].

After obtaining the waveforms of gate voltage (Vge), collector voltage (Vce), and collector current (Ic) through an oscilloscope, the dynamic characteristic parameters of the IGBT module are calculated based on the IGBT switching characteristic diagram, as shown in Figure 4. Figure 4a illustrates the turn-on characteristics. The turn-on delay time (td(on)) is the time from when Vge reaches 10% to when Ic rises to 10%. The rise time (tr) is the time for the collector current Ic to rise from 10% to 90%. The turn-on time (ton) is the sum of the turn-on delay time and the rise time. The turn-on loss (Eon) refers to the overlapping area of Vce and Ic during the turn-on process [31]. The calculation method for the turn-off characteristics is similar. Then, the calculated parameters are compared with the values in the IGBT module manual to calculate the absolute error, which is used to evaluate the dynamic characteristics of the IGBT.

2.2. Overall Design of IGBT Dynamic Characteristic Test Platform

2.2.1. Overall Design

The overall design of the IGBT module dynamic characteristic parameter test platform based on the dual-pulse test design is shown in Figure 5. The test platform is mainly composed of three modules: a host computer, a power supply module, and an acquisition module. The host computer controls the power supply module for charging and discharging, controls the pulse generator to issue driving pulses, and stores the waveform information collected by the oscilloscope. The power supply module is used to charge the bus capacitor and maintain the test voltage required by the platform. The acquisition module consists of voltage probes and current probes, which present the collected voltage and current information on the oscilloscope.

Based on the overall architecture outlined above, to ensure accurate and reliable testing of IGBT module dynamic characteristic parameters, the system requires targeted hardware designs for core modules including the gate drive circuit, safety protection, and inductor–capacitor value matching. The gate drive circuit must meet the requirements of fast response and anti-interference performance to accurately control the switching timing of the IGBT. The protection circuit shall be equipped with overvoltage protection to prevent damage to the test platform and IGBT modules caused by abnormal voltage during the test. The matching design of the load inductor and the bus capacitor directly affects the current rise rate and voltage overshoot characteristics in the double-pulse test, which is crucial to ensuring that the test waveforms meet the standard requirements. These three core hardware designs will be elaborated on in detail below.

2.2.2. Design of the Gate Drive Circuit

The control signal originates from the microcontroller unit (MCU). However, the control signal generated by the MCU is insufficient in voltage and current to directly drive the IGBT. Therefore, it is necessary to design an IGBT gate drive module to amplify the output signal of the control module, ensuring the normal turn-on and turn-off of the IGBT. The gate drive circuit design is shown in Figure 6, and the main drive circuit adopts UCC21550 enhanced isolated dual channel driver. This driver features 5 kV RMS enhanced isolation, 125 V/ns common-mode transient immunity, and 8 kV peak transient isolation voltage. It can effectively isolate the high-voltage and low-voltage sides, suppress transient voltage spikes and surge currents caused by high-frequency switching, and prevent false triggering and damage to the control side. Simultaneously possessing low transmission delay characteristics, strong isolation robustness, high anti-interference ability, and efficient driving performance, it is suitable for high-voltage and high-frequency scenarios.

The core innovation of this design lies in the symmetrical gate resistance topology con structed for the upper and lower bridge arms Q1 and Q2. By connecting fast recovery diodes D2 and D3 in series in the turn-off path, dynamic decoupling of the turn-on resistance and turn-off equivalent resistance is realized. This structure allows the rising and falling edge times to be optimized independently. A low-value turn-on resistance accelerates gate charge injection and effectively suppresses turn-on power loss. Meanwhile, the synergistic effect of the diodes and high-value turn-off resistors controllably slows down the gate discharge rate, significantly suppressing parasitic oscillations and switching transient ringing induced by the voltage slew rate. In addition, the input filter capacitor bank C1–C6 adopts a symmetrical layout, which can form balanced impedance paths and minimize the coupling of common-mode noise into the control loop.

2.2.3. Design of the Bus Voltage Protection Circuit

During the testing phase, IGBTs are prone to abnormal voltage due to complex test environments, stray inductance interference, and circuit parameter fluctuations, which may affect sensitive components in the system and distort the accuracy of test results. Therefore, the design of the bus voltage protection circuit is crucial.

The bus voltage protection circuit is shown in Figure 7. The voltage protection circuit designed in this work adopts an overvoltage protection architecture based on cooperative control of a high-precision analog front-end and digital logic. The circuit adopts a two-stage cascaded operational amplifier structure. The first-stage OPA2810 forms a voltage buffer follower, realizing high-impedance isolation of the voltage signal at the ADC acquisition terminal and common-mode noise suppression. The secondary op-amp constitutes an in-phase comparator, which compares the voltage after voltage division regulation with the programmable threshold VSET0 for level judgment. When an overvoltage event is detected, the comparator outputs a low level to trigger the 74HC series logic gate (Y1), generating a stably latched FAULT_OV fault flag. After this signal is captured in real time by the acquisition module, safety actions such as disconnecting the main circuit switch and closing the discharge relay are executed immediately to realize active discharge of the bus capacitor, effectively avoiding the risk of device breakdown.

2.2.4. Matching Design of Load Inductor and Bus Capacitor

In the double-pulse test, the bus capacitor is responsible for maintaining the stability of the DC bus voltage and suppressing voltage overshoot and oscillation, while the load inductor is used to store energy and control the current rise rate in the test loop. With the load inductance fixed, a small capacitance will cause an instantaneous voltage drop across the capacitor, resulting in unstable power supply during the test. If the capacitance is excessively large, the voltage drop across the capacitor will be extremely small, and the load inductor will take a long time to absorb energy, thereby affecting test efficiency. With the capacitance fixed, a large load inductor will require more time for the capacitor to supply energy, leading to increased power loss in the test loop. If the load inductor is too small, the charging pulse duration of the current will be too short and difficult to control during high-voltage testing. Therefore, the matching design of the load inductor and bus capacitor values is of great importance [32].

When testing an IGBT module with a specification of 750 V/820 A under a test voltage of 400 V, the load inductance is calculated. Equation (2) can be derived from Equation (1). This formula describes the basic relationship between the voltage and current change rate at both ends of an inductor, reflecting the physical characteristics of storing magnetic energy and hindering current transients in inductor components.

$$V=L\times {\displaystyle \frac{di}{dt}}$$

(1)

$$L=V\times {\displaystyle \frac{dt}{di}}$$

(2)

where L is the load inductance, V is the bus voltage, and di/dt is the current change rate.

If a test current of 800 A is to be achieved within 20 μs, then

$$L=400\times {\displaystyle \frac{20\times {10}^{-6} \mathrm{s}}{800 \mathrm{A}}}=10\times {10}^{-6} \mathrm{H}=10 \mathrm{\mu }\mathrm{H}$$

(3)

However, during actual testing, pulses with different pulse widths and durations are used, and the current change rate of the test circuit is also different. Based on the actual testing conditions, an inductance of 20 µH is finally selected.

Deriving the constraint formula for inductance and capacitance values, the relationship between the energy released at the capacitor terminal and the voltage drop is as follows [33], This equation is based on the principle of energy conservation and describes the physical law that when the electric field energy stored in a capacitor is converted into inductive magnetic energy during discharge, the capacitor voltage will inevitably decrease:

$${\displaystyle \frac{1}{2}}L{I^2}_{peak}={\displaystyle \frac{1}{2}}{C}_{bus}\left[{\left(U+\Delta U\right)}^2-U^2\right]$$

(4)

where I_peak is the inductor current, C_bus is the capacitance, and ∆U is the bus voltage drop value. The peak voltage of the test circuit can be obtained from Equation (4) as

$$U_{Peak}=U+\Delta U=\sqrt{{\displaystyle \frac{L·{I_{peak}}^2}{C_{bus}}}+U^2}$$

(5)

To protect the device, it is necessary to ensure that the sum of the bus voltage and the voltage variation in the circuit is less than the withstand voltage of the device under test, that is,

$$\sqrt{{\displaystyle \frac{L·{I_{peak}}^2}{C_{bus}}}+U^2}<U_{rating}$$

(6)

where U_rating represents the voltage endurance of the device. Simplifying Equation (6) yields

$${\displaystyle \frac{L}{C_{bus}}}<{\displaystyle \frac{{U^2}_{rating}-U^2}{{I^2}_{peak}}}$$

(7)

In practical measurements, it is stipulated that the peak voltage of the test circuit cannot exceed 80% of the device’s voltage rating, and here we take 0.8U_rating in addition, considering that the bus voltage V has certain fluctuations, a gain K is used to represent this fluctuation, and substituting it into Equation (7) yields

$${\displaystyle \frac{L}{C_{bus}}}<{\displaystyle \frac{{U^2}_{rating}-{(k\times 0.8U_{rating})}^2}{{I^2}_{peak}}}$$

(8)

Simplifying (8) yields

$${\displaystyle \frac{L}{C_{bus}}}<{\displaystyle \frac{(1-0.64k^2)\times {U^2}_{rating}}{{I^2}_{peak}}}$$

(9)

Calculate the bus capacitance using Equation (9), with the voltage fluctuation gain K set to 0.95. Substituting this value into Equation (9) yields a capacitance greater than 2830 µF. Taking into account the margin issue, a capacitance of 3500 µF is ultimately selected.

Through the aforementioned derivation, we obtained the constraint conditions between the circuit impedance characteristic (L/C_bus) and U_rating, I_peak, and the voltage fluctuation gain K. These constraints limit the range of the ratio between L and C_bus ensuring that the circuit can perform dynamic characteristic tests such as dual-pulse testing normally, while satisfying voltage withstand requirements and energy constraints.

3. Optimal Design of the Test Loop

During the process of building the testing platform, it was found that stray inductance could pose certain hazards to the testing platform. Due to the operation of the platform in high-power scenarios, when the device under test (DUT) performs on–off operations, stray inductance will induce voltage spikes based on electromagnetic induction principles, which will have a serious negative impact on the testing accuracy of various related parameters of the DUT. In extreme cases, the spike voltage may even exceed the withstand voltage limit of the DUT, causing device damage [34]. Therefore, it is necessary to reduce the harm caused by stray inductance.

In this paper, a PCB laminated busbar is designed through modeling and simulation to reduce the stray inductance of the test platform. Since a magnetic field is generated when current flows through a conductor, the ratio of the magnetic field to the current is the stray inductance. Inductance is proportional to magnetic flux; the stronger the magnetic field intensity, the higher the stray inductance. The laminated busbar utilizes a compact positive–negative conductive layer structure to form an extremely low-inductance current loop. When high-frequency switching current flows in opposite directions in the parallel positive and negative layers, according to the right-hand rule, the magnetic fields generated by the positive and negative plates are in opposite directions and thus cancel each other out. This greatly weakens the total magnetic flux enclosed by the loop, thereby effectively reducing the stray inductance of the test platform [35].

3.1. Structure Analysis of Laminated Busbar

The busbar consists of two conductive layers with a thin insulating layer sandwiched between them, and its structure is shown in Figure 8.

In the figure, l represents the length of the laminated busbar, b is the width, t is the thickness, and a is the distance between the positive and negative plates. The current direction and magnetic field direction are shown in the figure. The magnetic fields generated by the current flowing through the positive and negative plates are in opposite directions and cancel each other out.

The inductance of a busbar is divided into two parts: internal inductance and external inductance. The internal inductance is generated by the magnetic flux inside the busbar and is related to the skin effect and proximity effect of the current, while the external mutual inductance is determined by the magnetic field generated by the current flowing through the busbar in the external space [36]. The expression for the stray inductance of the busbar is

$$L={\displaystyle \frac{u_{0}tl}{12b}}+{\displaystyle \frac{u_{0}l}{\mathrm{\pi }}}\{{\displaystyle \frac{2\mathrm{a}}{b}}{\tan }^{-1}({\displaystyle \frac{b}{2a}})+{\displaystyle \frac{1}{2}}\ln [1+{({\displaystyle \frac{2a}{b}})}^2]\}$$

(10)

where l is the length of the laminated busbar, b is the width, t is the thickness, a is the distance between the positive and negative plates, and u₀ is the permeability of free space for copper plates. Obtain the design concept of the busbar from the derivation formula of the stray inductance of the busbar. When physically designing the busbar, its thickness should be made thinner, its width should be appropriately increased, and its length should be shortened as much as possible. At the same time, it is important to ensure that the spacing between the positive and negative plates is minimized as much as possible. This structural design can maximize the reduction of parasitic inductance of the busbar.

3.2. Simulation Analysis on the Physical Structure of Laminated Busbars

To verify the accuracy of the derived formula for stray inductance of the laminated busbar, ANSYS software is used to simulate and model a typical double-layer planar laminated busbar. The initial structural parameters are as follows: the busbar includes two conductive layers of positive and negative busbars, with a gap of 0.5 mm, length of 500 mm, thickness of 1 mm, width of 300 mm, and excitation current frequency of 1000 Hz. By simulating the actual working state and modifying these parameters, the inductance characteristic parameters under different working conditions are obtained to explore the influence of the physical structure of the busbar on the parasitic inductance. The simulation results are shown in Figure 9.

It can be seen from the simulation results that, except for the increase in width which leads to the decrease of inductance, the increase of other geometric parameters will cause the stray inductance of the busbar to increase. The design concept of the above laminated busbar is verified.

3.3. Laminated Busbar Via-Hole Design

The laminated busbar is a bridge connecting the busbar capacitor and IGBT, which needs to be fixed with bolts to connect the two. It is inevitable to drill holes, which will increase the stray inductance of the laminated busbar, especially in areas with high current density. Extract stray inductance from the via using ANSYS and observe its current density. The simulation diagram is shown in Figure 10. The current density at the via is high and there is a certain amount of eddy current. The extracted stray inductance is 3.86 nH, which is relatively large.

In some cases, it is inevitable to open holes in areas with high current density. Square solder pads can be added to the holes with high current density to increase the contact area with high current, reduce current density and eddy current magnetic field strength, lower stray inductance, and improve heat dissipation efficiency. As shown in Figure 11, the current density around the conductor decreases, and the eddy current magnetic field strength decreases. The extracted stray inductance is 2.69 nH, which is 30.3% lower than that of ordinary vias.

3.4. Overall Simulation Analysis of Laminated Busbar

Based on the analysis of the laminated busbar, the preliminary designed laminated busbar is shown in Figure 12. Since the connection between the busbar and IGBT is the area with the highest current density, three sets of high-frequency filtering capacitors are arranged here to smooth the current and filter out interference. Now simulate the busbar and extract stray parameters. Before simulation, configure the parameters of the laminated busbar, set the simulation area, and add 500 A excitation current. Due to interference, the frequency of the excitation current is not constant, and a sweep frequency needs to be set to simulate changing frequencies. The working current frequency of IGBT is generally in the kHz range, and the influence of stray inductance may breed high-frequency frequencies in the MHz range. Therefore, the sweep frequency is set to 1 kHz-1 MHz. The current density simulation diagram and magnetic field strength simulation diagram of the busbar are shown in Figure 13.

By observing Figure 13a,b, we can observe that the current density of the busbar at the vias and IGBT connection is relatively high, but the overall magnetic field strength of the busbar is relatively low, especially in the part filtered by the filtering capacitor. This is because the upper layer of the busbar only flows positive electricity, and the lower layer only flows negative electricity. The magnetic field generated by the current flowing through the conductor is mostly cancelled out due to the opposite direction, so the overall magnetic field strength of the busbar is very small, and the stray inductance of the test circuit as a whole is also reduced.

The extraction of stray inductance in the busbar was examined via the solution data module in ANSYS, and the results are presented in Figure 14. When the operating frequency is 10 kHz, the stray inductance of the busbar is only 5.47 nH. If the operating current frequency surges to the megahertz level due to interference, the stray inductance of the busbar is only 4.06 nH. Overall, the stray inductance of the busbar itself is very low, and when incorporated into the test circuit, it can effectively reduce the stray inductance of the loop.

4. Test Results and Analysis

Based on the double-pulse test principle and overall platform design scheme described above, the design and fabrication of key models have been completed, and an automotive-grade IGBT module dynamic characteristic test platform has been built, as shown in Figure 15. The platform mainly consists of a bus capacitor, load inductor, programmable power supply, laminated busbar, pulse generator, and oscilloscope.

4.1. Savitzky–Golay Data Denoising Processing

When collecting test voltage and current, the coupling electromagnetic interference caused by the collection probe lead forming a receiving loop, coupled with the limitation of the grounding loop inductance and probe bandwidth, results in obvious high-frequency burrs mixed in the collected signal, greatly affecting the accuracy of the test results. In this paper, a Savitzky–Golay filter is introduced and designed to construct a data preprocessing model. This filter smooths data through local polynomial least-squares fitting. Compared with conventional low-pass filters, it can better suppress noise while maximally preserving key physical features in switching waveforms, such as peak values, rising and falling edges of the switching waveforms, and the accurate positions of switching instants [37,38].

4.1.1. Model Derivation

Assume that the length of the observation window is N = 2M + 1 and the order is P, then the observation window data can be expressed as

$$X={[-M,-M+1\cdots \cdots ,0,M-1,M]}^T$$

(11)

The P-order polynomial model is

$$y(x)=a_0+a_{1}x+a_2{x}^2+\cdots \cdots a_p{x}^p$$

(12)

Since the final desired value is the smoothed value at the center point (x = 0), then

$$y(0)=a_0$$

(13)

Just need to provide the value of a0. Construct a Vandermonde matrix A with dimensions (2M + 1) × (p + 1).

$$A=\left[\begin{array}{ccccc}1& -M& {(-M)}^2& \dots & {(-M)}^P\\ 1& (-M+1)& {(-M+1)}^2& \dots & {(-M+1)}^P\\ ⋮& ⋮& ⋮& \ddots & ⋮\\ 1& 0& 0& \dots & 0\\ ⋮& ⋮& ⋮& \ddots & ⋮\\ 1& M& M^2& \dots & M^P\end{array}\right]$$

(14)

The coefficient vector solution of A is

$$a={(A^{T}A)}^{-1}{A}^{T}y$$

(15)

The smoothed value of the center point is

$$\stackrel{\wedge }{y_0}=a_0=[1,0,0\cdots 0]·a=[1,0,0\cdots 0]{(A^{T}A)}^{-1}{A}^{T}y$$

(16)

The order determines the size of the fitting force. If the order is too low, it will be overly smooth, and if it is too high, it may fit noise. Savitzky–Golay filters use second- or third-order polynomials in dual pulse testing because low-order filters can effectively remove high-frequency noise while maximizing the retention of key physical features of IGBT switch waveforms without introducing excessive smoothing or artificial distortion.

The size of the window determines the number of data points involved in fitting. A larger window will result in a stronger smoothing effect because it takes in more data points for fitting, thereby removing high-frequency noise more clearly. However, it may lead to the loss of signal details and the blurring of rapidly changing edges. Smaller windows, on the other hand, can better preserve the details and rapid changes of the signal, but have weaker suppression effects on high-frequency noise. Therefore, choosing the appropriate window size is key to balancing noise suppression and signal fidelity.

The relationship between the attenuation frequency, order, and window number of Savitzky–Golay filters is shown in the following equation,

$$fc\approx {\displaystyle \frac{(p+1)·fs}{\pi ·m}}$$

(17)

In the formula, fc is the attenuation frequency, which is the frequency at which the filter filters out high-frequency noise; P is the order; M is the number of windows; and fs is the sampling frequency of the oscilloscope, which is taken as 500 MHz/s.

According to Equation (17), calculate the attenuation frequency corresponding to the order and window number of the Savitzky–Golay filter, as shown in the following

Table 1. Savitzky–Golay Filter Attenuation Frequency Parameter Table.

Order	Number of Windows	Attenuation Frequency (MHz)
2	7	68
	9	53
	11	43
	13	37
3	9	70
	11	58
	13	49
	15	42

:

4.1.2. Analysis of Savitzky–Golay Filtering Effect

Before filtering, it is necessary to calculate the bandwidth range of the useful signal to prevent it from being filtered out. The bandwidth of the useful signal can be obtained by the following equation.

$$f_{signal}\approx {\displaystyle \frac{0.35}{tr}}$$

(18)

tr is the rise time of the signal. According to the datasheet of the device under test, the rise time of Ic is 70–100 ns. Substituting it into Equation (18) and calculating it, the bandwidth of the Ic signal is approximately between 3.5 and 5 MHz. Similarly, it can be concluded that the bandwidth of Vce signal is between 4.5 and 7 MHz, and the bandwidth of Vge signal is between 6 and 8.5 MHz.

The frequency of noise is the LC oscillation frequency formed by parasitic inductance and parasitic capacitance. The size of the noise frequency is related to the size of parasitic inductance and parasitic capacitance. The bandwidth of noise is determined by the formula:

$$f_{res}={\displaystyle \frac{1}{2\pi \sqrt{L_{stray}·C_p}}}$$

(19)

Due to the parasitic inductance of the testing platform being at the nH level and the parasitic capacitance being at the nF level. The minimum size of noise frequency is above 10 MHz, while the frequency of useful signal is between 3.5 and 8.5 MHz. Therefore, Savitzky–Golay filter is mainly used to attenuate high-frequency noise signals above 10 MHz.

The collector voltage Vce and collector current Ic are significantly affected by the coupling noise between the voltage and current probe and the transmission line at the switching transient, and contain multiple high-frequency components such as spikes and ringing. Therefore, a third-order polynomial fitting is used to fit Vce and Ic. Among them, the noise frequency of Vce is mainly between 40 and 50 MHz. When the window length is set to 15, the smoothing effect of noise is the best; the noise frequency of Ic is mainly between 40 and 50 MHz, but the transient duration of Ic is relatively narrower. An excessively large window can cause the peak to be suppressed and the edges to be passivated. Therefore, a relatively small window with a window length of 13 is used to achieve the best filtering effect. After introducing the designed Savitzky–Golay filter, the noise reduction ratio of collector voltage Vce at the switch reached 67.5%, and the noise reduction ratio of collector current Ic at the switch reached 69.7%. The noise reduction effect is shown in Figure 16.

The main function of gate driving voltage is to provide sufficient voltage to IGBT, and control the normal on/off of IGBT. The gate voltage is less affected by the voltage driving source and probe link, so the fitting force required for Vge is not strong. After introducing the Savitzky–Golay filter, setting the order of Vge to 2 and the window to 9, the noise reduction ratio of the gate voltage reaches 47.7% at 1.6–3 µs. The noise reduction effect of the gate voltage Vge is shown in Figure 17.

The Savitzky–Golay filter can filter out noise interference while preserving the key dynamic characteristics of IGBT modules to the greatest extent possible, which plays a certain role in improving the accuracy of testing equipment. The overall filtering effect is shown in Figure 18. The quantization table of the noise reduction effect of Savitzky–Golay filter is shown in

Table 2. Savitzky–Golay Filter Performance Quantification Table.

Parameter	Index	Before Filtering	After Filtering	Improvement Effect
Vge	SNR	40 dB	45.7 dB	↑ 5.7 dB
	RMS noise	0.15 v	0.078 v	↓ 48%
	P-P noise	0.45 v	0.21 v	↓ 53%
	Turn-on ringing P-P noise	1.6 v	0.8 v	↓ 50%
	Turn-off ringing P-P noise	1.7 v	0.84 v	↓ 50.6%
	Peak retention rate	15.0 v	15 v	100%
Vce	SNR	41.9 dB	51.5 dB	↑ 9.6 dB
	RMS noise	4.8 v	1.6 v	↓ 66.7%
	P-P noise	22 v	7.5 v	↓ 65.9%
	Turn-on ringing P-P noise	120 v	39 v	↓ 67.5%
	Turn-off ringing P-P noise	155 v	51.2 v	↓ 67%
Ic	SNR	39.2 dB	47.6 dB	↑ 8.4 dB
	RMS noise	3.3 A	1.12 A	↓ 66%
	P-P noise	14.8 A	5.4 A	↓ 63.5%
	Turn-on ringing P-P noise	22 A	6.67 A	↓ 69.7%
	Turn-off ringing P-P noise	30 A	9.5 A	↓ 68.3%
	Slope shaking RMS noise	2.9 A	1.43 A	↓ 50.1%

.

From the overall filtering effect diagram, it can be seen that the burrs of the waveform are greatly reduced after filtering, and the key physical features such as the rising edge, falling edge, and peak point of the waveform are well preserved. After filtering with different orders and windows based on the main active frequencies of Vge, Vce, and Ic that generate noise, the mean square error and peak to peak value of the platform noise are generally reduced by 48–68%, and the switch ringing or peak value is reduced by about 45–53%. The filtered waveform becomes noticeably thinner and the burrs are reduced.

4.2. Test Results and Calculation of Stray Inductance

After the filtering is completed, the platform is tested to verify the results. Select two IGBT modules of 750 V/820 A grade prepared by different manufacturers for double pulse testing. The testing process is carried out at room temperature (25 °C), with a bus voltage V_DC of 400 V, a driving voltage of −10 to + 15 V, and a load inductance of 20 μH. The results of the double pulse test are shown in Figure 19.

Select the double pulse results of IGBT modules manufactured by Manufacturer 1 to calculate the stray inductance of the testing platform, as shown in Figure 19a. At test point 1, use the cursor of the oscilloscope to capture the collector voltage and collector current values of 12.91 µs and 12.94 µs, calculate the current change rate di/dt based on the change in collector current Ic, and then calculate the stray inductance of the point based on the peak value of collector voltage Vce. Using the same method, obtain the stray inductance value of test point 2. Based on the test information of these two points, the overall stray inductance level of the test platform can be obtained. The information of the two test points is shown in

Table 3. Test Points Information.

Test Point	Test Time (µs)	Ic Change Value (A)	di/dt (A/s)	Vce Peak (V)
First pulse on	0.03	158.3	52.76	516
Second pulse on	0.02	162.7	81.35	602.3

.

At the moment of IGBT switching, the current change rate (di/dt) of Ic is extremely large, and the stray inductance Ls in the circuit will resist this current change, generating an induced voltage:

$$V_{Ls}=Ls\times {\displaystyle \frac{di}{dt}}$$

(20)

This induced voltage will be superimposed on the bus voltage V_DC, causing a voltage peak in the collector voltage Vce, also known as Vce peak. From this, the calculation formula for the stray inductance of the test platform can be inferred:

$$Ls={\displaystyle \frac{V_{cepeak}-V_{DC}}{di/dt}}$$

(21)

By substituting the information of the two test points into Equation (21), the stray inductance of test point 1 is calculated to be 21.98 nH, and that of test point 2 is 24.86 nH. The total stray inductance of the test platform circuit designed in this article for connecting PCB laminated busbars is much lower than that of traditional test circuits.

The dynamic characteristic parameters of the module under test are calculated from the waveforms measured by the test platform, and compared with the values in the device datasheet. The comparison results are shown in

Table 4. Comparison Table of Test Results from Manufacturer 1.

Parameter	Datasheet Value	Test Value	Error
Turn-on delay time (td(on))	0.28 μs	0.291 μs	3.93%
Rise time (tr)	0.07 μs	0.072 μs	2.86%
Turn-on time (ton)	0.35 μs	0.363 μs	3.71%
Turn-off delay time (td(on))	0.94 μs	0.986 μs	4.89%
Fall time	0.04 μs	0.042 μs	5%
Turn-off time (toff)	0.98 μs	1.028 μs	4.9%

and

Table 5. Comparison Table of Test Results from Manufacturer 2.

Parameter	Datasheet Value	Test Value	Error
Turn-on delay time (td(on))	0.315 μs	0.329 μs	4.44%
Rise time (tr)	0.108 μs	0.112 μs	3.70%
Turn-on time (ton)	0.423 μs	0.441 μs	4.25%
Turn-off delay time (td(on))	1.063 μs	1.103 μs	3.76%
Fall time	0.85 μs	0.089 μs	4.70%
Turn-off time (toff)	1.148 μs	1.192 μs	3.85%

. The absolute errors between the data measured by the IGBT dynamic characteristic test platform and the datasheet values of the module under test are all within 5%.

4.3. Multi Voltage Testing Verification

In order to verify the dynamic characteristics of IGBT modules under different operating voltages and the measurement accuracy, stability, and dynamic response consistency of the testing platform over a wide voltage range, double pulse tests were conducted on IGBT modules at 300 V, 400 V, and 500 V test voltages, respectively. The test results are shown in Figure 20.

It can be observed from Figure 20a,b that the IGBT gate voltage (Vge) waveforms are almost the same under different test voltages, and the change in test voltage has little effect on the gate voltage. It is found in Figure 20c,d that the higher the test voltage of the collector voltage during the conduction stage, the greater the waveform oscillation of the voltage; During the turn-off phase, the collector voltage waveforms at different test voltages rise almost simultaneously, and the larger the test voltage, the greater the voltage overshoot. Finally, it can be observed from Figure 20e,f that the conduction waveforms of the collector current at different test voltages almost rise at the same time. As the test voltage increases, the rate of change of the current continues to increase, and the peak value of the current also increases. During the turn-off process, the rate of change of the current and the oscillation of the turn-off waveform also continue to increase.

The IGBT dynamic characteristic testing platform can operate stably under different voltage tests, with minimal fluctuations in dynamic parameter test data between voltage points. At the same time, it can accurately and undistorted capture and restore the rapid changes in IGBT module during turn-on and turn-off transients.

5. Conclusions

This article designs an automotive-grade IGBT module dynamic characteristic testing platform based on dual pulse testing. By designing an improved PCB stacked busbar and introducing a Savitzky–Golay filtering system, the harm of high-frequency noise and stray inductance to the testing platform is reduced. The overall stray inductance of the testing platform is reduced to 23 nH. The dynamic characteristic parameters of the IGBT module measured by the proposed test platform exhibit an error of less than 5% relative to the datasheet values, demonstrating high measurement accuracy. The testing platform designed in this article provides a reliable technical means for precise performance evaluation and quality control of on-board IGBT modules. In addition, the low stray inductance bus design method and adaptive filtering strategy proposed in this article have universal reference value for the development of similar testing systems, which helps to promote the improvement of industry testing standards and testing efficiency.

This platform can be directly used for the selection verification and quality evaluation of IGBT modules for automotive specifications, and its high-precision testing capability can provide reliable data support for the optimization design of electric drive systems. Future applications can extend towards functional integration and cutting-edge expansion: on the one hand, integrating thermal characteristics and aging testing functions to achieve full lifecycle assessment of power devices under multiple stress coupling conditions; on the other hand, to adapt to the testing requirements of the new generation of wide bandgap materials such as SiC, GaN, etc., for higher switching frequencies, larger testing voltages and currents, and expand their application in the research and development of next-generation electric drive technologies [39]. By combining intelligent algorithms, automatic analysis of test data and performance degradation prediction can be further achieved, promoting the development of testing systems towards intelligent diagnosis.