A Fast-Locking PLL Using Low-Power Cycle Slippage Compensation and Accumulated Phase Error Correction

Abstract

This article presents a fast-locking phase-locked loop (PLL) that incorporates a low-power extended phase frequency detector (LPEPFD) and a discriminator-aided phase detector (DAPD) to simultaneously address cycle slippage and frequency overshoot issues during frequency and phase acquisition, respectively. Specifically, the proposed LPEPFD introduces a novel finite state machine architecture that extends the linear range of a conventional PFD without requiring a power-hungry counter, thereby eliminating cycle slippage and reducing the time required for frequency acquisition while maintaining switching activity and power consumption comparable to those of the conventional design. Moreover, after frequency convergence, the DAPD quantizes the accumulated phase error, which is corrected by adaptively tuning the programmable delay lines without causing significant frequency overshoot seen in conventional PLLs, resulting in improved settling time. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the proposed fast-locking PLL occupies an area of 0.36 mm² and operates over a frequency range of 2.6 to 3.2 GHz. Experimental results demonstrate a 0.84-μs settling time for a frequency hop from 2.6 to 3.1 GHz. The designed PLL consumes 5.6 mW of power from a supply of 1 V with an integral root-mean-square jitter of 1.27 ps from 1 kHz to 100 MHz.

1. Introduction

Phase-locked loops (PLLs) are indispensable components of frequency synthesizers in diverse systems including microprocessors and wireless communications. Traditional PLLs aim to produce clean output signals with low phase noise, low jitter, and minimal spurious tones; however, many modern applications impose the additional requirement of rapid frequency acquisition. In such scenarios, fast-locking PLLs play a crucial role by minimizing the time required to settle at a new frequency after startup or frequency hopping. This advantageous characteristic significantly improves system latency, channel switching time, and power efficiency, which renders fast-locking PLLs essential in frequency-hopping spread spectrum, dynamic voltage frequency scaling, low-power wake-up, and real-time communication systems [1,2,3,4].

Frequency hopping in a PLL inherently involves frequency and phase acquisition, which are equally critical determinants of fast-locking performance. In practice, these acquisition stages suffer from cycle slippage and frequency overshoot, which present major challenges to the fast-locking objective. The former issue occurs during frequency acquisition due to the nonlinear transfer characteristics between the phase error of the traditional phase frequency detector (PFD) and the average current of the charge pump (CP), which resembles a sawtooth wave as shown in Figure 1 [5,6]. The extension of loop bandwidth can mitigate cycle slipping, but at the cost of elevated in-band phase noise and jitter [7]. Therefore, bandwidth switching has been introduced to break that trade-off. Specifically, a wide loop bandwidth is used during frequency acquisition to accelerate the locking process, and a narrower loop bandwidth is preferred in steady-state condition to optimize the phase noise characteristics [8]. Even so, the bandwidth switching strategy is incapable of completely suppressing cycle slipping. Alternative strategies, including saturated PFD (SPFD) and extended PFD (EPFD), have been developed to address the intrinsic nonlinearity of conventional PFD (CPFD), as shown in Figure 1. To mitigate the sawtooth wave associated with CPFD, an SPFD [9,10,11] was used to realize a constant gain when the phase difference in the input clocks exceeded 2π. However, the SPFD was unable to maintain linearity for arbitrarily large phase differences, which restricts its effectiveness in minimizing acquisition time. EPFD methods were implemented in [12,13,14,15] and successfully linearized the CPFD and eliminated cycle slippage. However, the typical EPFD requires an additional counter that intensively switches multi-bit signals, which consumes extra power and increases circuit complexity.

Another bottleneck in fast-locking PLLs originates from frequency overshoot during the phase acquisition stage, as mentioned earlier. Specifically, when the output frequency approaches the target value in the presence of accumulated phase error, the PLL is incapable of aligning the phase directly and must instead correct it through frequency adjustments. The process forces the loop to fluctuate the frequency around the target frequency to adjust the phase trajectory, thus inherently introducing frequency overshoot and ultimately prolonging the settling time. To mitigate this limitation, recent approaches have dynamically adjusted the phase of the reference clock [16] or reset the frequency divider [17], but those methods are only applicable to all-digital PLLs (ADPLLs). Furthermore, existing approaches typically improve either frequency or phase acquisition speed but rarely address both simultaneously within a single architecture. As a result, achieving a short settling time remains a significant design challenge, which is addressed in this work.

In this article, we propose a fast-locking PLL that integrates a low-power EPFD (LPEPFD) in combination with a discriminator-aided phase detector (DAPD). In contrast to the typical EPFD, the LPEPFD employs an innovative finite state machine (FSM) approach to extend the linear operating range and eliminate cycle slipping. By efficiently managing state transitions to reduce unnecessary switching activity, the proposed LPEPFD enables fast frequency acquisition with a negligible increase in power consumption compared to that of a CPFD. Once the output frequency converges to the target value, the proposed DAPD is activated to quantize the accumulated phase error while the loop filter maintains the control voltage of the voltage-controlled oscillator (VCO). The quantized outputs generated by the DAPD are then applied to programmable delay lines (PDLs) to enable precise phase alignment without disturbing the VCO frequency, thus achieving phase acquisition without a significant frequency overshoot. Compared with prior methods that focus only on improving phase or frequency acquisition separately, the joint implementation of the LPEPFD and DAPD allows the proposed PLL to accelerate both acquisition stages simultaneously, demonstrating a considerable improvement over traditional designs while maintaining low power performance and robust lock behavior.

The remainder of this paper is organized as follows. Section 2 reviews the typical EPFD architecture and its operating principles while illustrating the power consumption overhead and design complexity of counter-based approaches. Section 3 introduces the fast-locking PLL incorporating the proposed LPEPFD and DAPD. The functional mechanism is revealed and supported by analytical derivations and behavioral level simulations to demonstrate the effectiveness of the proposed technique. Section 4 presents the experimental results and concludes this work.

2. Review of Typical EPFDs

In principle, a PLL relies on a PFD to monitor the phase error $∆\theta$ between the reference clock (REF) and the divider clock (DIV) for generating the corresponding CP current $I_{CP}$ to the loop filter. The transfer characteristic of $∆\theta$ and average current $I_{CP}$ in CPFD and CP, as shown in Figure 1, demonstrates that the average current $I_{CP}$ is produced accurately only when the phase error $∆\theta$ is within $\pm 2\mathsf{\pi }$. If $∆\theta$ exceeds that boundary, the CPFD and CP are unable to provide sufficient current to the loop filter, leading to cycle slipping. In other words, this drawback arises due to the missing edges which can be explained by the FSM of a CPFD structure as shown in Figure 2. The FSM consists of three states: the initial, charge, and discharge states. At the initial state $(UP,DN)=\left(\mathrm{0,0}\right)$, a rising REF edge causes a transition to the charge state $(UP,DN)=\left(\mathrm{1,0}\right)$. If a rising DIV edge subsequently occurs, the FSM returns to the initial state. However, if another rising REF edge arrives while the FSM is in the charge state, it has no effect on the FSM and thus constitutes a missing edge. Similarly, a rising edge of DIV in the discharge state is classified as a missing edge. These missing edges reduce the effective CP current to the loop filter, triggering cycle slipping.

To maintain linearity in the presence of missing edges, the EPFD architecture has been introduced. The idea is to count the number of missing edges and generate additional CP currents to compensate for the current shortfall. A typical EPFD, as shown in Figure 3a, employs an $N$-bit counter, an $N$-bit decoder, and additional control logic. The $N$-bit counter is incremented by one for each missing REF edge and decremented by one for each missing DIV edge. The $N$-bit counter generates the output of $BC=\left({BC}_{N-1},{BC}_{N-2},\dots ,{BC}_0\right)$, where the most significant bit (MSB), i.e., ${BC}_{N-1}$, considered as a sign bit, indicates the lead or lag relationship between REF and DIV, and the remaining bits $\left({BC}_{N-2},\dots ,{BC}_0\right)$ represent the number of missing edges. The binary count $BC$ is then decoded by the $N$-bit decoder to generate the control signals $BU$ and $BD$, which corresponds to charge and discharge operations, respectively, of the CP, as $BU=\left(B{U}_{N-2},\dots ,B{U}_0\right)=\left({BC}_{N-2},\dots ,{BC}_0\right)$ if ${BC}_{N-1}=0$ and $BD=\left({BD}_{N-2},\dots ,{BD}_0\right)=\left({BC}_{N-2}^{\prime },\dots ,{BC}_0^{\prime }\right)$, with ${BC}_j^{\prime }$ denoting the two’s complement of ${BC}_j$ if ${BC}_{N-1}=1$. Once frequency and phase acquisition are complete, the PLL stays in the steady-state condition, and the counter returns to $\left({BC}_{N-1},{BC}_{N-2},\dots ,{BC}_0\right)=(\mathrm{0,0},\dots ,0)$.

Despite the effective elimination of missing edges and cycle slipping, the typical EPFD introduces a notable disadvantage to the power consumption overhead. In complementary metal oxide semiconductor (CMOS) circuits, total power consumption comprises both static and dynamic components, and the static portion from leakage current is negligible compared to the dynamic portion, which is proportional to the circuit switching activity [18,19]. Different from the CPFD, which toggles only a single UP or DN upon a rising edge of REF or DIV, the EPFD exhibits intense multi-bit switching activity in the presence of missing edges, especially missing DIV edges. In such cases, the first missing DIV edge causes the counter to initially decrement $BC$ from $(\mathrm{0,0},\dots ,0)$ to $(\mathrm{1,1},\dots ,1)$ followed by decoding $BC$ into a discharge control signal, $BD=(\mathrm{0,0},\dots ,1)$, thus causing significant switching of the $N$-bit counter. Subsequent missing edges induce further switching across certain bits of the counter and decoder, as illustrated in Figure 3b. Due to the intensive switching events, Ref. [13] reported an extra power consumption of 3.39 mW during the frequency acquisition process compared to that in steady-state condition. Moreover, the employment of the $N$-bit counter and $N$-bit decoder complicates the circuit implementation while causing potential data overflow if the bit width is inadequate for the number of missing edges, resulting in major challenges for low-power operation and a wide linear range in PFD implementations.

Those limitations of the traditional EPFD have motivated the development of an alternative EPFD architecture that can suppress cycle slipping while avoiding the counter-based approach, thereby reducing both power consumption and design complexity. As proposed in Section 3, our LPEPFD addresses the challenges of the traditional EPFD by engineering the FSM to achieve linearization with minimal switching activity. In addition, we incorporate a DAPD to correct the accumulated phase error, effectively suppressing frequency overshoot and further shortening the overall locking time of the proposed PLL.

3. The Proposed PLL with Low-Power EPFD and Phase Error Correction DAPD

The overall architecture of the proposed fast-locking PLL is shown in Figure 4, which implements two circuit innovations: an LPEPFD, in conjunction with an extended CP (ECP), and a DAPD that quantizes the accumulated phase error and regulates PDLs accordingly. The LPEPFD effectively prevents cycle slipping with minimal switching activity while the DAPD can correct the accumulated phase error, ensuring both fast frequency acquisition and phase alignment. By combining those techniques, the proposed PLL achieves substantial improvements in both settling time and energy efficiency compared with the conventional counter-based EPFD design. In addition, the PLL architecture incorporates a second-order loop filter including $C_L$ in parallel with $R_S$ and $C_S$ in series, an LC-VCO, a frequency divider with a tunable ratio $M$, and a frequency counter (FC) with control logic to support the function of the proposed idea. The operation of the proposed LPEPFD and DAPD and their coordination with the other components in the designed PLL are discussed in the following section to provide a comprehensive explanation of the overall system behavior.

3.1. Low-Power EPFD (LPEPFD) and ECP

The proposed LPEPFD is designed to overcome the drawbacks of a typical EPFD, particularly the dependence on a counter and a decoder to count and compensate for the missing edges, associated with increased power consumption and design complexity. Instead of employing the counter-based approach, the LPEPFD restructures the FSM to extend the linear operating range of a CPFD. In contrast to the CPFD, which generates a single pair of $UP$ and $DN$ signals, the proposed LPEPFD produces two groups of multi-bit outputs: $U{P}_K=(U_K,\dots ,U_1,U_0)$ and $D{N}_K=\left(D_K,\dots ,D_1,D_0\right)$, where $K$ represents an integer, and $K\ge 0$. The $U{P}_K$ and $D{N}_K$ operations are controlled by the FSM, as illustrated in Figure 5, which consists of an initial state and multiple charge and discharge states indexed by $i=\mathrm{0,1},\dots , K$. To illustrate the operation of the FSM, we assume that the PLL is initially in steady-state condition, and the FSM is in the initial state such that $\left(U_K,\dots ,U_1,U_0\right)=\left(D_K,\dots ,D_1,D_0\right)=\left(0,\dots ,\mathrm{0,0}\right)$. When the divider ratio $M$ changes to a higher value, REF operates at a higher frequency than DIV, resulting in a positive phase error $∆\theta >0$. A rising REF edge causes the FSM to transition from the initial state to the charge-0 state $\left(U_K,\dots ,U_1,U_0\right)=\left(0,\dots ,\mathrm{0,1}\right),\left(D_K,\dots ,D_1,D_0\right)=\left(0,\dots ,\mathrm{0,0}\right)$. If the LPEPFD is in the charge-0 state and experiences a rising DIV edge, the FSM is reversed to the initial state. Otherwise, if another rising REF edge arrives while the FSM is in the charge-0 state, this edge is regarded as a missing edge, as discussed in Section 2. In the proposed LPEPFD, the rising REF edge shifts the FSM to the charge-1 state such that $\left(U_K,\dots ,U_1,U_0\right)=\left(0,\dots ,\mathrm{1,1}\right)$, $\left(D_K,\dots ,D_1,D_0\right)=\left(0,\dots ,\mathrm{0,0}\right)$, indicating that one missing REF edge has been detected. Furthermore, each subsequent rising REF edge advances the FSM to the next charge-$\left(i+1\right)$ state, whereas a rising DIV edge reverses the FSM to charge-$\left(i-1\right)$ state. The corresponding timing diagram illustrating the case of $∆\theta >0$ is shown in Figure 6, with $K=3$ as an example to demonstrate how the FSM addresses the number of missing REF edges in the output of $U{P}_K$.

On the other hand, when the divider ratio $M$ decreases and REF operates at a lower frequency than DIV, i.e., $∆\theta <0$, the FSM will transition between the initial and discharge states, as shown on the left side of Figure 5. In this scenario, each rising DIV edge increments the discharge index, advancing the FSM toward a higher discharge state, and each counterpart rising REF edge drives the FSM back to a lower discharge state toward the initial state. Through this mechanism, the FSM can dynamically respond to every rising edge of REF and DIV and record the missing edges into $U{P}_K$ and $D{N}_K$. These outputs from LPEPFD provide charge and discharge pulses that allow the ECP to adjust the total current $I_{CP}$ directed toward the loop filter. The ECP architecture comprises $(K+1)$ branches, each of which delivers a unit current of $I_{CPu}$; thus, the instantaneous magnitude of $I_{CP}$ is expressed as:

$$I_{CP}={\displaystyle \sum _{i=0}^K}\left(U_i-D_i\right)I_{CPu}.$$

(1)

By employing the proposed LPEPFD and ECP, the characteristic of $I_{CP}$ with respect to $∆\theta$ is linearized from $-2\pi \left(K+1\right)$ to $2\pi \left(K+1\right)$. The linearization advantage can be explained by decomposing $∆\theta$ into discrete intervals of $2\pi$ where each section is assigned to specific multi-bit outputs $U{P}_K$ for $∆\theta >0$ and $D{N}_K$ for $∆\theta <0$. For the former case, when $0<∆\theta <2\pi$, only $U_0$ is active, which generates a charge pulse proportional to $∆\theta$ and adjusts the charge current of ECP to the loop filter. In case of $2\pi <∆\theta <4\pi$ indicating one missing REF edge, $U_0=1$ is maintained to reflect that missing edge, and $U_1$ manages to produce the incremental charge corresponding to the $0<∆\theta <2\pi$ interval. The higher index outputs, i.e., $U_i$ with $i=2,\dots ,K$, continue this process for successive intervals, ensuring that each portion of the phase error contributes accurately to the total charge, thus effectively achieving operation in a wide linear range and eliminating the cycle slipping issue. Figure 7 illustrates the characteristics of $I_{CP}$ with respect to $∆\theta >0$ under $K=$ 3. For negative phase errors $∆\theta <0$, the $D{N}_K$ outputs perform an analogous function, generating discharge pulses in proportion to the negative phase error and maintaining symmetry in the transfer function. As a result, the overall transfer function between $I_{CP}$ and $∆\theta$ can be linearized and expressed as:

$$I_{CP}={\displaystyle \frac{∆\theta }{2\pi }}{I}_{CPu}.$$

(2)

After the PLL achieves steady-state condition, the FSM of the LPEPFD returns to its initial state. Furthermore, a reset functionality is added to the proposed LPEPFD so that at any state of the FSM, a rising edge of the RST signal will reset the FSM to its initial state. This feature is essential to maintain a stable control voltage at the loop filter output, thereby ensuring a stable operating frequency, which is beneficial to suppress the accumulated phase error, as discussed in Section 3.2.

It is worth mentioning that the proposed FSM ensures that only a single bit toggles in response to any missing edge of REF or DIV, thereby minimizing switching activity and lowering power consumption compared with the typical EPFD. In addition, the implementation of the proposed LPEPFD, as shown in Figure 8, following the operation of the revised FSM features a straightforward implementation compared to its counter and decoder counterparts in a typical EPFD. The architecture includes a CPFD for switching the FSM between the initial, charge- and discharge-0 states, cascaded by missing edge compensator (MEC) stages in an identical structure that enables the charge- and discharge-$i$ states for the FSM with $i=\mathrm{1,2}\dots ,K$. Compared with the circuit implementation of a typical EPFD, the proposed approach not only eliminates the counter and decoder, thereby preventing the switching operations associated with overhead power consumption but also simplifies the overall design by using replicas for MEC stages, which enables straightforward scalability of the LPEPFD for a large value of $K$. In the proposed PLL, the number of $K$ depends on the maximum value of $∆\theta$, denoted as $∆{\theta }_{max}$, which can be found by deriving the transfer function of $∆\theta$ and examining its transient behavior during frequency hopping as reported in [20,21]. $∆{\theta }_{max}$ can be calculated as:

$$\begin{gathered} ∆{\theta }_{max}={\displaystyle \frac{\alpha \left(f_{max}-f_{min}\right)}{f_{BW}\times M}} \\ \cong 20\pi \end{gathered}$$

(3)

where $f_{min}$ and $f_{max}$ are the minimum and maximum frequency outputs of the PLL within one frequency hop, respectively. In particular, the proposed PLL assigns $f_{min}$ and $f_{max}$ as 2.6 and 3.2 GHz, respectively with the divider ratio $M=$ 64. In addition, $f_{BW}$ represents a loop bandwidth of 120 kHz, and $\alpha$ represents a fitting factor from 0.7 to 0.8 depending on the damping factor and natural frequency of the design [21]. As a result, the $∆{\theta }_{max}$ is approximately $20\pi$, which results in $K=$ 9 in our PLL.

To show the superiority of the proposed approach, the settling time and power consumption performances of a PLL using the proposed LPEPFD are simulated and compared with those of a PLL using a CPFD and a typical EPFD in case of frequency hopping from 3.2 to 2.7 GHz, as shown in Figure 9. The proposed LPEPFD demonstrates a settling time of 6.3 µs without exhibiting cycle slipping behavior, which significantly restricts the CPFD to a settling time of 18 µs. Despite a settling time comparable to the proposed LPEPFD, the typical EPFD suffers from high dynamic power consumption due to severe switching activity with a peak power consumption of 7.8 mW associated with the counter and decoder as analyzed earlier, yielding an average power consumption of 0.1 mW during the frequency acquisition process. On the other hand, the proposed LPEPFD can maintain comparable switching to that of the CPFD, thus achieving average power consumption of 0.06 mW during both frequency acquisition and steady-state condition, which represents a 40% power consumption reduction compared to a typical EPFD.

3.2. Phase Error Correction DAPD

In addition to the proposed LPEPFD, which effectively suppresses cycle slipping during frequency acquisition, the designed PLL adopts a DAPD that cooperates with PDLs to address the frequency overshoot caused by the accumulated phase error during the phase acquisition, and thus further enhances the settling time performance. During the frequency acquisition process, the FC continuously monitors and compares the VCO frequency to the destination frequency. The design of the FC is based on a previous study [22], which counts the number of rising edges associated with the VCO within one period of two consecutive falling REF edges and compares it with the divider ratio M. As the frequency error approaches zero, an RST signal is activated to reset the LPEPFD, triggering the transition between the frequency acquisition and phase error correction stages. It is worth mentioning that this transition mechanism is inherently robust to noise, jitter, and process variations. Since the FC performs integer edge counting over a full reference period, it is much less sensitive to small timing perturbations. Typical jitter only introduces picosecond-level edge displacement, which generally does not change the integer count unless the edge occurs very close to the counting boundary. Therefore, moderate phase noise has a negligible impact on the transition decision. Moreover, process, voltage and temperature (PVT) variations mainly affect absolute delay and oscillator characteristics gradually rather than causing abrupt counting errors. Since the FC decision is based on accumulated edge counts rather than fine timing margins, the transition remains reliable across PVT conditions. During the phase error correction stage, the control voltage is reserved in the loop filter to maintain a stable frequency, and the accumulated phase error correction is initiated by the EN signal to enable the DAPD, which analyzes the accumulated phase error between REF and DIV to generate a quantized timing representation of the phase discrepancy. Essentially, this operation is analogous to that of a time-to-digital converter (TDC) in an ADPLL, which can be implemented as a delay-line-based TDC structure [23].

To determine the polarity of phase difference, the proposed DAPD implements a CPFD with additional digital logic to generate $LEAD$, $LAG$, and quantized timing code, as shown in Figure 10 [24]. In addition, the proposed DAPD features dual-resolution as coarse and fine modes with quantization timing outputs for each mode, respectively. The coarse and fine delay units are implemented using current-starved architecture [7], providing delay times of ${\tau }_C=$ 625 ps and ${\tau }_F=$ 19.5 ps, respectively. By employing a 32-bit thermometer code, the total delay range of coarse code $(C_{32}^T,\dots ,C_0^T)$ can span approximately one full REF period $T_{REF}$, while the total delay range of fine code $(F_{32}^T,\dots ,F_0^T)$ covers one coarse delay step. This configuration ensures that the DAPD can capture the entire phase difference between REF and DIV while enabling precise phase resolution. The thermometer code outputs from the DAPD are converted into binary format, i.e., $\left(C_5,\dots ,C_0\right)$ and $\left(F_5,\dots ,F_0\right)$, and then fed into the PDLs, which incorporate the structure of a digital-to-time converter (DTC) featuring the coarse and fine modes [25]. As shown in Figure 11a, $\left(C_5,\dots ,C_0\right)$ and $\left(F_5,\dots ,F_0\right)$ are used to regulate a bank of digitally controlled delay elements to correct the accumulated phase error between REF and DIV.

Specifically, the cooperative mechanism between the DAPD and PDLs executes the phase correction in a two-cycle procedure. Initially, the quantization timing outputs from the DAPD, which control the PDLs, are $(C_5,\dots ,C_0)=\left(F_5,\dots ,F_0\right)=(0,\dots ,0)$. We assume that REF and DIV operate at equal frequency and REF exhibits a leading phase compared with DIV. At the first REF cycle of the phase correction procedure, the accumulated phase error is quantized by the DAPD and reflected into $(C_5,\dots ,C_0)$ and $(F_5,\dots ,F_0)$ with $LEAD=$ 1. Then, the system employs the coarse timing code to correct the major portion of the phase error. As illustrated in Figure 11b, depending on the relative phase error between REF and DIV, the correction can be divided into two cases. If the phase error is less than a half REF period $T_{REF}/2$, i.e., $C_5=0$, the PDL delays REF by the amount specified by $(C_4,\dots ,C_0)$. On the other hand, when the phase error is larger than $T_{REF}/2$, i.e., $C_5=1$, DIV is delayed using the two’s complement code of $(C_5,\dots ,C_0)$. As a result, the proposed mechanism of phase correction can cover the full range of phase difference between REF and DIV by employing a delay-line length for the PDLs limited to $T_{REF}/2$, thus reducing the circuit complexity. Once the coarse correction removes the majority of the timing misalignment, the residual phase error is corrected by the fine timing code $(F_5,\dots ,F_0)$ during the second REF cycle. The phase correction operation in fine mode is functionally equivalent to the coarse counterpart. Finally, as the accumulated phase error is corrected significantly and coarse and fine codes converge to zero, the residual phase difference becomes sufficiently negligible to drive the PLL into steady-state lock. It is worth mentioning that the impact of leakage on the control voltage of the VCO during the activation of the RST signal is negligible in this design. In practice, the control voltage droop caused by leakage can be approximated as:

$$∆V={\displaystyle \frac{I_{leak}{T}_{leak}}{C_L}}$$

(4)

with $I_{leak}$ and $T_{leak}$ representing the current and duration of leakage, respectively. For a worst-case $I_{leak}$ on the order of a few nA, a $T_{leak}$ of two REF cycles, and a $C_L$ of 10 pF, the resulting voltage droop is below 1 mV, leading to a negligible frequency deviation during the phase acquisition process.

A behavioral diagram including the frequency and phase acquisition of the proposed PLL during an upward frequency hopping scenario is illustrated in Figure 12, which demonstrates the combination operation of the proposed LPEPFD and DAPD. The designed PLL accomplishes the frequency acquisition process without cycle slipping attributed by the LPEPFD. When the frequency error approaches zero, as detected by the FC, the RST signal is asserted to reset the LPEPFD and reserve the control voltage in the loop filter whereas the DAPD is enabled by the EN signal to initiate the accumulated phase error correction process. The quantization timing outputs from the DAPD, i.e., the coarse and fine codes, are generated as $\left(C_5,\dots ,C_0\right)$ and $\left(F_5,\dots ,F_0\right)$, respectively. The coarse phase correction is first applied by using the coarse timing code to control the PDLs and reduce the phase error to below ${\tau }_C$. The fine timing code is then updated and used to correct the phase error to less than ${\tau }_F$. Once $\left(C_5,\dots ,C_0\right)$ and $\left(F_5,\dots ,F_0\right)$ are all 0s, the EN signal is deactivated to turn the DAPD off, and the LPEPFD is reactivated by releasing the RST signal. At this stage, only a small residual phase error remains between REF and DIV, allowing the CPFD in the LPEPFD to rapidly align the phase error and bring the PLL into steady-state operation. This state is maintained by the loop as long as the REF frequency and the divider ratio $M$ remain unchanged. By leveraging the combined coarse and fine correction mechanism, the proposed DAPD substantially reduces the accumulated phase error by adjusting the PDLs timing. Consequently, the frequency overshoot commonly observed in traditional PLLs is largely suppressed, resulting in improved locking time.

The simulated phase noise of the proposed PLL is shown in Figure 13, where the noise contributions of individual building blocks are independently simulated and propagated to the output through their respective noise transfer functions. The results highlight a fundamental architectural trade-off between settling time and in-band phase noise. When active, the PDL dominates the low-offset phase noise, resulting in −85.3 dBc/Hz at 1 kHz, whereas the out-of-band noise is mainly determined by the VCO, achieving −112 dBc/Hz at 1 MHz. Disabling the DAPD and PDL circuitry improves the low-offset phase noise to −92.5 dBc/Hz at 1kHz but comes at the expense of increased PLL settling time due to unsuppressed frequency overshoot during phase acquisition. Despite these trade-offs, in modern transceivers, phase fluctuations at very low offset frequencies, i.e., <1 kHz, are largely tracked and compensated by the receiver’s carrier recovery and baseband phase-tracking loops [26]. As a result, slow phase noise has significantly less impact on the effective system performance compared with out-of-band phase noise components.

4. Measurement Results

The proposed fast-locking PLL was implemented in 28 nm CMOS technology with a core area of 0.45 $\times$ 0.8 mm², as shown in Figure 14. A signal generator of 50 MHz drives the external clock to the designed PLL for generating an output frequency range from 2.6 to 3.2 GHz. The frequency acquisition behavior of the proposed fast-locking PLL is measured with an oscilloscope and compared to the conventional PLL, as shown in Figure 15, in case of frequency hopping from 2.6 to 3.1 GHz. In this scenario, the phase difference exceeds $2\pi$, and the conventional PLL experiences multiple occurrences of cycle slipping that leads to a poor settling time greater than 15 μs. When the proposed PLL operates with only the LPEPFD enabled and the DAPD disabled, the settling time is improved to 7.2 μs without cycle slipping but still experiences frequency overshoot. With both the LPEPFD and DAPD activated, the proposed PLL achieves a settling time of 0.84 μs without frequency overshoot, highlighting a considerable improvement over the conventional technique. Moreover, various scenarios of upward and downward frequency hopping are illustrated in Figure 16 and Figure 17, respectively. For upward frequency transition from 2.6 GHz to various target frequencies, the proposed PLL achieves settling times ranging from 0.72 to 0.89 µs, as shown in Figure 16. Similarly, for downward hop from 3.2 GHz, the measured settling times range from 0.59 to 0.73 µs, as illustrated in Figure 17. The entire PLL circuit dissipates 5.6 mW from a 1 V voltage supply with a 3-GHz output signal.

In addition, a spectrum analyzer was used to measure the output spectrum of the proposed PLL, as shown in Figure 18, demonstrating a reference spur of −55.24 dBc with an output signal of 3 GHz. Figure 19 shows that the measured phase noise (PN) achieves −110 dBc/Hz at 1 MHz, and the integral root-mean-square (RMS) jitter ${\sigma }_t$ from 1 kHz to 100 MHz is 1.27 ps. Since the LPEPFD behaves identically to a CPFD in steady-state condition, the PN and reference spur performances remain comparable to those of a conventional PLL, thus indicating that the fast-locking enhancements impose no penalty in steady-state performance. Finally, the performances of the proposed PLL are summarized in

Table 1. Performance summary and comparison with other CMOS PLLs.

Parameter	JSSC 2024 [11]	TCASII 2022 [14]	TCASII 2022 [15]	MWTL 2024 [27]	TCASI 2025 [28]	Electronics 2025 [29]	This Work
Technology (nm)	90	40	180	180	28	180	28
Ref. Frequency $f_{REF}$ (MHz)	50	50	75	50	100	25.5	50
PLL Frequency $f_{PLL}$ (GHz)	1~3	2~3	2.1~2.6	1.5~2.56	6~6.9	2.9~3.2	2.6~3.2
Loop Bandwidth $f_{BW}$ (kHz)	12,000	800	200	<10 &	2000	100	120
Settling Time $T_s$ (µs)	0.52	0.6	5.9	6.5	0.62	5	0.84
Settling Cycle $N_{cycle}$ [$T_{REF}$]	26	30	443	325	62	127	40
Power Consumption PDC (mW)	12	4.6	15.4	54.2	4.6	6	5.6
PN @1MHz (dBc/Hz)	−113.4	−92.8	-	−137.9	−121.8	−134	−110
Jitter ${\sigma }_t$ (ps)	1.62	2.99	0.67 #	0.25	0.99	1	1.27
Area (mm2)	0.147	0.08	0.38	1.25	0.15	0.007	0.36
$FO{M}_1$ (dB)	−225	−223.9	−231.7 #	−234.7	−233.5	−232.2	−230.4
$FO{M}_2$ (dB)	−241	−241.6	−247.1 #	−251.8	−251.6	−253.2	−248.5
$FO{M}_3$ (dB)	−196.7	−194.3	−178.8 #	−184.5	−197.6	−190.1	−198

^&: Estimated from PN; ^#: Jitter integrated from 1 kHz to 10 MHz.

and benchmarked with other related works [27,28,29], demonstrating the fast-locking and low-power consumption characteristics of the proposed PLL. Compared with recent studies of fast-locking PLLs, the proposed PLL achieves comparable performance in terms of settling time, jitter, and power consumption. In Table 1, various figures of merit $FO{M}_1$, $FO{M}_2$, and $FO{M}_3$, are used to compare the performance and demonstrate the achievement of our work [30,31]:

$$FO{M}_1=10\log \left[{\left({\displaystyle \frac{{\sigma }_t}{1\mathrm{s}}}\right)}^2\times {\displaystyle \frac{P_{DC}}{1\mathrm{m}\mathrm{W}}}\right]$$

(5)

$${FOM}_2=10\log \left[{\left({\displaystyle \frac{{\sigma }_t}{1\mathrm{s}}}\right)}^2\times {\displaystyle \frac{P_{DC}}{1\mathrm{m}\mathrm{W}}}\times {\displaystyle \frac{f_{REF}}{f_{PLL}}}\right]$$

(6)

$${FOM}_3=10\log \left[{\left({\displaystyle \frac{{\sigma }_t}{1\mathrm{s}}}\right)}^2\times {\displaystyle \frac{P_{DC}}{1\mathrm{m}\mathrm{W}}}\times {\left(N_{cycle}\right)}^2\right].$$

(7)

In $FO{M}_3$, the settling performance in terms of the settling cycle, $N_{cycle}=T_s{f}_{REF}$ with $T_s$ representing the settling time performance and $f_{REF}=$ 50 MHz, is taken into account.

5. Conclusions

This paper has presented a fast-locking PLL that integrates a low-power extended phase frequency detector (LPEPFD) and a discriminator-aided phase detector (DAPD). The proposed LPEPFD addresses the cycle slipping problem in a power-efficient approach by extending the linear range of the conventional PFD without relying on counter-based logic, thereby reducing both switching activity and design complexity. Complementing this, the DAPD uses dual-resolution coarse and fine modes in conjunction with programmable delay lines (PDLs) to correct the accumulated phase error, effectively suppressing frequency overshoot while significantly shortening the lock time. Measurement results confirm that the proposed PLL achieves rapid frequency acquisition, low power consumption, and competitive phase noise performance. Given these characteristics, the proposed PLL is well suited for LTE and 5G-NR wireless communication systems, where fast frequency settling is critical for dynamic resource allocation and carrier reconfiguration, with settling times preferably shorter than the cyclic prefix duration (e.g., 2 μs) [32]. Furthermore, the proposed PLL can be applied to microprocessors utilizing dynamic voltage and frequency scaling, where fast frequency transitions improve power-management efficiency [8].

Building upon the fast-locking and low-power performance, future research can extend the proposed architecture to higher frequency bands through two primary approaches. First, by increasing the feedback divider ratio while maintaining the reference clock frequency, the proposed LPEPFD and DAPD can continue operating at their original speeds, provided that the loop filter is properly adjusted to preserve loop stability. Alternatively, increasing the reference clock frequency while keeping the divider ratio unchanged preserves the original loop dynamics, although it requires recalibration of the internal timing parameters in the phase error correction logic to accommodate the shorter reference periods. In either case, the core frequency and phase acquisition architecture remain structurally intact without requiring fundamental modifications.