Enhanced Charge Pump Architecture with Feedback Supply Selector for Optimized Switching Performance

Abstract

Conventional operational amplifier designs often experience parameter performance issues during the transition between complementary input differential stages, which restricts the full rail-to-rail common mode voltage swing. This paper presents an innovative charge pump architecture featuring a feedback supply selector that optimizes the transition performance. The proposed approach employs a switched-capacitor technique to boost the supply voltage by 1.5 V relative to the input voltage, thereby enabling the use of a single pMOS differential input stage. The novel supply selector dynamically chooses the maximum available voltage between the external supply and the boosted output, ensuring efficient transistor switching and improved biasing. Schematic-level and post-layout simulations in a 250 nm CMOS process validate the design under varied load currents, supply voltages, temperatures, and process corners. Results show a significant reduction in output voltage ripple, with a maximum value of 48 mV achieved post-layout, and enhanced overall efficiency, even under higher load currents. This architecture provides a robust and scalable solution for advanced operational amplifiers, particularly in fields where high performance and stability are critical.

1. Introduction

In contemporary times, electronic devices have become indispensable in daily human activities. From basic computers to highly sophisticated and sensitive applications, such as medical devices, electric vehicles, and essential components in aerospace systems, these devices accompany and facilitate both mental and physical labor. A critical component of these electronic systems is the operational amplifier [1,2,3] (op-amp). These amplifiers receive a relatively small input signal, amplify and process it, and subsequently transmit it through their output (either differential or single-ended) to the next component of the system.

The technological advance and the increasing performance requirements for electronic equipment have led to the undeniable necessity of designing op-amps with enhanced parameters, including offset voltage [4], noise input [5], bandwidth [6], phase margin, and transient response. Compared to bipolar technology, CMOS technology (Complementary Metal-Oxide-Semiconductor) [7] offers several advantages in achieving these improvements, including higher speed, increased gate impedance, and lower manufacturing costs. Consequently, innovative solutions have been devised to refine well-established designs that are presented in the literature, while entirely new, innovative designs have also been developed (e.g., architectures incorporating trimming or chopping techniques).

Another crucial characteristic that IC design engineers must consider is the rail-to-rail common mode swing at the input [8]. This feature ensures that the amplifier operates according to its specified parameters regardless of the common-mode signal and its amplitude. In modern circuits, it is generally desirable for the rail-to-rail common mode swing to function at least 100 mV above or below the circuit’s supply rails.

A commonly used approach to achieve a rail-to-rail common mode swing at the input is employing complementary pMOS–nMOS transistor pairs [9]. In a well-defined common-mode range (−0.1 V to V_DD − V_SG − 2V_OV (where V_OV is the transistor’s overdrive voltage)), the pMOS differential stage operates (as pMOS transistors are preferred for a wider common-mode voltage range due to noise considerations), while in the other range (V_DD − V_SG − 2V_OV V to V_DD + 0.1 V), the nMOS stage becomes active. IC designers also have the option to operate both differential stages simultaneously. However, this approach increases circuit complexity due to the additional circuitry required to maintain a constant transconductance over the entire common-mode voltage range.

New original circuits have been provided to improve the complementary input stages performance. However, these designs introduce a significant drawback: the transition between the two differential stages. In this transition range, the total input transconductance [10] fluctuates significantly, causing a deviation in the amplifier’s parameters and restricting the common-mode voltage range in which the amplifier works as intended. If an electronic system operates within this undesired transition range, the amplifier may fail to process signals correctly, potentially leading to system malfunction.

A more efficient and robust solution to this issue is the charge pump method [11,12] that powers the input stage. By increasing the supply voltage with a defined margin, a single differential pair can be employed to achieve the input’s rail-to-rail swing, thereby eliminating the transition range where circuit parameters are compromised.

This paper presents an innovative charge pump design based on the switched capacitors principle. To maximize circuit efficiency, a state-of-the-art supply selector is implemented and discussed, enabling the switching transistors within the design to be turned on and off effectively.

This design is intended for applications involving general operational amplifiers that require a rail-to-rail input stage with enhanced common-mode voltage performance and a range of input currents suitable for both low-power and high-precision applications.

This article’s format is as follows: Section 2.1 introduces and explains the capacitor’s charge and discharge principle alongside the Dickson charge pump circuit. Section 2.2 explores the proposed charge pump architecture based on the switched capacitor principle. Section 2.3 discusses the low-dropout regulator (LDO) that drives the charge pump input and generates the required voltage. Section 2.4 examines the innovative supply selector circuit design and operation. Section 2.5 presents the final proposed charge pump schematic alongside all the internal blocks which compose it. Section 3 presents the proposed method and the supply selector circuit schematic-level simulations (Section 3.1). Parasitic extraction simulations are performed alongside a comparison to other papers that are recorded in the literature (Section 3.2). Section 4 details the charge pump layout implementation. A conclusion is also stated at the end of this paper.

2. Design and Implementation

This section offers a comprehensive overview of charge pump designs, emphasizing the dynamic behavior of capacitors within these circuits. Additionally, it introduces the basic schematic of the charge pump circuit to be implemented and simulated in this paper, along with an explanation of its operation. For contextual understanding, the Dickson charge pump is also discussed, with particular emphasis on its voltage multiplication mechanism. Furthermore, the Low-Dropout Regulator (LDO), which ensures a stable input supply, and the innovative supply selector circuit, designed to dynamically select the maximum available voltage and optimize the charge pump’s operation under varying conditions, will also be discussed.

2.1. Charge Pump Principle

When a capacitor [13] is charged through a switch, it demonstrates the characteristic behavior of an RC circuit. This section will analyze the charging process, contrasting the ideal case, where the capacitor is connected to a switch without any resistance or inductance, with a more realistic model that accounts for the resistance of the switch, as well as the resistance and inductance inherent to the capacitor, as shown in Figure 1.

The charging process involves the movement of electrons, which creates an electric field within the capacitor.

Figure 2 shows two graphs depicting the behavior of the capacitor’s voltage and current, based on the formulas that define them, which are discussed in this section.

The capacitor charging and discharging process is characterized by an exponential curve governed by the time constant τ, which depends on the resistance R and capacitance C (τ = R × C). In the ideal case, the capacitor should charge instantaneously when a voltage is applied.

In a real capacitor model, the switch resistance (R_SW), series resistance (R), and inductive effect (L) influence the charging and discharging process. The series and switch resistances limit the current flow, reducing the charging rate and extending the time required for the capacitor to reach its final voltage.

The inductive effect (L) opposes rapid current variations, leading to transient oscillations or ringing during switching events. This effect becomes more pronounced at higher frequencies, where it can affect performance. However, these effects are minimal for integrated capacitors and do not significantly influence overall behavior.

Initially, the capacitor is uncharged, with the voltage across it being 0 V and the current through the circuit at its maximum. At this point, the capacitor begins to accumulate charge, and the current is highest because there is no opposing voltage across the capacitor. The initial conditions of the circuit, where R and C are set to unitary values, serve as a simplified model for analyzing the capacitor’s charging process.

As the capacitor begins to charge, the voltage across it increases according to the following formula:

$$\mathrm{V}\left(\mathrm{t}\right)={\mathrm{V}}_0\left(1-{\mathrm{e}}^{-\frac{\mathrm{t}}{\mathrm{R}\mathrm{C}}}\right)$$

(1)

where $\mathrm{V}\left(\mathrm{t}\right)$ is the voltage across the capacitor at time t, ${\mathrm{V}}_0$ is the initial voltage applied, and $\mathrm{R}\mathrm{C}$ is the time constant, with R being the equivalent resistance between the switch resistance R_SW and the capacitor’s series resistance.

Simultaneously, the current through the circuit decreases exponentially, as described by the formula:

$$\mathrm{I}\left(\mathrm{t}\right)={\mathrm{I}}_{0\mathrm{ }}\left({\mathrm{e}}^{-\frac{\mathrm{t}}{\mathrm{R}\mathrm{C}}}\mathrm{ }\right)$$

(2)

where $\mathrm{I}\left(\mathrm{t}\right)$ is the current through the capacitor at time t, ${\mathrm{I}}_0$ represents the initial current flow through the circuit, and can be calculated using Ohm’s Law:

$${\mathrm{I}}_{0\mathrm{ }}={\displaystyle \frac{{\mathrm{V}}_0}{\mathrm{R}}}$$

(3)

When the capacitor is fully charged, the voltage across it equals the supply voltage, and the current decreases to zero. As shown in Figure 2, during the charging process, the time constant τ represents the duration required for the voltage across the capacitor to reach approximately 63% of its final value (V₀). After a period of 5τ, the capacitor is considered to be nearly fully charged, achieving more than 99% of its final voltage.

The charging behavior of capacitors plays a critical role in circuits like charge pumps, where capacitors are used to store and transfer energy to achieve a higher voltage. In such circuits, the capacitor’s charging and discharging cycles are carefully timed and controlled to ensure optimal performance and efficiency.

One of the most well-known charge pump circuits is the Dickson charge pump [14,15,16], illustrated in Figure 3. It features a two-stage circuit consisting of two diodes (D₁ and D₂) and two capacitors (C₁ and C₂). The circuit requires a fixed input voltage, which serves as the base voltage for the multiplication process. Additionally, a clock signal is essential for proper operation, as it controls the charge transfer between stages.

The circuit operates based on the toggling of the clock signal [17]. When the clock is low (0), diode D₁ conducts, allowing the input voltage V_IN to charge capacitor C₁. In an ideal operation, when there is no voltage drop between the diodes and the clock transitions high (1), capacitor C₁ is forced to a potential of 2V_IN. At this stage, D₁ turns off, while D₂ turns on, allowing capacitor C₂ to charge to 2V_IN. As a result, the output voltage reaches twice the input voltage, effectively boosting the input voltage to twice its value. For N stages, the output voltage reaches approximately N × V_IN; thus, through this technique, the input voltage is effectively multiplied, with the final output voltage being directly proportional to the number of stages used in the circuit.

An alternative implementation replaces the diodes with MOS transistors, as shown in Figure 3b. In certain cases, this can reduce voltage transfer losses when the input voltage is high enough. However, at low input voltages, the architecture does not perform as well due to the significant drain-source voltage drop of the transistors. One significant limitation of this scheme is the voltage drop across the diodes (or switches in general), which diminishes the voltage transfer and reduces the overall voltage transfer depending on the number of stages. Thus, the output voltage provided by the charge pump is given by the following formula:

$${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}=\mathrm{N}\times {\mathrm{V}}_{\mathrm{I}\mathrm{N}}-\sum _{\mathrm{k}=1}^{\mathrm{N}}{\mathrm{V}}_{\mathrm{T}}\left(\mathrm{k}\right)$$

(4)

where N is the number of stages and ${\mathrm{V}}_{\mathrm{T}}$ is the threshold voltage of each transistor in every stage.

2.2. Proposed Switched-Capacitor Charge Pump

The proposed schematic for the charge pump circuit, as shown in this paper’s Figure 4a, introduces a significant improvement over the previous design of the Dickson charge pump. Unlike the earlier version, which aimed to double the input voltage, this new design increases the V_DD voltage by 1.5 V, corresponding to the V_IN voltage. This eliminates the need for transistors that could accommodate higher V_DS voltages (>6.5 V for a V_DD = 5 V), which would demand additional metal masks, thus increasing the chip cost and complexity. Also, the non-overlapping principle is used for clock signals clk1 and clk2 (Figure 4b) to toggle between two operational phases, which are detailed below. In this manner, the clocks achieve a higher performance for the charge pump output, as one pair of switches closes before the other one opens, thus assuring signal integrity. For example, the M₂ transistor should close before M₃ opens, to avoid a short between V_DD signal and GND. This is the so-called “break before make” method.

In the first phase, presented in Figure 5a, the clock signal is at a logical “1”. During this phase, switches S₁ and S₂ are closed, allowing capacitor C₁ to charge to the value of V_IN. Meanwhile, switches S₃ and S₄ are open since they are pMOS transistors with a high logic level applied to their gates.

In the second phase, depicted in Figure 5b, when the clock signals are at a logical “0”, switches S₁ and S₂ are open. At this point, the voltage at node A is equal to the sum of the voltage across capacitor C₁ and the V_DD power voltage. This voltage at node A is further transmitted through switch S₄ and is used to charge capacitor C₂. As a result, the output voltage, V_CP, is increased by V_IN relative to V_DD. This solution enables the amplifier to achieve a complete swing of common-mode voltages across a wide range, both below and above the supply voltages, while using only a single pMOS differential input stage.

The clock signals driving the two phases are synchronized but slightly delayed relative to one another, using a non-overlapping circuit. This delay ensures that switches S₁ and S₂ are fully open before the S₃ and S₄ switches are closed. This sequencing prevents any short-circuit path between the supply voltage and ground, thereby avoiding unnecessary power dissipation and ensuring the integrity of the voltage across capacitor C₁. Additionally, if switches S₁ and S₄ are both open at the same time, the voltage at node A would drop below V_IN, preventing capacitor C₁ from charging fully. This would hinder the output voltage, V_CP, from reaching the desired level, keeping it lower than V_DD + V_IN.

2.3. Low-Dropout Regulator (LDO)

LDOs [18,19] are essential components in modern electronics, providing stable output voltages even when the difference between input and output voltages is minimal. These devices operate as DC linear voltage regulators, ensuring reliable performance in sensitive circuits. The LDO schematic used in this paper is illustrated in Figure 6.

The LDO consists of two main components: an error amplifier (M₁–M₂ and M₇–M₈ transistors) and a pass transistor M₉ [20], which work together to regulate voltage levels precisely.

A reference voltage [21] of approximately 1.5 V is available from design. This voltage reference corresponds to the V_IN node in Figure 4, which will be summed to the charge pump output alongside the supply voltage V_DD. A reference voltage, rather than V_DD, was chosen as V_IN to enable the use of symmetric low-voltage transistors, as explained in Section 2.2.

As stated above, the minimum voltage required to be added above V_DD in order to only use one input differential pair is the sum of the gate-source voltage (V_SG) and twice the overdrive voltage (2V_OV), which is approximately 1.3 V. However, due to the influence of switches, capacitors, and the varying load current (ranging from 50 µA to 400 µA), voltage losses can cause the node to drop below the required minimum; thus, the available 1.5 V reference voltage could be insufficient. This drop prevents the operational amplifier from achieving the rail-to-rail input swing. Furthermore, the current capability must be ensured.

To mitigate this issue, the LDO is employed. When a 1.5 V voltage is applied at the input, the LDO boosts the output to 2 V. The pass transistor, M9, is sized appropriately to accommodate load currents between 50 µA and 400 µA. In this manner, the voltage losses can be surpassed and the current capability is ensured. The output voltage is defined by the formula:

$${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}=\left(1+{\displaystyle \frac{{\mathrm{R}}_2}{{\mathrm{R}}_3}}\right){\mathrm{V}}_{\mathrm{R}\mathrm{e}\mathrm{f}}$$

(5)

Using this formula, the resistor values R₂ and R₃ can be calculated to achieve output voltage equal to 2 V. The LDO uses Miller compensation [22] and a nulling resistor. The nulling resistor shifts the pole from the right-hand plane to the left-hand plane, ensuring the amplifier’s stability and performance.

Without the LDO, the charge pump capacitor draws current directly from the reference voltage source during charging, causing voltage fluctuations that may affect circuit stability. Drawing current from the reference voltage causes its value to change, deviating from the precise 1.5 V required. To mitigate this, a buffer can be placed at the reference voltage output. However, while a buffer replicates the voltage, it cannot address the variations fully. Hence, the LDO is preferred to achieve a stable 2 V output. The transistor sizes and the corresponding values of the other components forming the voltage selection circuit are provided in

Table 1. Design parameters for the LDO.

Parameter	Value
(W/L) M1–M2	20/2 µm/µm
(W/L) M3, M4	12/2, 60/2 µm/µm
(W/L) M5, M6	12/2, 60/2 µm/µm
(W/L) M7–M8	40/0.5 µm/µm
(W/L) M9	800/0.5 µm/µm
R1	28.9 kΩ
R2	200 kΩ
R3	600 kΩ
R4	200 kΩ
C1	1.15 pF
I1	1 µA

.

2.4. Innovative Supply Selector Circuit

The innovative circuit that selects the maximum available supply voltage in the system is presented in Figure 7. Its function is to compare the external supply voltage and the voltage generated by the charge pump architecture described in this paper, selecting the highest value.

This ensures that the two transistors, nMOS and pMOS, which connect the reference voltage (V_REF), the supply voltage (V_DD), and the charge pump (V_CP), can be fully turned on or off, thereby maximizing the charge pump’s efficiency, which is based on the coupled capacitors’ principle.

The supply selector circuit principle is explained as follows. Transistors M₁₂ and M₁₃ read the voltage values at the V_DD and V_CP nodes. When the V_CP node has a lower value than V_DD, the M₁₃ transistor’s source is at a higher potential than that of transistor M12, causing the V_SEL node to be pulled down to V_LOW by the nMOS transistor M₉. The Schmitt trigger U₁ converts the analog V_SEL signal into a digital signal (input of the inverter INV₁), ensuring a smooth transition. Consequently, the M₁₈ transistor’s gate is pulled low by inverter INV₁, while the M₁₇ transistor’s gate is pulled high by inverter INV₂. As a result, M₁₈ is turned on, allowing the V_DD signal to be transmitted to the V_MAX output.

Conversely, when the V_CP node has a higher value than V_DD, the M₁₂ transistor’s source is at a higher potential than that of transistor M₁₃, causing the V_SEL node to be pulled up to V_MAX. In this case, the M₁₈ transistor’s gate is pulled high by inverter INV₁, while the M₁₇ transistor’s gate is pulled down by inverter INV₂. As a result, M₁₇ is turned on, allowing the V_CP signal to be transmitted to the V_MAX output.

The transistor pairs M₁–M₂ and all transistors from M₄–M₁₀ represent current mirrors that multiply or demultiply the reference current I₁. The nMOS transistors M₃–M₁₄ act as cascode stages, reducing the current variation through M₂ and M₁₅ with respect to the supply voltage. The nMOS transistors M₁₁ and M₁₆ introduce hysteresis into the circuit. The Zener diode D₁ ensures a maximum voltage difference of 5.15 V between the V_MAX and V_LOW nodes, allowing the proposed architecture to be implemented in a low-voltage technology. The capacitor C₁ smooths out potential variations that may arise. Transistors M₁₄–M₁₅ should be designed appropriately to ensure the necessary current for the proper circuit operation and the diode D₁. The transistor sizes and the corresponding values of the other components forming the voltage selection circuit are provided in

Table 2. Design parameters for supply selector.

Parameter	Value
(W/L) M1–M2, M15	8/4, 96/4 µm/µm
(W/L) M3, M14	12/1, 144/1 µm/µm
(W/L) M4–M5	18/3 µm/µm
(W/L) M6–M7, M10	4/4 µm/µm
(W/L) M8–M9	8/4 µm/µm
(W/L) M11, M16	10/0.5 µm/µm
(W/L) M12–M13	6/3 µm/µm
(W/L) M17–M18	20/0.5 µm/µm
(W/L) M5–M6, M9–M10	480/10, 416/3 µm/µm
(W/L) D1	0.8/5.4 µm/µm
C1	900 fF
I1	1µA

.

2.5. Top-Level View of the Proposed Charge Pump

The final charge pump schematic proposed in this paper is presented in Figure 8, illustrating all the components that constitute the design. The fundamental schematic, previously explained in Section 2.2, is highlighted using a rectangular frame. The error amplifier (AO), along with the feedback resistors R₁ and R₂, forms the low-dropout regulator described in Section 2.3, which provides both the input voltage for the charge pump and current-driving capability. The selector for the highest available voltage, in conjunction with the two level shifters (LVS₁ and LVS₂), ensures the complete switching operation of transistors M1 from M4.

A ring oscillator which is compensated in temperature and supply voltage is employed, generating a 50 MHz clock frequency at room temperature [23]. The oscillator produces two non-overlapping clock signals to maximize the charge pump efficiency. The inverter INV₁ is utilized to bring the two clock signals into phase, as the OSC block (oscillator) generates complementary clock signals. Capacitor C₁ functions as the switching capacitor between the reference voltage and the output, while C₂ represents the charge pump output’s load. M₁ and M₂ transistors dimensions are ${\displaystyle \frac{W}{L}}={\displaystyle \frac{44}{0.5}}{\displaystyle \frac{\mu \mathrm{m}}{\mu \mathrm{m}}}$ and M₃ and M₄ transistors dimensions are ${\displaystyle \frac{W}{L}}={\displaystyle \frac{60}{0.5}}{\displaystyle \frac{\mu \mathrm{m}}{\mu \mathrm{m}}}$.

3. Simulations and Results

This chapter presents and discusses the proposed implemented method results based on circuit analysis. To evaluate the design performance, two types of simulations were conducted: schematic-level simulations (detailed in Section 3.1), which consider only the active and passive devices used in the circuit alongside their intrinsic parasitic effects (C_GS, C_GD, etc.) and parasitic extraction simulations (PEX—detailed in Section 3.2), which also add the parasitic contributions introduced by interconnecting wiring within the circuit.

3.1. Schematic Level Simulations

The schematic-level simulations were carried out using the Cadence Virtuoso design environment, employing a 250 nm CMOS technology node. This technology was selected due to its stability at elevated temperatures—characterized by low leakage currents—as well as its proven reliability in automotive applications over time.

The supply voltage selector circuit performance is illustrated in Figure 9a,b, considering two supply voltages (2 V and 5 V) and four operating temperatures (−40 °C, 25 °C, 125 °C and 150 °C). The maximum value of V_CP is set 1.8 V above the external supply voltage. In the upper section of the figures, the waveforms corresponding to the supply voltage and the charge pump’s output are depicted, while the lower section presents the V_MAX voltage obtained at the selector output. It is important to note that, for the purpose of checking the supply selector’s performance, an ideal voltage source is used in this case for the V_CP signal.

The results indicate that when V_CP is below V_DD, the circuit output follows the external power supply. Conversely, when V_CP exceeds V_DD, the voltage selector output accurately replicates the V_CP’s behavior. Notably, regardless of the ambient temperature, the waveform remains unchanged, with the four graphs corresponding to the different temperatures overlapping perfectly.

The supply selector’s performance is also tested under fast transient input signals, as shown on the right-hand side of Figure 9a,b. Even when V_CP undergoes an abrupt transition from 0 V to V_DD + 1.8 V, the output successfully tracks the corresponding waveform without significant malfunctions. This demonstrates that the proposed model remains viable under all transient conditions.

Process variations can impact the proposed method’s quality. To assess the circuit’s performance under such conditions, slow and fast corner simulations are conducted. The results are presented in Figure 10a for the slow corner and 10b for the fast corner. This analysis focuses solely on the 5 V supply case, as the 2 V scenario exhibits identical behavior. The temperature range considered remains consistent with the typical case. The slow corner combines slow transistors’ turn-on and turn-off capability and a larger parasitic capacitance, due to a lower-than-normal carrier mobility. Accordingly, the fast corner exhibits faster turn-on and turn-off capability and a lower parasitic capacitance, due to a faster-than-normal carrier mobility.

In the slow corner (Figure 10a), the transistor’s threshold voltage shifts to a higher value, demanding a higher voltage to turn the devices on. Conversely, in the fast corner (Figure 10b), the threshold voltage is reduced, leading to a lower turn-on voltage for the transistors. A comparison between the two figures further reveals that process deviation does not impact on the circuit’s functionality. The waveforms corresponding to slow and fast process corners overlap closely, with only minor deviations on the order of a few µV.

Despite the process variations that could occur in the circuit manufacturing development, the supply selector schematic level simulations’ outcome confirms that the proposed technique remains a robust and effective solution for enhancing the switched-capacitor charge pump performance.

Another important charge pump parameter for this architecture that must be studied separately is the reference voltage V_REF, since its value is added at the circuit output together with the supply voltage, thereby yielding the V_CP voltage. The V_REF’s dependency on temperature should be minimized to eliminate potential variations in the circuit’s final output voltage attributable to this parameter. If the reference voltage is to vary either directly or inversely with temperature, the charge pump’s output efficiency could be also affected by this specification (in addition to factors such as the switches’ R_ON resistance in the design, load current, output resistance, charge injection, etc.).

Following the discussion above, Figure 11a illustrates the influence of temperature on the reference voltage V_REF. On the x-axis the temperature domain is represented and on the y-axis the reference voltage values according to different temperatures. It is observed that the voltage reference has a typical curvature with the ambient temperature, with the maximum value reached around room temperature (1.53 V) and a minimum voltage reached at 150 °C (1.5 V). The voltage drift with temperature obtained is $TC=\frac{\Delta VREF}{\Delta T\ast VREF\_NOM}{10}^6=105.26 \frac{\mathrm{p}\mathrm{p}\mathrm{m}}{°\mathrm{C}}$. This is a typical value for first-order temperature compensation. For improved precision, second-order compensation would be necessary; however, this would require additional circuitry and was not the present paper’s objective.

Since Figure 11 shows only a typical simulation, in which device mismatches are not included, a Monte Carlo simulation was conducted using 200 points to account for these discrepancies. The sampling method selected for this paper is “low-discrepancy sequence”, as it covers the interest domain more quickly and evenly than random sampling. The histogram is depicted in Figure 11b for a V_DD = 2 V and a temperature T = 25 °C.

It is observed that the mean value obtained in the Monte Carlo simulation is the same as that in a typical simulation (1.53 V), and the histogram exhibits a Gaussian distribution. Considering the standard deviation (σ = 24.56 mV), the reference voltage minimum and maximum values are V_{REF_MIN} = 1.38 V and V_{REF_MAX} = 1.68 V, respectively, when applying the mean ± 6σ technique for process improvement.

As highlighted in Section 2.4, to maximize the charge pump performance presented in this paper, it is necessary to implement a circuit that selects the maximum voltage available in the circuit. Without this additional block, the nMOS transistor M1 and the pMOS transistor M4 in the final charge pump schematic cannot be completely turned off or on, thereby affecting the circuit’s efficiency.

Figure 12 presents the charge pump output with and without the innovative supply selector circuit that has been implemented and explained above. The external supply voltages studied are 2 V and 5 V, with the temperature set at T = 25 °C. In the supply selector circuit’s absence, the charge pump V_CP output decreases for both supply voltages. In the 2 V supply voltage case, the decrease is significant—approximately 960 mV. In percentage terms, the supply selector’s efficiency on the charge pump is 35.58%.

For a 5 V supply, the output’s voltage difference with and without the supply selector is smaller, only 300 mV. This is since the switching [24] of transistors M₁ and M₄ is better controlled as the supply voltage increases; however, the ripple is much higher in the supply selector’s absence. These results indicate that the transistors’ proper biasing used as switches is essential for enhancing efficiency, and that the innovative supply selector circuit proposed in this work improves the charge pump.

Subsequently, the designed charge pump response as a function of the load current is examined. Four load current values are tested: 50, 100, 200 and 400 µA, with the aim of ensuring an extensive range of biasing currents where the proposed method can be used to power the input stage. The obtained results are illustrated in Figure 13a,b.

In both figures’ upper section, the waveforms corresponding to a 2 V supply voltage are displayed, while the lower section shows the waveforms corresponding to a 5 V supply voltage. The selected temperature in this case is also T = 25 °C.

As the load current increases, the charge pump output voltage decreases: from 3.81 V (for V_DD = 2 V) and 6.84 V (for V_DD = 5 V) at I_LOAD = 50 µA to 3.29 V (for V_DD = 2 V) and 6.54 V (for V_DD = 5 V) at I_LOAD = 400 µA. Although, for a 2 V supply voltage, the drop at the V_CP node is more pronounced (520 mV vs. 300 mV), the 3.29 V value remains sufficient to power the differential stage (the minimum charge pump output node voltage being defined as: V_{CP_MIN} = V_DD + V_TH + 2V_OV = 3 V, in a cascode current mirror case, with an 800 mV typical threshold voltage and a 100 mV saturation voltage).

Additionally, in Figure 13b a zoom has been applied on the x-axis to better understand the waveforms and the ripple behavior. It can be observed that the ripple increases as the load current increases. The implemented charge pump can support a wide range of bias currents for the input differential stage; thus, it is up to the IC designer which parameters to prioritize, depending on what it is required to achieve.

An important charge pump parameter that must be analyzed is the output ripple. Its value depends on the load current, the switches’ on resistance R_ON, and the circuit load capacitance. The simplest method to improve this parameter is to increase the load capacitance; however, the main drawback is the proportional increase in chip area. IC designers seek state-of-the-art solutions to minimize the output ripple as much as possible. In general, a trade-off is reached between the ripple magnitude and other required parameters.

This paper also addresses the output ripple issue, and Figure 14a,b present the results obtained for this parameter at four different temperatures: −40 °C, 25 °C, 125 °C, and 150 °C, and for two supply voltages: V_DD = 2 V and V_DD = 5 V. The load current is set to I_LOAD = 200 µA.

To facilitate a clearer understanding of the obtained results, a zoom-in is performed on the graphs along both the y- and x-axes. It can be observed that the ripple value does not vary significantly with temperature for either supply voltage. The maximum fluctuation occurs at 5 V supply voltage (ΔV_RIPPLE = 4 mV), while for a 2 V supply, the temperature-induced variation is negligible, measuring only 1 mV. The typical ripple values obtained for the designed charge pump are 26 mV (V_DD = 2 V) and 32 mV (V_DD = 5 V). Based on this analysis, an increasing trend in ripple value is observed as the supply voltage increases.

Like the voltage selector analyzed earlier, verifying the charge pump functionality across different process corners is essential to ensure optimal circuit performance under worst-case conditions. Consequently, simulations were conducted for both slow and fast process corners, and the results are illustrated in Figure 15. In this case, the same four temperatures are utilized to analyze the circuit: −40 °C, 25 °C, 125 °C, and 150 °C, with the charge pump load current set to 200 µA.

As shown, the process variations do not significantly impact the designed charge pump output, regardless of ambient temperature or supply voltage. When comparing the results obtained for different process corners at the two supply voltages, the charge pump output variations (ΔV_CP) are as follows: 60 mV (T = −40 °C, 25 °C), 50 mV (T = 150 °C), 40 mV (T = 125 °C), results obtained for V_DD = 2 V. In the 5 V case, the ΔV_CP variation for different process corners is tighter: 60 mV (T = −40 °C), 20 mV (T = 125 °C), 10 mV (T = 25 °C), and 0 mV (T = 150 °C).

The relatively small fluctuations observed in the corner simulations indicate that the designed charge pump remains unaffected by process-induced parameter shifts, maintaining its reliability across all studied conditions (including the most unfavorable ones, where all parameters are shifted in a single direction).

To evaluate and account for the mismatch among the devices that design the charge pump, Monte Carlo simulations were performed with a total of 200 samples. The selected temperature for this analysis is T = 25 °C, using the same load current as in the previous two simulations (I_LOAD = 200 µA). The resulting histograms are presented in Figure 16: (a) for V_DD = 2 V and (b) for V_DD = 5 V. It can be observed that, for the higher supply voltage, the charge pump standard deviation output doubles, increasing from 15.99 mV (V_DD = 2 V) to 33.06 mV (V_DD = 5 V). This outcome is expected, since for the lower supply voltage the added V_REF value above the supply is equal to the supply voltage, thereby limiting the variations induced by the feedback amplifier; in this case, the two-stage op-amp output is biased in the linear region (for any other V_DD value, the pMOS output transistor would operate in subthreshold region).

If we consider the mean ±6σ principle once more, then the minimum output value obtained in 99.999% of cases for the two scenarios studied is 3.5 V (V_DD = 2 V) and 6.51 V (V_DD = 5 V). These values are more than sufficient to power the op-amp’s input differential stage. A summary of the results obtained for an ambient T = 25 °C temperature and both supply voltages is presented in

Table 3. Charge pump results summary at T = 25 °C.

Parameter	VDD = 2 V	VDD = 5 V
Input voltage (V)	2	5
Output voltage (V) (ILOAD = 200 µA)	3.6	6.71
Load capacitance (pF)	160	160
Number of stages	1	1
Clock frequency	50 MHz	50 MHz
Maximum output current	400 µA	400 µA
Output voltage ripple (mV) (ILOAD= 200 µA)	26	32
Output current (no load) (µA)	354.8	628.4

.

3.2. Post-Layout Simulations

Parasitic effects, including wire resistance, vertical capacitance, and coupled capacitance, can significantly impact on the parameters and the charge pump’s overall functionality. To accurately assess the circuit’s performance while accounting for these factors, post-layout simulations are conducted using the parasitic extraction (PEX) method. The R_C_CC model has been employed in this paper. These post-layout simulations provide the most precise results, offering a comprehensive prediction of how the proposed design will behave in silicon.

Figure 17a,b present the results obtained from PEX simulations performed on the designed charge pump for different load current values. The same test conditions described in Section 3.1 are maintained: four load currents (50 µA, 100 µA, 200 µA, and 400 µA), an ambient temperature of T = 25 °C, and two supply voltages, V_DD = 2 V and V_DD = 5 V.

The results show that the output V_CP obtained from PEX is lower under all tested conditions compared to the results illustrated in Figure 13a,b. The primary factor contributing to this efficiency reduction is the metal interconnects’ resistivity, which, in combination with the switches’ R_ON resistance, affects the connections between the low-dropout regulator (LDO), switches, supply voltage, and charge pump output. Additionally, secondary effects such as coupled capacitances and a lower clock frequency obtained after PEX simulations (f = 48.13 MHz) further influence performance degradation.

The lowest efficiency is observed for a 400 µA load current and a 2 V supply voltage. Under these conditions, the obtained output voltage is V_CP = 3.11 V, which is 180 mV lower than the result obtained from the schematic-level simulation. However, this voltage remains above the critical threshold required for the differential input stage’s proper operation (V_{CP_MIN} = V_DD + V_TH + 2V_OV = 3 V); thus, the charge pump delivers an appropriate output voltage, even under high input current conditions.

Next, the ripple at the charge pump output is analyzed based on the PEX simulation results. The test conditions are identical to those described in Figure 14a,b, including four temperature levels (−40 °C, 25 °C, 125 °C, and 150 °C) and two supply voltages (V_DD = 2 V and 5 V). The results are presented in Figure 18a,b.

It is observed that the output ripple is higher compared to the results obtained from schematic-level simulations. This increase is primarily due to the lower clock frequency that was also mentioned above, which allows the capacitor to charge and discharge over a longer period.

Comparatively, at an ambient temperature of 25 °C, the ripple values obtained from PEX simulations are 9 mV and 16 mV higher than those from schematic-level simulations, as shown in Figure 14a,b. Specifically, for V_DD = 2 V, the ripple increases from 26 mV (schematic) to 35 mV (PEX), while for V_DD = 5 V, it rises from 32 mV (schematic) to 48 mV (PEX).

When analyzing the ripple variation with temperature, the change remains quite tight: only ΔV_RIPPLE = 4 mV for a 2 V supply voltage and ΔV_RIPPLE = 5 mV for V_DD = 5 V.

To further increase the confidence in the proposed charge pump architecture results after parasitic extraction, slow and fast corners are also performed. As explained earlier in this paper, these corners represent the worst-case scenario in which the proposed circuit could operate.

Furthermore, the models accompanying the devices used in this work are very precise, being verified after thousands of circuits that were designed with them. The results achieved are illustrated in Figure 19a,b (slow and fast for V_DD = 2 V) and Figure 19c,d (slow and fast for V_DD = 5 V).

Again, as shown in the waveforms above, the process variations after PEX do not substantially impact the designed charge pump output, regardless of ambient temperature or supply voltage. When comparing the results obtained with process variations at the two supply voltages, the charge pump output fluctuations (ΔVCP) are as follows: 80 mV (T = −40 °C), 100 mV (T = 25 °C), 110 mV (T = 125 °C), and 140 mV (T = 150 °C), results obtained for V_DD= 2 V. In the 5 V case, the ΔV_CP variation for different process corners is again tighter: 30 mV (T = −40 °C), 50 mV (T = 25, 125 °C), 10 mV (T = 25 °C), and 20 mV (T = 150 °C).

The results accomplished after parasitic extraction highlight the fact that the proposed charge pump with a novel supply selector circuit that controls the switches’ gates is suitable to bias different op-amp input differential stages, from low-power applications to automotive ones.

A summary of the PEX results obtained in this paper is presented in

Table 4. Charge pump results summary after PEX at T = 25 °C.

Parameter	VDD = 2 V	VDD = 5 V	Schematic Level VDD = 2 V	Schematic Level VDD = 5 V
Input voltage (V)	2	5	2	5
Output voltage (V) (ILOAD = 200 µA)	3.503	6.65	3.6	6.71
Load capacitance (pF)	160	160	160	160
Number of stages	1	1	1	1
Clock frequency	48.12 MHz	48.13 MHz	50 MHz	50 MHz
Maximum output current	400 µA	400 µA	400 µA	400 µA
Output voltage ripple (mV) (ILOAD = 200 µA)	35	48	26	32
Output current (no load) (µA)	352.6	625.1	354.8	628.4

alongside a comparison between these outcomes and the ones obtained at a schematic level simulation.

Table 5. Table of comparison of charge pump circuit with other recent similar works.

Parameter	[25]	[26]	[27]	[28]	This Work
Year	2012	2018	2020	2020	2025
Technology (CMOS)	130 nm	130 nm	65 nm	65 nm	250 nm
Input voltage (V)	N/A	1.2	0.4	0.4	2
Output voltage (V)	10	7.45	1.9	2	3.505
Load capacitance (pF)	1 µF	N/A	160	160	160
Number of stages	N/A	8	4	4	1
Voltage gain per stage	N/A	6.20	1.476	1.49	1.5
Clock frequency	0.1 MHz	N/A	25	4	48.12 MHz
Maximum output current	500 µA	5 mA	N/A	N/A	400 µA
Output voltage ripple (mV) (with ILOAD)	100	73	100	N/A	35
Output current (no load) (µA)	250	N/A	30	12.6	352.6
Power consumption (no load) (µW)	897.6	37250	12	5.04	705.2
Die area (mm2)	2.25	N/A	0.031	0.021	0.35

lists the proposed switched-capacitor charge pump with supply selector architecture performances obtained with parasitic effects (post-layout simulations) compared to other works that are reported in the literature (measurements and simulation results). The selected input voltage is 2 V. The presented circuit shows superior output voltage ripple performance to all the listed works, alongside lower power consumption than [25,26] and the die area is lower than [25]. Also, the proposed design has only one gain stage, and improved voltage gain per stage compared to [27,28]. The load capacitor is also lower than [25] and equal with [27,28].

4. Layout Implementation

This section presents the final layout of the circuit, as illustrated in Figure 20. The layout comprises the circuit blocks discussed earlier in the paper, specifically the relaxation oscillator (A), supply selector (B), charge pump (C, G), and Low-Dropout Regulator (LDO) (D). For these blocks, we aimed to use separate supplies for digital and analog components, connecting at a higher metal layer [29], such as Metal 3. This approach was chosen to enhance performance and reduce interference between the two types of circuits. Compensation capacitors (E, F) were strategically placed at the top and bottom of the layout. The central area was dedicated to digital components, ensuring a compact and efficient design. Compensation capacitors were strategically placed directly above the devices to maintain stability [30]. The area of the circuit without the load capacitor is 575.8 µm × 241.2 µm.

In the case of the charge pump, the switches (C) were positioned on the right side of the circuit to minimize the length of connections to capacitor C1 (G), reducing resistance, as highlighted in Figure 20. These connections were routed on higher metal layers to further decrease the resistance of the wires [31]. Additionally, the digital section of the oscillator was placed near the nMOS and pMOS transistors used for switching, ensuring that clock signal paths were as short as possible to avoid issues in circuit operation. All digital cells were handcrafted, avoiding the use of standard cells. This method allowed for greater control over the layout and performance of each cell, ensuring they met our specific requirements. Figure 21 highlights the final layout of the circuit, with the load capacitor of the charge pump added.

Additionally, we implemented a common centroid matching technique for all devices to ensure uniformity and minimize mismatches. The total area of the circuit is 689.3 µm × 513.5 µm.

5. Conclusions

The proposed charge pump architecture, based on a switched-capacitor mechanism with a dynamic feedback supply selector, represents a significant advancement in analog circuit design. By circumventing the instability issues traditionally encountered during the transition between complementary differential stages, this approach not only achieves a full rail-to-rail common mode swing but also streamlines the circuitry by enabling the use of a single pMOS differential input stage. Comprehensive schematic-level and post-layout simulations validate the circuit’s robustness across a wide range of operating conditions—demonstrating superior performance in terms of voltage ripple, load current, mismatch between devices, and process variability. These promising results suggest that the design could have profound implications for high-performance analog applications, particularly in the automotive and precision instrumentation sectors. Furthermore, the novel integration of the supply selector opens avenues for future research, including scalability into advanced CMOS nodes and integration with emerging mixed-signal systems, ultimately contributing to the evolution of more efficient and reliable analog circuit solutions in next-generation integrated platforms.