Enhanced Charge Pump Architecture with Feedback Supply Selector for Optimized Switching Performance

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The article presents a novel charge pump architecture featuring a feedback-controlled power selector that optimizes transition performance. The proposed architecture employs the switched-capacitor technique to increase the supply voltage by 1.5 V relative to the input voltage, enabling the use of a single differential pMOS input stage. The primary research question addressed in this study concerns a newly proposed architecture aimed at providing a robust and scalable solution for advanced operational amplifiers, particularly in fields where high performance and stability are crucial.

The manuscript's topic revolves around the proposal of a new charge pump architecture based on a switched-capacitor mechanism with a dynamically controlled feedback power selector. For this reason, this study is considered relevant to the field of analog circuit design.

The key novelty of this work lies in the proposal of a new charge pump architecture with a feedback-controlled power selector, which mitigates instability issues that traditionally arise during the transition between complementary differential stages. Furthermore, this approach not only achieves full rail-to-rail common-mode swing but also optimizes circuitry by enabling the use of a single differential pMOS input stage.

In line 128, the variable name I(t) should be corrected, as it must represent the current through the capacitor.

Section 2.1 describes the operating principle of the charge pump. For the real capacitor charging model, the switch resistance (Rsw) and an inductive effect (L) are considered. However, the influence of Rsw and L on the capacitor's charging and discharging behavior is not explained (it is not reflected in Equations 1–3) nor in the graphs of Figure 2.

In line 179, the name of Figure 5 must be corrected (it appears incorrectly as Figure E).

In the paragraph corresponding to lines 204–213, Figure 6 must be referenced somewhere.

The paragraph in lines 161–164 is suggested to be placed before Equation 4, since the threshold voltage of the transistors is mentioned.

In line 270, correct “M1 from M4” (currently says: “M1 and M4”).

The paragraph in lines 313–317 discusses the slow and fast corner conditions; it is recommended to include a detailed explanation of these conditions.

Reference [27] in line 324 must be corrected.

Table 5 presents a comparison between the proposed circuit and other similar works. It is suggested to include additional comparison parameters, such as power consumption (energy) and area.

In general, the methodology employed in this study is considered appropriate, addressing the topic clearly and comprehensibly while supporting the information with reliable and up-to-date sources.

The conclusions and future perspectives are deemed coherent with the subject matter discussed throughout the manuscript.

The references cited throughout the manuscript are considered appropriate and relevant, adequately supporting the discussion, with most of them being recent.

Regarding the figures, it is recommended to enlarge the font size (or change the color) of the voltage values in the graphs of Figures 11a), 12, 13, 14, 15, 17, 18, and 19.

Author Response

Dear Reviewer,

Thank you for your interest and for comments concerning our paper entitled “Enhanced Charge Pump Architecture with Feedback Supply Selector for Optimized Switching Performance”. Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our research. Now, we are submitting the revised version after carefully considering all the comments. We hope that this version will improve the quality of our manuscript.

On behalf of my co-authors, I would like to clarify some of the points brought up. The responses to your observations and suggestions are provided in contrast color and are accompanied by a revised version of the manuscript in final version. We addressed every concern or suggestion individually by providing a detailed answer below it.

Sincerely,

The Authors

[Comment 1] In line 128, the variable name I(t) should be corrected, as it must represent the current through the capacitor.

[Response] Thank you very much for your time in reviewing our manuscript. Your comments are valuable for revising and improving our paper quality. In the revised manuscript, I(t) is now corrected and represent the current through the capacitor.

[Comment 2] Section 2.1 describes the operating principle of the charge pump. For the real capacitor charging model, the switch resistance (Rsw) and an inductive effect (L) are considered. However, the influence of Rsw and L on the capacitor's charging and discharging behavior is not explained (it is not reflected in Equations 1–3) nor in the graphs of Figure 2.

[Response] Thank you so much for your input! The series and switch resistances limit the current flow, reducing the charging rate and extending the time required for the capacitor to reach its final voltage. The inductive effect (L) opposes rapid current variations, leading to transient oscillations or ringing during switching events. This effect becomes more pronounced at higher frequencies, where it can affect performance. However, these effects are minimal for integrated capacitors and do not significantly influence overall behavior. These aspects are also mentioned in the revised manuscript, with Equation 1 further explains the switch resistance and capacitor’s series resistance influence.  

[Comment 3] In line 179, the name of Figure 5 must be corrected (it appears incorrectly as Figure E).

[Response] We are sorry for neglecting this aspect. The name of Figure 5 is corrected in the latest manuscript version.

[Comment 4] In the paragraph corresponding to lines 204–213, Figure 6 must be referenced somewhere.

[Response] Figure 6 is now referenced in the mentioned paragraph.

[Comment 5] The paragraph in lines 161–164 is suggested to be placed before Equation 4, since the threshold voltage of the transistors is mentioned.

[Response] The mentioned paragraph is now placed before Equation 4 in the revised manuscript.

[Comment 6] In line 270, correct “M1 from M4” (currently says: “M1 and M4”).

[Response] M1 from M4 is now modified in the revised manuscript.

[Comment 7] The paragraph in lines 313–317 discusses the slow and fast corner conditions; it is recommended to include a detailed explanation of these conditions.

[Response] We included a detailed explanation for the fast and slow corner conditions in the revised manuscript.

[Comment 8] Reference [27] in line 324 must be corrected.

[Response] Thank you so much for your comment Reference [27] is now corrected in the revised manuscript!

[Comment 9] Table 5 presents a comparison between the proposed circuit and other similar works. It is suggested to include additional comparison parameters, such as power consumption (energy) and area.

[Response] Power consumption and die area are now added as comparison parameters in Table 5.

[Comment 10] Regarding the figures, it is recommended to enlarge the font size (or change the color) of the voltage values in the graphs of Figures 11a), 12, 13, 14, 15, 17, 18, and 19.

[Response] Thank you for your comment! We enlarged as much as possible the font size of the voltage values in the Figures 11 a), 12, 13, 14, 15, 17, 18 and 19 graphs.

We hope that our replies will be appreciated by the Reviewer!

Reviewer 2 Report

Comments and Suggestions for Authors

This manuscript introduces a switched-capacitor charge pump design able to increase the supply voltage by 1.5 V. A modified version of the Dickson charge pump is proposed, with the addition of a supply selector circuit that chooses the highest between the external supply voltage and the boosted supply voltage to be employed as high logic levels for the switches within the charge pump itself. Pre- and post-layout simulations of a system including the charge pump, an LDO, a voltage reference and a clock generator are reported, showing effectiveness of the proposed approach. Although the overall novelty of the approach is moderate, the authors introduced a few interesting points in their design (especially the feedback supply selector, addressing overvoltage problems typically affecting the switches in supply-boosted circuits). The experimental validation is accurate enough. The authors are invited to address the following points before their manuscript can be considered for publication.

1. In my opinion, the very first phrase of the abstract is unclear. Readers would fail to grasp the link between the use of complementary input pairs (which is a very old and well-established practice) and possible instability (?). Please substantially rephrase this statement.
2. There are two typos at page 3, line 111 and page 6, line 179.
3. Concerning techniques needed to stabilize the transconductance of the input stage across wide common-mode input ranges, discussed at page 2, lines 52-60, the authors might cite doi: 10.1109/PRIME58259.2023.10161977 to better substantiate their statement about the need of increased circuit complexity to achieve this functionality.
4. In Sect. 2.1, the authors initially mention the parasitic inductance of the capacitor, but then they do not include it in the calculations and related discussion. It would be probably better to not even mention the inductance, which is most likely negligible for an integrated capacitor.
5. Page 4, line 150: when stating the the Dickson charge pump yields 2Vin the authors should specify that this is the ideal result that would be achieved if there were no voltage drops across the diodes.
6. Concerning Fig. 4, the explanation about the two clocks (clk1 and clk2) is confused. In the text, it is first suggested that they are the same clock signal, while later the non-overlap relation is clarified. Please rephrase this part. Furthermore, it might be useful to graphically represent the non-overlap relation of the two clock signals in Fig. 4.
7. Page 5, lines 169-171: clarity of this statement is not great. Please rephrase this part.
8. Page 6, lines 201-213: it seems to me that this part is also confused, without clear logic development of the discussion. Please rephrase this paragraph to improve its clarity.
9. Page 9, line 286: it is not clear what the authors mean with “intrinsic parasitic devices”. Do they mean parasitic capacitances of the transistors (Cgs, Cgd, etc.)? these parasitic components are usually included in device models provided by the foundry, so they will appear in pre-layout simulations (not only in post-layout). But maybe the authors employed a particular CMOS process with low-accuracy device models. Please clarify this point and modify the text.
10. Throughout the whole article, the target application of this design is not made clear. This could be stated in the introduction.

In Fig. 11, the authors introduce results on a voltage reference that seems to have not been mentioned earlier in the paper. What is the purpose of this? If the authors want to keep these results, they should motivate their usefuleness in the overall discussion and provide details on the employed voltage reference architecture. Furthermore, instead of the reference voltage variation across temperature (delta_Vref), the temperature coefficient is usually employed as performance metric for voltage references, defined as: TC = delta_Vref/(delta_T*Vref_nominal)*1e6 [expressed in ppm/°C]. it is also not really meaningful to show plots of Vref as a function of time (fig. 11a). the authors might plot Vref directly as a function of temperature.

Author Response

Dear Reviewer,

Thank you for your interest and for comments concerning our paper entitled “Enhanced Charge Pump Architecture with Feedback Supply Selector for Optimized Switching Performance”. Those comments are all valuable and very helpful for revising and improving our paper, as well as the important guiding significance to our research. Now, we are submitting the revised version after carefully considering all the comments. We hope that this version will improve the quality of our manuscript.

On behalf of my co-authors, I would like to clarify some of the points brought up. The responses to your observations and suggestions are provided in contrast color and are accompanied by a revised version of the manuscript in final version. We addressed every concern or suggestion individually by providing a detailed answer below it.

Sincerely,

The Authors

[Comment 1] In my opinion, the very first phrase of the abstract is unclear. Readers would fail to grasp the link between the use of complementary input pairs (which is a very old and well-established practice) and possible instability (?). Please substantially rephrase this statement.

[Response] Thank you very much for your time in reviewing our manuscript. Your comments are valuable for revising and improving our paper quality. The statement is revised in the manuscript new version: ,, Conventional operational amplifier designs often experience stability parameters performance issues during the transition between complementary input differential stages, which restricts the full rail-to-rail common mode voltage swing.”

[Comment 2] There are two typos at page 3, line 111 and page 6, line 179.

[Response] We are sorry for neglecting this aspect. Now the typos are corrected.

[Comment 3] Concerning techniques needed to stabilize the transconductance of the input stage across wide common-mode input ranges, discussed at page 2, lines 52-60, the authors might cite doi: 10.1109/PRIME58259.2023.10161977 to better substantiate their statement about the need of increased circuit complexity to achieve this functionality.

[Response] Thank you so much for your input! The paper you suggested is now cited in the latest manuscript version.

[Comment 4] In Sect. 2.1, the authors initially mention the parasitic inductance of the capacitor, but then they do not include it in the calculations and related discussion. It would be probably better to not even mention the inductance, which is most likely negligible for an integrated capacitor.

[Response] You are right! The inductance is negligible for an integrated capacitor, thus it is not mentioned in the latest manuscript.

[Comment 5] Page 4, line 150: when stating the Dickson charge pump yields 2Vin the authors should specify that this is the ideal result that would be achieved if there were no voltage drops across the diodes.

[Response] Thank you so much for this comment. In the revised manuscript, we specified that the results are in ideal operation, when there is no voltage drop between the diodes.

[Comment 6] Concerning Fig. 4, the explanation about the two clocks (clk1 and clk2) is confused. In the text, it is first suggested that they are the same clock signal, while later the non-overlap relation is clarified. Please rephrase this part. Furthermore, it might be useful to graphically represent the non-overlap relation of the two clock signals in Fig. 4.

[Response] You are right! The explanation about the clock signals was confused. In the manuscript newest version, the non-overlap relation is clarified with more details. Also, Figure 4 b) illustrates the clocks’ non-overlapping waveforms.

[Comment 7] Page 5, lines 169-171: clarity of this statement is not great. Please rephrase this part.

[Response] We are sorry for neglecting this aspect. In the new manuscript version, we rephrased the 169-171 lines.

[Comment 8] Page 6, lines 201-213: it seems to me that this part is also confused, without clear logic development of the discussion. Please rephrase this paragraph to improve its clarity.

[Response] Thank you so much for your comment! Lines 201-213 are now rephrased to improve our paper clarity.

[Comment 9] Page 9, line 286: it is not clear what the authors mean with “intrinsic parasitic devices”. Do they mean parasitic capacitances of the transistors (Cgs, Cgd, etc.)? these parasitic components are usually included in device models provided by the foundry, so they will appear in pre-layout simulations (not only in post-layout). But maybe the authors employed a particular CMOS process with low-accuracy device models. Please clarify this point and modify the text.

[Response] Special thanks for your comment and concern. Schematic-level simulations (detailed in Subchapter 3.1), consider only the active and passive devices used in the circuit alongside their intrinsic parasitic effects (CGS, CGD etc.). Parasitic extraction simulations (PEX - detailed in Subchapter 3.2) also adds the parasitic contributions introduced by interconnecting wiring within the circuit. This is also mentioned in the revised manuscript.

[Comment 10] Throughout the whole article, the target application of this design is not made clear. This could be stated in the introduction.

[Response] The target application of this design is stated in the paper’s introduction in the revised manuscript: ,,This design is intended for applications involving general operational amplifiers that require a rail-to-rail input stage with enhanced common-mode voltage performance and a range of input currents suitable for both low-power and high-precision applications.”

[Comment 11] In Fig. 11, the authors introduce results on a voltage reference that seems to have not been mentioned earlier in the paper. What is the purpose of this? If the authors want to keep these results, they should motivate their usefuleness in the overall discussion and provide details on the employed voltage reference architecture. Furthermore, instead of the reference voltage variation across temperature (delta_Vref), the temperature coefficient is usually employed as performance metric for voltage references, defined as: TC = delta_Vref/(delta_T*Vref_nominal)*1e6 [expressed in ppm/°C]. it is also not meaningful to show plots of Vref as a function of time (fig. 11a). the authors might plot Vref directly as a function of temperature.

[Response] This voltage reference corresponds to the VIN node in Figure 4, which will be summed to the charge-pump output alongside the supply voltage VDD. A reference voltage, rather than VDD, was chosen as VIN to enable the use of symmetric low-voltage transistors. This is also clarified in the latest manuscript, in lines 169-171. Details on the employed voltage reference architecture are available in the cited paper 21: C. Stanescu, C. Dinca and R. Iacob, "Soft-start low voltage CMOS LDO," CAS 2013 (International Semiconductor Conference), Sinaia, Romania, 2013, pp. 185-188, doi: 10.1109/SMICND.2013.6688650.

The temperature coefficient is now employed as performance metric for voltage references in the revised manuscript. Also, Vref is now plotted directly as a function of temperature.

We hope that our replies will be appreciated by the Reviewer!

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

The authors addressed all concerns. The paper may now be published.

Comments on the Quality of English Language

N/A