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Article

Three-Channel Fully Integrated Galvanic Isolation Interface in GaN Technology

by
Katia Samperi
1,
Nunzio Spina
2,
Alessandro Castorina
2 and
Giuseppe Palmisano
1,*
1
DIEEI, Università di Catania, I-95125 Catania, Italy
2
STMicroelectronics, I-95121 Catania, Italy
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(7), 1403; https://doi.org/10.3390/electronics14071403
Submission received: 8 January 2025 / Revised: 7 March 2025 / Accepted: 24 March 2025 / Published: 31 March 2025
(This article belongs to the Special Issue Gallium Nitride (GaN)-Based Power Electronic Devices and Systems)
Browse Figures
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Abstract

:
This paper presents a three-channel galvanic isolation interface in GaN technology. Driver, diagnostic, and control channels have been implemented in a two-die integrated system to perform an isolation interface for a high-performance power switching system. Chip-to-chip communication has been used, which is based on planar micro-antennas with on–off keying modulated RF carriers. This approach provides a high isolation rating by properly setting the distance between chips. Various innovation aspects are adopted with respect to previously published works. They mainly involve the receiver robustness thanks to the switched-capacitor bias control, a bidirectional data channel implementation for power section diagnostic, and a duty cycle distortion compensation for accurate PWM signal. Driver and control channels use RF carriers of about 2 GHz and 0.9 GHz and achieve 2 MHz and 0.5 MHz measured pulse width modulation signals, respectively. The bidirectional channel adopts an RF carrier of about 400 MHz and exhibits a maximum measured data rate as high as 10 Mb/s. Thanks to the extensive use of switched-capacitor circuit solutions, well-controlled behavior is achieved against the large process tolerances and temperature drifts of the GaN technology. The isolation interface is supplied at 6 V and occupies a die area of 7.6 mm2 for each chip.

1. Introduction

Gallium Nitride (GaN) High-Electron-Mobility Transistor (HEMT) is a promising technology for next-generation smart power and RF systems thanks to its inherent material properties that give rise to devices with excellent figures of merit [1]. The wide bandgap and high electron mobility of the two-dimensional electron gas (2DEG) at the GaN/AlGaN interface allow transistors with a higher breakdown, faster switching speed, and lower on-resistance than silicon ones [2,3,4,5,6].
In recent years, the GaN technology has been improved, mainly to improve power conversion efficiency, thus achieving more mature technology. In addition, a lot of attention has been paid to low-voltage GaN devices that are mandatory for a fully integrated power system. The integration on the same substrate of low-voltage and high-voltage GaN transistors allows the switching frequency to be further increased. Indeed, the implementation of a driver and power switch in a two-device solution is affected by frequency limitations due to parasitic inductances [7,8,9,10]. Moreover, driver/power switch integration further increases power efficiency and compactness thanks to the high switching frequency mentioned before, which reduces the size of capacitors and inductors in the final power application. Unfortunately, control circuit design in GaN technology is a challenging task mainly due to the lack of p-channel transistors and the wide spread of transistor electrical parameters [11,12,13,14,15]. To overcome these limitations, several research efforts have been addressed to all-GaN design approaches for integrated basic cells, gate drivers, and power switch systems, including the control circuitry [16,17,18,19,20,21,22,23,24,25,26,27,28].
Many power switching systems for different application fields (medical, smart-home systems, electric vehicles, industrial instrumentations, etc.) need galvanic isolation to be compliant with safety and reliability standards [29,30,31]. Among several approaches for galvanic isolation, an effective and low-cost solution for isolation ratings higher than 10 kV is the near-field chip-to-chip communication, which uses integrated micro-antennas and a modulated RF carrier to transmit data through the isolation interface [32,33,34,35,36,37,38,39,40,41,42,43,44].
This paper presents a fully integrated three-channel galvanic isolation interface in a GaN technology, which is based on the chip-to-chip communication approach shown in Figure 1. The overall system is made up of two chips, a controller chip (chip CTR) and a power chip (chip PW). They should be assembled side-by-side in the package lead frames at a proper distance through isolation (DTI) to guarantee the desired galvanic isolation performance. Chip-to-chip wireless communication is achieved using magnetically coupled planar micro-antennas and OOK-modulated RF carriers.
Two works by the authors on galvanic isolation with chip-to-chip and magnetic micro-antennas were recently published [45,46]. In [45], silicon BCD technology is used whereas [46] uses a GaN technology. Although the two system architectures are similar, they greatly differ in the circuit design approaches. The galvanic isolation interface in [46] has two channels, i.e., a driver channel and a power supply control channel. The main challenge in the design of GaN mixed analog/digital integrated circuits is to overcome the strong technology limitations with a robust design approach. For this purpose, further work was carried out by the authors to improve previous circuit solutions, including additional system functionalities. Specifically, more robust and accurate circuits were arranged for the receiver and a duty cycle distortion compensation circuit was added. Moreover, a bidirectional diagnostic channel was implemented since it is important in some high-performance switching systems to guarantee circuit safety and reliable operation.
To increase the robustness of the receiver, the switched-capacitor (SC) approach was properly exploited to improve both offset compensation and amplification approaches. Specifically, a dedicated feedback loop was arranged for the offset compensation, and the traditional differential stage with resistive load was replaced by a high-gain SC amplifier with dynamic biasing. These approaches increased accuracy against process tolerances and temperature bias drift.
The paper is organized as follows. Section 2 deals with the three-channel system architecture. Section 3 presents the improved receiver along with a detailed comparison with the previous one. Section 5 describes measurements, and Section 6 presents the conclusions.

2. System Architecture

The proposed system performs three isolation channels, namely the driver control channel, the power supply control channel, and the diagnostic bidirectional channel, which are shown in Figure 2. The three-channel galvanic isolation interface is thought to be embedded with a driver/power switch in the final application to achieve a high-performance fully integrated GaN power switching system. The interface will be assembled in a system-in-package (SiP) approach, setting a DTI of around 250 µm to achieve an isolation rating of up to 12.5 kV assuming a standard molding compound with a dielectric strength of roughly 50 V/µm [43].
The two chips were fabricated using a 0.5 µm GaN on Si technology by TSMC, which includes enhancement (E) and depletion (D) n-channel transistors, MIM capacitors, and 2DEG resistors. Moreover, a 650 V power transistor is also available, enabling the galvanic isolation interface to be integrated with a power section in future applications.
The driver channel (see Figure 2a) is used to send the PWM signal through the isolation barrier to drive a power switch for a switching power converter. The RF front-end consists of two magnetically coupled planar micro-antennas, a transmitter (TX), and a receiver (RX) [46]. The TX is mainly performed by an LC oscillator that provides the 2 GHz RF carrier modulated by the PWM signal. The adopted modulation is the on–off keying (OOK). Due to the distance between the two chips, the RF signal is strongly attenuated when it reaches the RX input and hence it needs to be amplified before being recovered. The rectifier provides about 6 dB conversion gain and performs the offset compensation that is necessary to guarantee further amplification despite the bias drift due to process tolerances. Finally, a buffer is included, which preserves the channel speed performance despite external load capacitances due to the measurement setup. It can also be exploited in a future application to drive the driver/power switch.
The power supply control channel (see Figure 2b) operates with a 0.9 GHz RF carrier. It performs a voltage-mode feedback control [46] for the dc-dc flyback power converter that provides the isolated power supply for the power chip. Differently from the driver channel, RX and TX of the power supply control channel also include a start-up circuit [47] and a PWM generator [48], respectively.
The bidirectional channel (see Figure 2c) is used to transmit diagnostic data (i.e., digital-coded currents and voltages) for power section safety and reliable operation. It adopts the same architecture used in [45] for the BCD technology but with a different circuit implementation especially for the receiver, as will be discussed below. Each side of the bidirectional channel can be configured as TX or RX in a half-duplex communication scheme between the two chips. The integrated micro-antenna is exploited for the TX oscillator tank and RX input matching network. The enable signals ENTR and E N ¯ TR are properly used to switch the micro-antenna between TX and RX. Equalization capacitors, CC1,2 and CC7,8, were included to compensate for the capacitive mismatch between the LC tank and the RX input network. The RF carrier was set to about 400 MHz. In stand-by conditions, ENTR is set high and low in the chip CTR and PW, which are then configured as the transmitter and receiver, respectively. The coupling capacitors, CC3,4, are connected to the ground and the antenna in chip CTR is being resonated with the equivalent parallel capacitor Ceq = C + 0.5 CC3,4, performing the oscillator tank. At the same time, coupling capacitors, CC7,8, are grounded and the antenna in chip PW is used for the input impedance network of the RX that is on. Therefore, data transmission from chip CTR to chip PW is enabled. When a query coming from the µC is sent from chip CTR to chip PW to start diagnostic data acquisition, a time window is generated on both sides during which data communication in the opposite direction (i.e., from chip PW to CTR) is enabled by setting low ENTR in chip CTR and high ENTR in chip PW, which are then configured as the receiver and transmitter, respectively. After this time window, the diagnostic channel switches to its stand-by condition, i.e., with chip CTR configured as TX and chip PW as RX, ready for another query.

3. Receiver

A simplified block diagram of the receiver (RX) is shown in Figure 3a. It adopts an innovative approach that takes advantage of the SC technique. The receiver is mainly composed of a rectifier, an SC comparator, and a non-inverting bootstrapped buffer. A phase generator performing ϕ1 and ϕ2 is also used, which exploits a locally generated clock signal for the start-up and stand-by conditions and for the recovered PWM signal during the working condition, as described in [46]. Figure 3b shows the clock phase scheme in the working condition. Rectifier offset compensation and comparator dynamic biasing are performed during ϕ1, which is made up of a small duration pulse within the time slot in which the PWM signal is low (see Figure 3b). During ϕ1, the input terminal of the output buffer is connected to the ground thanks to switch QE9 to maintain the low level of the PWM signal at the receiver output. When ϕ1 goes low, ϕ2 switches the receiver in its operative configuration, ready to recover the next incoming PWM signal.
The rectifier exploits a common-source topology based on the input pair, QE1,2, and a resistive load, RL. A current generator, QD1-R3, is used to increase the bias current in QE1,2 while keeping high RL for better gain. The rectifier gives a first gain contribution of about 12 dB, which allows a negative output signal of around 600 mV to be achieved from an RX input signal of about 150 mV, being the TX output as high as 12 V.
Offset compensation at the rectifier output is mandatory for the next comparator operation. It is performed thanks to the feedback loop composed of the differential voltage-shifted buffer (DVSB) in Figure 3c and the rectifier itself used as a gain stage. The loop frequency compensation is easily implemented by exploiting the hold capacitor, CH1, since DVSB is characterized by the only high-impedance node at the rectifier output. Bias currents in DVSB are provided by the current generators, QD1–3-R1–3, using depletion transistors with degeneration.
The signal current in the differential pair, QE1,2, of DVSB is transferred into transistor QE3, thanks to the local feedback achieved by QE3 and QE4, and then mirrored in the rectifier input transistors, QE1,2, in Figure 3a. The final dc loop gain can then be written as
T = g m 1 , 2 · R L
and is equal to the rectifier gain.
The antenna is ac-coupled to the rectifier input thanks to the capacitors, CC, and the bias resistances, R1,2. The inductor central tap is connected to the ground for the driver and control channels, and to VDD for the bidirectional channel. This low-impedance connection increases the rejection of common-mode disturbances.
The rectifier is followed by an SC high-gain amplifier operated as a comparator. It is composed of QE3 and current source QD2-R4, with switches QE7 and QE8 that perform a dynamic biasing during ϕ1 to guarantee robustness to process tolerances and temperature variations. The bias voltage is stored in CH2, whose left terminal is connected to the reference voltage, VREF2, during ϕ1. Since QE3 is biased in the saturation region in ϕ1, the comparator provides high speed during ϕ2.
Assuming the receiver input signal is low at the beginning of the operating phase, ϕ2, a threshold voltage, ∆VT, equal to VREF1 − VREF2 (∆VT = 200 mV) is applied to the SC comparator input, which maintains low the receiver output as long as the PWM signal at the receiver input is low. Therefore, ∆VT performs a hysteresis threshold that guarantees an appropriate noise immunity.
The proposed receiver is greatly improved compared to the previous version shown in Figure 4 [46] in terms of robustness to process tolerances of the GaN technology.
A first problem of the previous receiver concerns the offset compensation circuit. During phase ϕ1, voltage VO1 is stored in the compensation capacitor, CH, thanks to the feedback loop performed by Amp1,2, thus allowing offset-free signal amplification for Amp1. However, the value of VO1 depends on both the mismatches in the cascode current mirror, QE1–5, and the absolute tolerances on the load resistances, R1 and R2. If VO1 approaches VDD, switch QE7 cannot be turned on during ϕ1, thus compromising the offset compensation. Moreover, negative and positive output bias voltage variations also reduce the output swing.
Another drawback correlated to the previous implementation is the accuracy of the rectifier bias current. Current mirrors in the amplifiers were avoided and substituted with more accurate current sources using degenerated depletion transistors. However, the use of a current mirror could not have been avoided in the rectifier. Therefore, the large transistor mismatch in the cascode current mirror, QE1–5, gives rise to a large variation not only in the output bias voltage mentioned before but also in the rectifier transconductance and hence in its gain.
Finally, process tolerances also cause common-mode bias voltage drifts and hence swing limitations in Amp1,2. The amplifiers exploit a differential stage with load resistances. Its differential output is accurate thanks to the differential control feedback for the offset compensation. However, the common-mode output voltage suffers from process tolerances, despite the use of more accurate current sources with depletion transistors instead of current mirrors, as mentioned before. Consequently, a drift of the output bias voltage may occur, which, besides limiting the maximum achievable gain, also leads to a swing reduction at the amplifier output.
All these limitations are overcome with the proposed improved receiver in Figure 3. The first issue on the offset compensation robustness is overcome with the feedback loop around the rectifier, which sets its bias output voltage to the reference voltage, VREF1 (VREF1 = 3 V). Indeed, this bias voltage is stored in the hold capacitor, CH1, during ϕ1 and then maintained at the output during ϕ2. Differently from the previous solution in Figure 4, this guarantees a correct switching operation for QE6 (QE7 in the previous design) regardless of process tolerances. Moreover, the bias current accuracy in the rectifier was also improved since it no longer depends on the current mirror but on the sum of the current imposed by the feedback loop in RL ((VDD − VREF1)/RL) and the current of QD1-R3. This also allows RL and the rectifier bias current to be sized quite freely to increase the rectifier gain, without affecting the output bias voltage accuracy.
The output swing limitation in the amplifiers due to common-mode drifts in the previous receiver is here overcome by substituting the differential stage with the SC comparator that also provides a high gain.
Finally, it is also worth mentioning that ∆VT in this work is accurately defined by the difference of reference voltages, whereas, in the previous receiver in Figure 4, it was set by the difference between VO1 and VO2, which is affected by process tolerances on both R1 and the current mirror, QE1–5.
A schematic of the bootstrapped output buffer is shown in Figure 5. It is made up of two NOT gates with current source load, QD1,2-R1,2, a dual-feed source follower (DFSF), QE,3,4, a diode-connected transistor, QE5, and a bootstrap capacitor, CB [49]. The output buffer was included to drive the large external load capacitance, CL, due to the measurement setup, without significantly degrading the rise and fall times of the output signal. When VIN is low, QE3 is in triode, and capacitor CB is charged through transistor QE5 to VDD − VT. When VIN goes high, QE2 and QE3 are turned off, QD2 goes fast in triode, and the gate-source voltage of QE4 becomes equal to the voltage across CB, which remains constant to around VDD-VT until VIN is high since the charge into CB is frozen, being terminal A floating. Therefore, QE4 drives CL with a high current until it goes into the triode region, with the output voltage, VOUT, reaching VDD.

4. Duty Cycle Distortion Compensator

As far as the transmitter (TX) is concerned, it uses the D-class oscillator described in [46] but also includes an improvement of the PWM signal accuracy thanks to a circuit for the compensation of the duty cycle distortion. This distortion is mainly due to the modulation process induced by the PWM signal in the oscillator, while only a minor contribution comes from the receiver. Specifically, the PWM distortion is mainly caused by the turn-on time of the oscillator, which is much higher than the turn-off time. The duty cycle compensator is shown in Figure 6a. It is composed of a flip-flop, a delay circuit (D), and some gates. The approach is to delay the falling edge of the PWM input signal, VPWM_ID, by an amount equal to the turn-on time of the oscillator. The equalized PWM signal, VPWM_EQ, at the output of the compensator is then used to drive the oscillator. In this way, a nominally accurate correction is achieved. Figure 6b shows VPWM_ID, VPWM_EQ, in which the falling edge was delayed by D, and the modulated RF carrier at the output of the oscillator, without (VRF_WO) and with (VRF_W) duty cycle distortion compensation. Despite the delay, D is not well correlated with the turn-on time of the oscillator, and an effective correction of the duty cycle distortion is achieved. The circuit in Figure 6a is useful for the correction of negative values of the duty cycle distortion as happens in this work. In the case of positive values, a similar solution can be easily arranged.

5. Experimental Results

The galvanic isolation interface was assembled chip-on-board by placing the two chips at 250 µm, as shown in the photograph in Figure 7, where the three channels are highlighted with dashed lines. The top one is the driver channel, the middle one is the power supply control channel, and the bottom one is the bidirectional diagnostic channel. Each chip occupies an area of about 3.6 mm × 2.1 mm, including protection circuits and pads.
A supply voltage of 6 V was adopted for each channel. The measured current consumptions for driver and bidirectional channels with 50% duty cycle signals are 7 mA and 8 mA, respectively, including about 1 mA of current for the bootstrapped test buffer. The current consumption for the power supply control channel is 7.5 mA, as reported in [46].
Figure 8, Figure 9 and Figure 10 show the 2 MHz PWM signal at the input and output of the driver channel with 10%, 50%, and 90%, of the duty cycle, respectively. The measured propagation delay of the output signal is about 45 ns. The bottom graph in Figure 9 highlights the comparison between the PWM output signals with and without the duty cycle distortion compensation. Thanks to the distortion compensator, the PWM signal distortion reduces by about 8 ns, from 18 ns to 10 ns. Moreover, it can also be seen that, thanks to the bootstrapped test buffer, all the measured output waveforms switch from the ground to the supply voltage with a sharp response, i.e., with a rise and fall time of about 10 ns, despite the probe input capacitance that is as high as 10 pF.
Figure 11 shows the 1 MHz PWM signal with a 50% duty cycle at the input and output of the bidirectional channel. High-frequency operation up to 10 MHz was also demonstrated as shown in Figure 12. No compensation distortion was used for this channel.
The channel carrier frequencies were measured thanks to an integrated test circuit based on a simple common-drain stage. An input capacitive partition was used, which provides a proper attenuation to avoid signal swing issues. The resulting carrier spectra are shown in Figure 13. The carrier frequencies for the driver channel, the power supply control channel, and the bidirectional channel are about 1.9 GHz, 940 MHz, and 440 MHz, respectively. The frequency separation between channels reduces crosstalk problems [46]. Finally, Table 1 summarizes the measured main electrical parameters of the galvanic isolation interface, also reporting a comparison with some typical state-of-the-art solutions.
The performance of the proposed galvanic isolation interface is aligned with the best works in the literature, although the only integrated implementation in GaN technology [46] is the previous work of the authors. With respect to the latter, this work includes the bidirectional diagnostic channel, achieves a better PWM signal distortion thanks to the distortion compensator, and provides a more robust receiver against process tolerances. The work in [45] includes a bidirectional diagnostic channel but it is implemented in BCD and hence is not suitable for the integration with the driver/power switch, which is possible instead with the GaN technology.

6. Conclusions

A three-channel galvanic isolation interface based on the chip-to-chip RF communication approach and magnetically coupled planar micro-antennas was presented. It implements the driver, the bidirectional diagnostic, and the control channel, thus performing the complete functionalities that are required in a high-performance fully integrated GaN power switching system with galvanic isolation. The interface is implemented with two chips placed at 250 µm and achieves a maximum rate of 2 MHz and 10 MHz for the driver and diagnostic channel, respectively.

Author Contributions

Validation, A.C.; Investigation, K.S., N.S. and G.P.; Writing—original draft, K.S.; Writing—review and editing, G.P.; Supervision, G.P. All authors have read and agreed to the published version of the manuscript.

Funding

This work has been carried out in the framework of the ECSEL European Project “Gallium Nitride for Advanced Power Applications” (GaN4AP), ECSEL JU No. 101007310.

Data Availability Statement

Data are contained within the article.

Acknowledgments

The authors would like to thank Mariantonietta Rizzo and Egidio De Giorgio of STMicroelectronics, Catania, Italy, for their support in layout.

Conflicts of Interest

Authors Nunzio Spina and Alessandro Castorina were employed by the company STMicroelectronics. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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Figure 1. Simplified on-package representation of the isolation interface based on chip-to-chip communication.
Figure 1. Simplified on-package representation of the isolation interface based on chip-to-chip communication.
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Figure 2. Example of system application. (a) Driver control channel, (b) power supply control channel, and (c) bidirectional diagnostic channel.
Figure 2. Example of system application. (a) Driver control channel, (b) power supply control channel, and (c) bidirectional diagnostic channel.
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Figure 3. (a) Simplified schematic of the proposed receiver, (b) PWM signal and clock phases operation, (c) schematic of the DVSB.
Figure 3. (a) Simplified schematic of the proposed receiver, (b) PWM signal and clock phases operation, (c) schematic of the DVSB.
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Figure 4. Simplified schematic of the previous receiver in [46].
Figure 4. Simplified schematic of the previous receiver in [46].
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Figure 5. Bootstrapped digital buffer.
Figure 5. Bootstrapped digital buffer.
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Figure 6. (a) Simplified schematic of the PWM duty cycle distortion compensator. (b) PWM and RF signals.
Figure 6. (a) Simplified schematic of the PWM duty cycle distortion compensator. (b) PWM and RF signals.
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Figure 7. Photograph of the chip-on-board assembly of the galvanic isolation interface.
Figure 7. Photograph of the chip-on-board assembly of the galvanic isolation interface.
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Figure 8. A 2 MHz and 10% PWM signal in the driver channel.
Figure 8. A 2 MHz and 10% PWM signal in the driver channel.
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Figure 9. A 2 MHz and 50% PWM signal in the driver channel.
Figure 9. A 2 MHz and 50% PWM signal in the driver channel.
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Figure 10. A 2 MHz and 90% PWM signal in the driver channel.
Figure 10. A 2 MHz and 90% PWM signal in the driver channel.
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Figure 11. A 1 MHz data signal in the bidirectional channel.
Figure 11. A 1 MHz data signal in the bidirectional channel.
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Figure 12. A 10 MHz data signal in the bidirectional channel.
Figure 12. A 10 MHz data signal in the bidirectional channel.
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Figure 13. Measured channel carrier frequencies. Markers 1, 2, and 3 refer to the bidirectional channel, supply control channel, and driver channel, respectively.
Figure 13. Measured channel carrier frequencies. Markers 1, 2, and 3 refer to the bidirectional channel, supply control channel, and driver channel, respectively.
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Table 1. Summarized performance and comparison with the state of the art.
Table 1. Summarized performance and comparison with the state of the art.
Parameters[42][45][46][50][51]This Work
Applicationn.a.Gate driversGate driversGate driversGate driversGate drivers
No of isolation channels232223
Max rate500 Mbit/s0.4 MHz (1)
15 MHz (2)		2 MHz (1)1 MHz1 MHz2 MHz (1)
10 MHz (2)
Propagation delay [ns]n.a.3430442840
PWM distortion [ns]n.a.n.a18n.a.6.510
Isolation technologyChip-to-chip RF communicationChip-to-chip RF communicationChip-to-chip RF communicationPolyimide
transformers		On-chip SiO2 capacitorsChip-to-chip RF communication
Isolation levelReinforced
(>10 kVPK)		Reinforced
(>10 kVPK) (3)		Reinforced
(>10 kVPK) (3)		Basic
(5.7 VRMS)		Reinforced
(8 kVPK)		Reinforced
(>10 kVPK) (3)
CMTI
[kV/μs]		50n.a. (4)n.a. (4)150100n.a. (4)
Supply voltage [V]1.83653/5.56
Technology0.18 µm CMOS0.32 μm BCD0.5 μm GaN on Sin.a.n.a.0.5 μm GaN on Si
No. of dice222232
Area [mm2]n.a.11.65.8n.a.n.a.8.7
(1) Driver channel. (2) Bidirectional diagnostic channel. (3) Estimated assuming 50 V/µm dielectric strength molding compound and 250-μm DTI. (4) Measurement is not available.
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Samperi, K.; Spina, N.; Castorina, A.; Palmisano, G. Three-Channel Fully Integrated Galvanic Isolation Interface in GaN Technology. Electronics 2025, 14, 1403. https://doi.org/10.3390/electronics14071403

AMA Style

Samperi K, Spina N, Castorina A, Palmisano G. Three-Channel Fully Integrated Galvanic Isolation Interface in GaN Technology. Electronics. 2025; 14(7):1403. https://doi.org/10.3390/electronics14071403

Chicago/Turabian Style

Samperi, Katia, Nunzio Spina, Alessandro Castorina, and Giuseppe Palmisano. 2025. "Three-Channel Fully Integrated Galvanic Isolation Interface in GaN Technology" Electronics 14, no. 7: 1403. https://doi.org/10.3390/electronics14071403

APA Style

Samperi, K., Spina, N., Castorina, A., & Palmisano, G. (2025). Three-Channel Fully Integrated Galvanic Isolation Interface in GaN Technology. Electronics, 14(7), 1403. https://doi.org/10.3390/electronics14071403

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