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Article
Peer-Review Record

Advancing Mapping Strategies and Circuit Optimization for Signed Operations in Compute-in-Memory Architecture

Electronics 2025, 14(7), 1340; https://doi.org/10.3390/electronics14071340
by Zhenjiao Chen 1,2, Binghe Ma 1, Feng Liang 3, Qi Cao 3, Yongqiang Wang 3, Hang Chen 3, Bin Lu 1 and Shang Wang 3,*
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Reviewer 3:
Electronics 2025, 14(7), 1340; https://doi.org/10.3390/electronics14071340
Submission received: 5 March 2025 / Revised: 25 March 2025 / Accepted: 26 March 2025 / Published: 27 March 2025
(This article belongs to the Section Circuit and Signal Processing)

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Dear Authors, please, read carefully and try to address all my notes and remarks.

  1. Try to express and separate, if possible, a little bit more clearly the motivation, purpose and tasks of the work in the Introduction. In the Conclusion, briefly state that the purpose is achieved and the tasks are resolved.
  2. In the end of the conclusion, try to add one sentence about potential future work on the topic.
  3. For additional improvement of the quality of the work, try to apply, if possible, several formulas related to the content. For this purpose, the authors could use some of the cited references.
  4. Try to discuss, if possible, in a little bit more details the used software NeuroSim. Try to give, if possible, a short comparison with similar works, which use frequently utilized software products, as Python, Matlab, Spice, Tensorflow and others.
  5. In the Conclusion, try to give a short description by one sentence about the main advantages and disadvantages of the proposed work.
  6. Try to include, if possible, one or two time-diagrams and schematics, related to the discussed content. As a template, the authors could use the cited references.
  7. Try to expand, is possible, the abstract by one or two sentences.
  8. The authors could try either to describe the abbreviations ISP and IOSP and the other ones immediately after their first appearance in the main text paper, or to give them in the list before the references. Check the requirements of the Journal template and also several of the newest papers published in the Journal for comparisons.
  9. Try to include the key-word “circuit optimization” in the main text of the paper.
  10. In the end of the Introduction, a short description of the remainder of the paper should be included, for example: Section 2 discusses …, In Section 3 is presented …
  11. A minor English grammar and spell check is required.
  12. Try to rename, if possible, the caption of Section 2 and make it more informative for the readers. The present caption “The proposed method” is very short.
  13. Try to separate the sub-section 3.2 “Results and discussion” in two parts. Section 3.1 could be named “Results”. Another section 4 could be introduced before the Conclusion and could be named “Discussion”.
  14. Try to include, if possible, in Section 2 and 3 some simple examples, related to the presented block diagrams. If possible, the authors could provide pseudo-codes of the discussed algorithms.
  15. The authors could provide, if possible, a brief information of the hardware parameters and software environment, related to the proposed algorithms, for example: “For the analyses and simulations, a computer configuration with …………. Operating system, …………… GB RAM memory, Intel i5 processor, … are used”.
  16. In the end of the Conclusion, the authors could try to provide some practical and future potential applications of the proposed methods. 
  17. In the abstract, try to expand the description in the fourth sentence which expresses several existing mapping strategies. Try to describe them, if possible, in a little bit more details. In the end of the abstract, try to add one sentence about the potential impact of the proposed work on the considered field of science. In parallel, consider the requirements of the Journal about the maximal length of the abstract. 
  18.  In the second Section, try to pay attention on the description of the applied research, related to the proposed mapping strategy. If possible, try to give some practical examples with pseudo-code or small block-diagrams or flowcharts. This could enrich the work and could bake it useful for the scientific community. 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The submitted manuscript proposes some improvements to the existing mapping strategies to support signed weights and activations for computer-in-memory architecture. The contributions of the paper are clear.

Below I include some comments to improve the paper.

# A short description of paper’s structure should be added at the end of the introduction.

# The authors have achieved improvements in latency and area efficiency, with minimal hardware overhead in their experiments. How can the results be generalized?

# Do the improvements work for all situations? Are there any situations, when they do not perform well?

# What are the limitations of the proposed improvements?

# Please pay attention to the references in the text. For example (line 35): “B et al. [8]” -> should be the full name.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Dear authors, in the next paragraphs, my comments about your manuscript.

 

It is very evident that there have been great improvements in the strategies as compared to the standard methodologies, which resulted in increased energy utilization and speed. Therefore, the proposed methods have been successful in giving improvements in energy utilization significantly (up to 4×) and speed (up to 3.59×). The work is also free from the loopholes that existed in other ways because it allows processing of signed weights and activations at very minimum additional costs. The study hypothesizes the limitations of the von Neumann architectures with the concept of the "memory wall" and proves how interconnected memory and computing (CIM) are advantageous for artificial intelligence applications. Different bit mapping strategies have been proposed, but most have disregarded the arrangement of most significant bits, or they do not permit signed operations. Division of numbers into positive and negative parts or of redesign of memory circuits has been executed in the previous works, but these always carry too much cost. Bringing forward minimum modifications to peripheral circuits, avoiding major changes in base architecture and being compatible with digital and analog CIM architectures would make them broadly useful. However, robust results have been obtained through simulations in NeuroSim V1.4 applied to networks such as Yolov3-tiny and ResNet18.

 

Points of improvement

1.It has comparative analysis with existing methods yet the article could include an extensive set of benchmark tests with various neural networks and architectures to showcase how the proposed optimizations may benefit them.

2.It could have introduced detailed comparative tables with other methodologies in order to highlight efficiency-boxes gains as well as the gain in performance.

3.The validation is, however, in simulation with NeuroSim V1.4 but really practical validation would be in hardware (FPGA or ASIC).

4.Measuring actual energy consumption and latency in hardware would, hence, solidify the advantages of the proposed techniques.

5.The authors mention that there is a high area overhead associated with the IOSP approach, without fully examining what this area overhead might entail for larger and more complex networks.

6.The interesting thing to evaluate is how optimizations behave when increased weight and activation matrices induce larger models.

7.There exists the potential for some of these more efficient strategies to incur some extra computing cycles; a more thorough discussion of this with respect to actual real-time-type applications such as edge inference would be informative. Some discussions could address energy efficiency versus latency trade-offs in different use-case scenarios.

8.The article mainly addresses SRAM-based digital CIM, although other memory technologies (e.g., ReRAM, PCM) would also be interesting to mention in relation to the optimizations proposed.

9.It could also provide an analysis on how these techniques might be adapted for various technology nodes (for example 7 nm, 5 nm) and how this impacts scalability and efficiency.

10.Some of these illustrations and diagrams could be clearer articulating data flows in ISP and IOSP strategies.

11.Multiple comparative graphs contrasting the different approaches should be added to the graphic representation of results to allow easy interpretation.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

I appreciate the efforts of the authors to improve paper’s quality. I have no other comments.

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