Xu, L.; Chang, Y.; Liu, L.; Qiao, K.; Xu, Z.; Wang, J.; Su, C.; Liu, T.; Yin, F.; Wang, X.
An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics 2025, 14, 1115.
https://doi.org/10.3390/electronics14061115
AMA Style
Xu L, Chang Y, Liu L, Qiao K, Xu Z, Wang J, Su C, Liu T, Yin F, Wang X.
An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics. 2025; 14(6):1115.
https://doi.org/10.3390/electronics14061115
Chicago/Turabian Style
Xu, Linmeng, Yu Chang, Liyu Liu, Kai Qiao, Zefang Xu, Jieying Wang, Chang Su, Tianye Liu, Fei Yin, and Xing Wang.
2025. "An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation" Electronics 14, no. 6: 1115.
https://doi.org/10.3390/electronics14061115
APA Style
Xu, L., Chang, Y., Liu, L., Qiao, K., Xu, Z., Wang, J., Su, C., Liu, T., Yin, F., & Wang, X.
(2025). An Efficient Simplified SPAD Timing Jitter Model in Verilog-A for Circuit Simulation. Electronics, 14(6), 1115.
https://doi.org/10.3390/electronics14061115
