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Volume 14
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Correction to Electronics 2024, 13(23), 4668.
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Correction

Correction: Li et al. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668

by
Qitao Li
1,
Wei Zhang
1,*,
Zhuolun Wu
1,
Yuzhou Dai
1 and
Yanyan Liu
2
1
School of Microelectronics, Tianjin University, Tianjin 300072, China
2
College of Electronic Information and Optical Engineering, Nankai University, Tianjin 300071, China
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(4), 727; https://doi.org/10.3390/electronics14040727
Submission received: 10 February 2025 / Accepted: 11 February 2025 / Published: 13 February 2025
Versions Notes
In the original publication [1], the data in Table 2 should be corrected due to typographical mistakes. A correction has been made to Table 2:
Original table:
Table 2. Count signals for 3–5 level DWT.
Table 2. Count signals for 3–5 level DWT.
cnt3[3:0]cnt4[1:0]cnt5[1:0]LevelModule
0–3××31
4–7××32
8–11××33
9–121×41
9–122×42
9–123×43
9–124151
9–124252
9–124353
9–1244NN
Corrected table:
Table 2. Count signals for 3–5-level DWT.
Table 2. Count signals for 3–5-level DWT.
cnt3[3:0]cnt4[1:0]cnt5[1:0]LevelModule
0–3××31
4–7××32
8–11××33
12–150×41
12–151×42
12–152×43
12–153051
12–153152
12–153253
12–1533NN
Additionally, some numbers in paragraph 2 in Section 3, Subsection 3.4 that are based on Table 2 should be corrected:
Original: “When cnt3 ranges from 12 to 15, the fourth-level DWT is executed for the first, second, and third tile blocks, contingent upon cnt4 values of 1, 2, and 3, respectively. Likewise, with cnt3 ranging from 12 to 15 and cnt4 set to 4, the fifth-level DWT is performed on the first, second, and third tile blocks based on cnt5 values of 1, 2, and 3. No calculations are conducted when cnt3 is between 12 and 15 and both cnt4 and cnt5 are set to 4”.
Corrected: “When cnt3 ranges from 12 to 15, the fourth-level DWT is executed for the first, second, and third tile blocks, contingent upon cnt4 values of 0, 1, and 2, respectively. Likewise, with cnt3 ranging from 12 to 15 and cnt4 set to 3, the fifth-level DWT is performed on the first, second, and third tile blocks based on cnt5 values of 0, 1, and 2. No calculations are conducted when cnt3 is between 12 and 15 and both cnt4 and cnt5 are set to 3”.
The authors state that the scientific conclusions are unaffected. This correction was approved by the Academic Editor. The original publication has also been updated.

Reference

  1. Li, Q.; Zhang, W.; Wu, Z.; Dai, Y.; Liu, Y. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668. [Google Scholar] [CrossRef]
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MDPI and ACS Style

Li, Q.; Zhang, W.; Wu, Z.; Dai, Y.; Liu, Y. Correction: Li et al. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668. Electronics 2025, 14, 727. https://doi.org/10.3390/electronics14040727

AMA Style

Li Q, Zhang W, Wu Z, Dai Y, Liu Y. Correction: Li et al. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668. Electronics. 2025; 14(4):727. https://doi.org/10.3390/electronics14040727

Chicago/Turabian Style

Li, Qitao, Wei Zhang, Zhuolun Wu, Yuzhou Dai, and Yanyan Liu. 2025. "Correction: Li et al. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668" Electronics 14, no. 4: 727. https://doi.org/10.3390/electronics14040727

APA Style

Li, Q., Zhang, W., Wu, Z., Dai, Y., & Liu, Y. (2025). Correction: Li et al. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668. Electronics, 14(4), 727. https://doi.org/10.3390/electronics14040727

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