A Real-Time Performance Assessment Scheme for Half-Bridge Submodules of Modular Multilevel Converters

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Dear authors,
the paper’s proposal, which consists of a technique for testing and evaluating submodules in modular multilevel converters without the need for the actual converter, is interesting as it combines real and virtual conditions.

1. Fig. 3: can the simplification of IGBTs as resistors, based on their bidirectional switching behavior, be applied under all conditions? For instance, with S1 turned on, S2 turned off, and the current flowing into the +Vsm terminal — how can S2 be represented by a resistor? I understand it would correspond to a very high resistance or an open circuit, but representing it simply by R2 raises doubts, since no current would flow through R2.

2. Fig. 5b: in the cells represented in positions 5 and 3, highlight in color the circuit that actually corresponds to the inverter submodule (SM), as this would improve readability.

3. Line 258 and Fig. 10: this part is unclear; the text states one thing (the blue waveform corresponds to the 29th SM), while the figure shows something different (the red waveform represents the 29th SM).

4. Simulations: it would be valuable to present a complete simulation considering all 30 virtual submodules under different grid conditions, and then the same scenario replacing the 30th SM with a real one, showing the waveforms of both the 30 virtual SMs and the real 30th one. Fig. 11 presents the waveform of another cell compared with the real one.

Author Response

Thank you so much. Please refer to the attached file for the reply

 

 

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The paper presents a novel real-time testing scheme for individual submodules (SMs) of Modular Multilevel Converters (MMCs) using Hardware-in-the-Loop Simulation (HILS). The proposed method is well-motivated, clearly explained, and validated through real-time simulation. The approach has practical significance for reducing development time and cost in MMC-based systems.

1.The selection of 30 SMs per arm is not justified. A brief explanation of why this number was chosen would be helpful.

2.More details on the inverter design and control strategy would strengthen the reproducibility of the work.

3.While the limitations of prior methods are mentioned, a more direct quantitative or qualitative comparison  would highlight the advantages of the proposed method more clearly.

4.The validation waveforms are shown for a short duration. A comment on the long-term stability of the proposed scheme, especially regarding the capacitor voltage balancing between the internal model and the external SM over multiple cycles, would strengthen the claim of operational identity.

Author Response

Thank you so much. Please refer to the attached file for the reply

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This paper presents a different real-time testing scheme designed for individual submodules of Modular Multilevel Converters (MMCs). The conventional approach to testing entire MMC systems is often labor-intensive and expensive, particularly given the complexity and number of series-connected submodules involved. The proposed method may enhance efficiency by enabling real-time assessment of each submodule under actual operating conditions, utilizing an external circuit configuration for one submodule. This proposal streamlines the testing process and may significantly lower development costs and time. The method's is validated through Hardware-in-the-Loop Simulation (HILS), showcasing its practical applicability in real-world scenarios.

Review,

The proposal allows for the real-time testing of individual submodules (SMs) rather than the entire MMC system, which is typically time-consuming and costly. This focuses on assessing each SM's performance under realistic operating conditions, thereby streamlining the testing process. This interesting approach not only might enhance the testing capabilities for MMCs but also may represent a significant step forward in the efficiency and effectiveness of HVDC system development. But…

In section 2 the Authors stated that “In the SM structure illustrated in Figure 3a, the IGBT can be represented as a two state resistor. This is because ……… The voltage across the capacitor is expressed by Equation (1)….”

This is a key part of the proposal but is not explained well. Many doubts arise. Diodes are unidirectional, resistors do not operate as switches, Ron and Roff are not equal in semiconductor switches. Then, strong references are needed. Moreover, is this an average model? If affirmative, what are the conditions used to comply with this average model? References are needed.

Fig. 5 needs better explanations. It is just confusing.

Figures showing Simulink opal models may look fine, but these are not necessary for general knowledge. Is this work perhaps dedicated only to those researchers who have a system such as that of the authors? How all potential readers could replicate this proposal without such tools.

Also,

“half-bridge” should be in the title

The manuscript is quite understandable just minor edition is needed

How does the testing method reduce development costs and time?

What challenges does traditional testing of MMC systems face?

Comments on the Quality of English Language

The manuscript is quite understandable just minor edition is needed

Author Response

Thank you so much. Please refer to the attached file for the reply

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Dears,
Regarding the review, the modifications and questions raised have been addressed, therefore the manuscript is in a condition to be accepted.

Reviewer 3 Report

Comments and Suggestions for Authors

Most of the issues have been addressed. This version of the paper is more clear.