A Real-Time Performance Assessment Scheme for Half-Bridge Submodules of Modular Multilevel Converters

Abstract

This paper proposes a real-time testing scheme for individual modules of Modular Multi-level Converters (MMCs), which are used in VSC-HVDC systems and high-voltage electric motor drives. In MMCs for voltage-source HVDCs, multiple submodules (SMs) are connected in series to form one arm. For MMCs comprising hundreds of identical submodules connected in series, testing the entire system is highly time-consuming and costly, while the proposed method enables real-time testing of each submodule, thereby significantly reducing overall system development cost and time. This study presents a method for configuring one SM from the series-connected SMs with an external circuit, allowing it to be tested under actual MMC operating conditions. The proposed method is comprehensively validated via Hardware-in-the-Loop Simulation (HILS), incorporating operability assessments and a real-time implementation of the circuit model to verify its practical applicability.

1. Introduction

A Modular Multi-level Converter (MMC) consists of multiple modularized structures, called Submodules (SMs), which are connected in series. Each SM contains low voltage-rated switching elements and is typically configured as either a half-bridge or a full-bridge. As a multi-level converter, the use of MMCs has been steadily increasing in voltage-source HVDC systems and high-voltage motor drive circuits [1,2,3,4,5,6,7,8,9,10,11,12]. The structure of an MMC involves connecting SMs in series, and this topology allows for easy adjustment of the voltage level by simply increasing or decreasing the number of SMs. Depending on the required voltage level, an MMC can comprise anywhere from several tens to several thousands of identical SMs connected in series. If the entire MMC system can be tested using only one or a few SMs, it would significantly shorten the development period and reduce costs.

To date, various methods for testing individual SMs or valve units, which combine several SMs, have been studied [13,14,15,16,17,18,19,20,21,22,23,24]. As reported in papers [13,14,15,16,17,18], their experimental circuit demonstrates a limitation in that the DC offset component and the second harmonic component are not fully represented when modeling the arm current. In the studies presented in papers [19,20,21,22], the DC offset component is successfully simulated, whereas the second harmonic component is not. For the work described in papers [14,23], a separate external circuit is implemented to generate the arm current. Since testing is conducted using a current with a predetermined pattern, this approach does not simulate actual operating conditions. In papers [13,21,22,24], a HILS test method for MMCs was proposed, but it involves testing all SMs collectively, rather than focusing on individual SMs.

The previous studies relied on fixed waveforms for the arm current and typically evaluated multiple SMs collectively rather than individually. To address these limitations, this paper proposes a novel method that enables the testing of a single SM under realistic MMC operating conditions. The core contribution of this work lies in replacing one SM within the MMC model with a dependent voltage source that mimics the electrical behavior of the actual SM. This voltage source is controlled by an SM test module, which interfaces with a simulated MMC system through hardware-in-the-loop simulation (HILS). This setup allows for accurate emulation of the arm current without the need for predefined current waveforms.

This paper presents an experimental approach for testing one SM in an MMC using Hardware-in-the-Loop Simulation. In the HILS test, one SM, which forms part of the MMC, serves as the hardware. The real-time operating MMC model in HILS is developed using MATLAB/Simulink R2019a, and one SM is selected as the hardware in the HILS test, with an external circuit configured accordingly. The arm current flowing through the SM configured in the external circuit is generated by an inverter, while the voltage of the submodule capacitor, which varies according to the arm current and the gate signal of the SM, is fed back to the MMC model in the real-time simulator. This feedback updates the MMC arm voltage information. By showing that the capacitor voltages of the individual SMs in the MMC and the capacitor voltage of the externally configured SM are identical, and that the current waveform in the real-time simulator matches that of the inverter, the validity of the proposed MMC testing method is demonstrated through the real-time HILS experiment. As a result, individual SMs can be validated under realistic operating scenarios, rather than simplified test conditions. This methodology not only enables detailed performance evaluation of each SM but also reduces the time and cost associated with MMC prototype development. Furthermore, it enhances the scalability and flexibility of research by allowing full-system validation using only a single physical SM module.

2. Real-Time Operational MMC Model for HILS Applications

Figure 1 illustrates the basic three-phase MMC structure. It has three legs, each consisting of two arms. Each arm contains SMs connected in series, with each SM configured as a half-bridge composed of a capacitor and two IGBTs. To accurately emulate the output voltage of the series-connected SMs, an equivalent MMC model is essential for real-time implementation. Figure 2 shows the MMC equivalent model used in this study. It is a model implemented in Simulink to operate on Opal-RT, a real-time operating system. The model consists of three phases, with the configuration of one leg (Leg-A) shown in the box on the right of the figure. Figure 3 depicts a model for equalizing the SM. One SM that forms the MMC arm in Figure 2 can be equalized to the form shown in Figure 3, depending on the direction of the switching and arm currents applied to $S_1$ and $S_2.$ The MMC model presented in this paper is based on the type 4 detailed equivalent circuit model proposed in reference [25,26]. In this model, the output voltage of the SM is represented through the equivalent resistance model.

In the SM structure illustrated in Figure 3a, the IGBT can be represented as a two-state resistor. This is because the diode connected in parallel with the IGBT functions as a bidirectional switch, allowing only one device to conduct during each switching cycle. The IGBT exhibits a resistance of $R_{on}$ when the switch is on, and a resistance of $R_{off}$ when the switch is off. The voltage across the capacitor is expressed by Equation (1). When the trapezoidal integration method is applied, the capacitor can be modeled as an equivalent voltage source and resistance, as shown in Equation (2). The values of $R_c$ and $v_{cEQ}$ are provided in Equations (3) and (4), respectively.

$$v_c\left(t\right)={\displaystyle \frac{1}{C}}{\int }_0^t{i}_c\left(t\right)dt \approx v_c\left(t-∆\mathrm{T}\right)+{\displaystyle \frac{1}{C}}\left({\displaystyle \frac{i_c\left(t-∆T\right)+i_c\left(t\right)}{2}}\right)∆T$$

(1)

$$v_c\left(t\right)=R_c·i_c\left(t\right)+v_{cEQ}\left(t-∆T\right)$$

(2)

$$R_c={\displaystyle \frac{∆T}{2C}}$$

(3)

$$v_{cEQ}\left(t-∆T\right)={\displaystyle \frac{∆T}{2C}}{i}_c\left(t-∆T\right)+v_c\left(t-∆T\right)$$

(4)

It can be observed that $R_c$ is determined by the capacitance and the simulation time step ΔT. The value of $v_{cEQ}$ is calculated based on the capacitance, the time step ΔT, the current flowing through the capacitor, and the voltage at the previous time step. The equivalent circuit of the SM, derived from the capacitor voltage modeling and the switch resistances $R_1$ and $R_2$ is shown in Figure 3b. The output terminal voltage of the SM, $v_{sm}$, is expressed in Equation (5).

$$v_{sm}\left(t\right)=R_{smEQ}·i_{sm}\left(t\right)+v_{smEQ}\left(t-∆T\right)$$

(5)

$R_{smEQ}$ and $v_{cEQ}\left(t-∆T\right)$ are as shown in Equations (6) and (7), respectively.

$$R_{smEQ}=R_2\left(1-{\displaystyle \frac{R_2}{R_1+R_2+R_c}}\right)$$

(6)

$${ v}_{smEQ}\left(t-∆T\right)=\left({\displaystyle \frac{R_2}{R_1+R_2+R_c}}\right)\times V_{cEQ}\left(t-∆T\right)$$

(7)

While Figure 3b illustrates the equivalent model for an individual SM, Figure 4 presents the equivalent model for an SM string, which consists of a series-connected structure of SMs. In this configuration, the output terminals of the SMs are connected in series. The voltage of the SM string can be expressed as the sum of all individual $v_{sm}$ values, as shown in Equation (8).

$$v_{SMstring}\left(t\right)=\sum _{i=1}^N{v}_{s{m}_i}\left(t\right)=\sum _{i=1}^N{R}_{smE{Q}_i}·i_{SMstring}\left(t\right)+\sum _{i=1}^N{v}_{smEQ}\left(t-∆T\right)=R_{EQ}·i_{SMstring}\left(t\right)+v_{EQ}\left(t-∆T\right)$$

(8)

Equation (8) represents the structure of a series connection of the equivalent resistance and voltage source of the string, as shown in Figure 4b. This configuration can be modeled as a Thevenin equivalent circuit. Meanwhile, the Norton equivalent circuit is shown in Figure 4c. In the model shown in Figure 2, the voltage of each arm is implemented using the Norton equivalent circuit depicted in Figure 4c.

3. Test Method for Selected SMs Within a Series-Connected Configuration

Figure 5 presents a schematic diagram of the proposed test method for SM modules, illustrated here for a single SM in a series connection. While this study demonstrates the method using one SM as an example, the proposed approach can be readily extended to test a specific number of SMs within a series-connected structure. The MMC used in this study consists of 30 SMs per arm. As illustrated in Figure 5a, SM1 to SM29 of the MMC were implemented as equivalent models in a real-time operating system (OS). In the proposed method, as shown in Figure 5b, the SM inside the MMC (the 30th SM in this paper, represented by the red block ①) is replaced with a dependent voltage source (green block ②). The value of this dependent voltage source is assigned using the voltage from the external SM Testing Module. Figure 5b illustrates the external SM Testing Module (green block ③) implemented outside the MMC equivalent model for HILS testing. The current flowing through the external SM is identical to the internal current of the MMC, and this current is controlled by the inverter. Within the MMC, SM30, represented by the red block ①, was replaced with a dependent voltage source, shown as the green block ② in Figure 5b. One SM is implemented outside the MMC equivalent model, as shown in block ③, and operates as external circuit for the HILS test. The current flowing through the SM in block ③ is identical to the arm current $i_{arm}$, and the inverter and inductor $L$ are used to emulate this current. The current command value $i^{*}$ after SM29 is applied to the external L, as marked by ④. The resulting $V_{testcapSM}$ is applied to the dependent voltage source, as indicated by ⑤, enabling the operation of the module.

Figure 6 shows the actual implementation block of the real-time OS for Figure 5. It displays the Leg-A section of the MMC within the SM_Subsystem block in the MATLAB/Simulink model of Opal-RT, along with the proposed scheme. In the MMC equivalent model shown in Figure 2, the last SM among the 30 SMs in the upper arm of Leg-A is extracted to configure the test circuit. In this configuration, 29 SMs are represented by the equivalent model of the MMC arm, while one externally installed SM is replaced by a dependent voltage source. Specifically, a single SM block, expressed as a half-bridge, is substituted with a dependent voltage source. The magnitude of this dependent voltage is determined by the gate signal of the SM and the capacitor voltage of the SM.

The magnitude of the dependent voltage source equivalent to the nth SM is as shown in Equation (9), where S represents the gate signal. S has a value of 1 when the upper switch is on and 0 when the lower switch is on. The magnitude of $V_{capSM}$ corresponds to the voltage of the SM capacitor, as shown in Figure 5b.

$$v_{sm\_n}=S \times v_{capSM}$$

(9)

In Figure 6, blocks ① to ③ are the components required in the Opal-RT real-time simulator to exchange signals with external systems. Block ① in Figure 6 serves as the initialization block for the Opal-RT real-time simulator and a block for input/output monitoring. Block ② represents the OpCtrl component, which receives the current command value and gating signal sent by MMC Leg-A. The blue block ③ is the OpCtrl block responsible for PI control, applying the gate signal to the external testing SM module to generate outputs for controlling the inverter. After measuring the $V_{capSM}$ value resulting from this process, the value is applied to the dependent voltage source that replaces the 30th SM in MMC Leg-A.

4. Emulation of Voltage Relationships and Currents of the External SM

The SM output voltage is determined by S (gate signal). Meanwhile, the voltage of the SM capacitor is influenced by the direction of the arm current and the value of S. The relationship between $V_{SM}$, the direction of the arm current, and S is summarized in

Table 1. Output voltage of SM depending on the switching state and charge/discharge of the SM’s capacitor according to the direction of the arm current.

	${\mathit{i}}_{\mathit{S}\mathit{M}}\mathbf{>}\mathbf{0}$	${\mathit{i}}_{\mathit{S}\mathit{M}}\mathbf{<}\mathbf{0}$	${\mathit{v}}_{\mathit{S}\mathit{M}}$
$S_1$ on $(S_1=1, { S}_2=0)$			$V_{capSM}$
$S_2$ on $(S_1=0, S_2=1)$			0

. It can be observed that when $S_1$ is on, the $V_{SM}$ voltage is equal to the SM capacitor voltage, regardless of the direction of the arm current. When $S_1$ is off, $V_{SM}$ is 0, irrespective of the direction of the arm current. From Equation (9), it follows that when S = 1, $V_{SM}$ is equal to $V_{capSM}$, and when S = 0, $V_{SM}$is 0.

Since the SMs are connected in series, the arm current is the same for all the SMs. When $S_1$ is on, the SM capacitor is charged or discharged depending on the direction of $i_{SM }$(arm current). When $S_1$is off, current flows toward the lower arm element, creating no charge/discharge path to the capacitor, and thus there is no change in $V_{SM}$. Meanwhile, the arm current flowing through the SM block in Figure 5b is controlled via the inverter. Figure 7 shows the externally located SM and the inverter circuit configured to generate current flowing through the SM with the same waveform as the arm current ($i_{SM})$. Even when controlling the current using the method in Figure 7, the magnitude depends on S and the direction of the current, satisfying the relationship presented in Table 1. Figure 7a shows the current path based on the direction of the load current when $S_1$ is on. It can be observed that the same current path is generated as in the case where $S_1$ = 1 in Table 1. It can be seen that the current control by the inverter and the voltage change in $V_{capSM}$ follow the same pattern. Figure 7b shows the current path when $S_2$ = 1, which is when $S_1$ = 0. Since there is no current path to $V_{capSM}$, similar to the case where $S_2$ = 1 in Table 1. There is no change in the magnitude of $V_{capSM}$. It can be seen that the magnitude of the voltage $V_{capSM}$ is implemented in a way that accurately reflects the actual operating conditions, as the control of the $i_{SM}$ using the inverter.

5. Verification Through Hardware-in-the-Loop Testing

To demonstrate the validity of the proposed scheme, the circuit shown in Figure 6 was run in real time. Figure 8 illustrates the configuration of the SC_console section, showing the measured values in Opal-RT, the real-time simulator, and the waveforms monitored in real time.

The voltage and current values in the equivalent model, along with the capacitor voltage and current values of the SM taken outside, were monitored using two channels each from the eight available in/out channels.

Table 2. System specifications used in HILS test.

	Parameters		Value
MMC	$V_{dc}$	DC-link voltage of MMC	300 V
	$L_{load}$	Load inductance	0.01 H
	$L_{arm}$	Arm inductance	0.03 H
	$N_{arm}$	Number of SM per arm	30
	$C_{MMC}$	Capacitance of SM capacitor	0.02 F
Externally	$V_{dc\_SM}$	DC voltage of SM	20 V
located	$L_{SM}$	Inductance of an inductor in an inverter	0.01 H
SM	$C_{SM}$	Capacitance of SM capacitor	0.02 F

presents the specifications of the system used in the experiment. Figure 9 illustrates a comparison of the ${\mathit{V}}_{\mathit{a}\mathit{s}}$ waveforms of the MMC-HVDC systems. Figure 9a shows the ${\mathit{V}}_{\mathit{a}\mathit{s}}$ waveform of the original MMC-HVDC, while Figure 9b shows the ${\mathit{V}}_{\mathit{a}\mathit{s}}$ waveform of the testing SM module’s MMC-HVDC with the proposed method. This is the case when there is one SM (30th SM) on the outside. The two waveforms are shown to coincide, confirming that the real-time operation circuit functions under the same real-time conditions.

Figure 10 shows the voltage waveforms of the SM capacitor. The red waveforms represent the capacitor voltages of the SM test module, while the blue waveforms represent the voltage values of the 29 capacitors in the MMC leg-A upper arm. Since Opal-RT operates in real time, the operation was stopped after 10 s, and the waveforms up to 0.5 s were enlarged to display the detailed waveforms. Except for the initial time, it can be observed that the capacitor voltage waveform inside the MMC and the capacitor voltage waveform of the external SM test module are identical. Figure 11 illustrates the arm current waveform generated using the arm current and inverter. As with the previous figures, the waveform up to 0.5 s is enlarged to display the detailed waveform. After the current build-up time in the inductor, it can be observed that the arm current command value and the actual current value are identical, validating the effectiveness of the proposed methodology.

Figure 10 presents the DC voltage of the 29th SM block and the DC-side capacitor voltage waveform within the externally implemented SM Testing module. The red waveforms represent the capacitor voltages of the SM test module, while the blue waveforms represent the voltage values of the 29th capacitors in the MMC leg-A upper arm. Since Opal-RT operates in real time, the operation was stopped after 10 s, and the waveforms up to 1 s were enlarged to display the detailed waveforms. Except for the initial time, it can be observed that the capacitor voltage waveform inside the MMC and the capacitor voltage waveform of the external SM test module are identical.

Figure 11 illustrates the arm current waveform generated using the arm current and inverter. As with the previous figures, the waveform up to 0.5 s is enlarged to display the detailed waveform. After the current build-up time in the inductor, it can be observed that the arm current command value and the actual current value are identical, validating the effectiveness of the proposed methodology.

6. Conclusions

This paper proposed a real-time testing scheme for the submodule performance of an MMC-based HVDC system by extracting one SM externally and conducting real-time hardware-in-the-loop testing. The validity of the proposed method was demonstrated through real-time simulation using MATLAB/Simulink and a real-time OS. Unlike existing submodule test methods, the proposed model enables testing in conditions identical to actual operating scenarios. Configuring one SM as an external circuit and performing real-use scenario tests on an MMC-based HVDC system model made up of tens to hundreds of submodules enables verification and experimentation at significantly reduced costs. The scheme developed in this study is expected to yield significant economic and time benefits in the development of systems using MMC.