A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs
Abstract
1. Introduction
2. Background on Structured and Systematic Analog Design
2.1. Structured Analog Design
- Amplification Structures: These include differential pairs, simple gain stages, and cascode amplifiers. Their purpose is to provide voltage amplification and signal processing.
- Load and Bias Structures: This group includes resistive loads, current mirrors, and cascode current mirrors. They define the output impedance and enable current control and replication.
- Biasing Networks: These comprise voltage bias stacks and startup circuits, ensuring proper operating points for active devices throughout the system.
- A symbolic netlist derived from a small-signal model;
- A set of internal electrical variables;
- Exploratory parameters (e.g., currents, dimensions);
- A connection interface to other macromodels or primitives.
2.2. Systematic Design
- -based design, where the ratio between transconductance and drain current determines device sizing and inversion level;
- Voltage/current domain separation, which simplifies the estimation of biasing and signal parameters;
- Lookup Tables (LUTs) derived from PDK-level simulations, enabling accurate prediction of electrical parameters over a wide range of operating points.
2.3. Symbolic Analysis and MNA
- Insight into parameter dependencies, showing how performance metrics evolve with design variables;
- Efficient local exploration, where symbolic equations can be evaluated rapidly over different input values;
- Compatibility with automation, as the symbolic form can be programmatically manipulated to extract or verify electrical constraints.
2.4. Lookup Tables (LUTs) for Design Exploration
3. Proposed Methodology
3.1. Stage 1: Pre-Exploration
3.2. Stage 2: Global Exploration
- Top-down flow (Specification derivation): Circuit specifications are propagated from the top level down to the primitives at the base of the hierarchy, defining constraints for each macromodel and subblock.
- Bottom-up flow (Design space propagation): Once the lower levels are evaluated, the results are propagated upward, updating and optimizing the parameters of higher-level macromodels.
- Select the current macromodel under evaluation.
- If the macromodel contains primitives, generate its corresponding design space.
- Perform local exploration using predefined parameters and the values obtained from its primitives.
- Filter the results to ensure compliance with design constraints.
- If the macromodel contains submacromodels, derive new constraints from the exploration results.
- Use these derived constraints to explore the submacromodels, repeating the process until the lowest level is reached.
- Once a macromodel with no submacromodels is reached, return its exploration results to the next level up in the hierarchy.
- Use the obtained values to update previously predefined parameters in the parent macromodel.
- Re-optimize the results to meet the derived specifications.
- If another adjacent macromodel exists, mark it as next and resume the global exploration flow.
3.3. Stage 3: Local Exploration
- Symbolic analysis: This step extracts the system of equations that describe the behavior of the testbench using MNA. Solving the resulting linear system enables the explicit definition of the transfer function or any other target equation required for the design objective.
- Vectorized evaluation: Once the symbolic equations are formulated, all design-space equations are computed in a single batched array operation, treating the parameters set as arrays. This eliminates explicit Python loops and accelerates the exploration.
4. Implementation
4.1. Context and LDO Architecture
- Error Amplifier: Compares the output voltage with a reference and amplifies the error.
- Pass Element: A power transistor (typically PMOS or NMOS) that regulates the current flow from input to output.
- Feedback Network and Compensation: Sets the regulation point and ensures stability.
4.2. Design Objectives
4.3. Stage 1 Implementation
4.3.1. Modularization
4.3.2. Testbenches
4.3.3. LUT Generation
4.4. Stage 2–3 Implementation
4.4.1. Exploration Results
Transition 1: From LDO to Error Amplifier
Transition 2 and 3: From Amplifier to Primitives
Transitions 4, 5 and 6: Exploration of Intermediate Blocks
Transition 7: Final Resolution of the LDO
4.5. Evaluation of Alternative Topologies and Technologies
- Single-stage OTAs provide higher phase margins due to simpler stability requirements, but generally at the cost of greater area.
- The two-stage OTA achieves a better balance between stability and compactness.
- Among the technologies, IHP SG13G2 enables valid designs with minimal area; Sky130A offers a moderate trade-off; and GF180MCU, while requiring more area, supports all topologies thanks to its higher-voltage devices.
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Specification | Design Objective |
---|---|
1.8 V | |
1.2 V | |
0.9 V | |
PSRR (100 Hz) | <−60 dB |
Dropout | <400 mV |
Load regulation | <1 mV/mA |
Phase margin | >60° |
0.5 pF | |
5 mA | |
Current efficiency | >98% |
W of pass transistor | <15 mm |
W of amplifier transistors | 1 μm < W < 200 μm |
Topology Technology | A IHP | A SKY | A GF | B GF | C GF |
---|---|---|---|---|---|
Area [mm] | 0.60 | 0.79 | 1.01 | 1.12 | 1.2 |
PSRR [dB] | −62.08 | −65.71 | −76.15 | −60.05 | −64.65 |
Loadreg | 0.185 | 0.456 | 0.022 | 0.693 | 0.756 |
Dropout [mV] | 326.78 | 333.82 | 380.67 | 380.67 | 380.67 |
Phase Margin | 85.77 | 89.98 | 73.29 | 89.89 | 89.95 |
Transition | No Before Filter | No After Filter | Reduction Percentage |
---|---|---|---|
1 | – | – | |
2 | – | – | |
3 | 410 | ||
4 | – | – | |
5 | 3125 | 46 | |
6 | 19 | ||
7 | 76 | 23 |
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Arévalos, D.; Marin, J.; Herman, K.; Gomez, J.; Wallentowitz, S.; Rojas, C.A. A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics 2025, 14, 3448. https://doi.org/10.3390/electronics14173448
Arévalos D, Marin J, Herman K, Gomez J, Wallentowitz S, Rojas CA. A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics. 2025; 14(17):3448. https://doi.org/10.3390/electronics14173448
Chicago/Turabian StyleArévalos, Daniel, Jorge Marin, Krzysztof Herman, Jorge Gomez, Stefan Wallentowitz, and Christian A. Rojas. 2025. "A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs" Electronics 14, no. 17: 3448. https://doi.org/10.3390/electronics14173448
APA StyleArévalos, D., Marin, J., Herman, K., Gomez, J., Wallentowitz, S., & Rojas, C. A. (2025). A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics, 14(17), 3448. https://doi.org/10.3390/electronics14173448