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Article

A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs

1
Faculty of Computer Science and Mathematics, Hochschule München University of Applied Sciences, 80335 Munich, Germany
2
Department of Electronic Engineering, Universidad Técnica Federico Santa Maria, Valparaiso 2390123, Chile
3
Advanced Center of Electrical and Electronics Engineering, Universidad Técnica Federico Santa Maria, Valparaiso 2390103, Chile
4
IHP—Leibniz Institute for High Performance Microelectronics, 15236 Frankfurt, Germany
5
Facultad de Ingeniería y Ciencias Aplicadas, Universidad de Los Andes, Santiago 7620086, Chile
*
Authors to whom correspondence should be addressed.
Electronics 2025, 14(17), 3448; https://doi.org/10.3390/electronics14173448
Submission received: 15 July 2025 / Revised: 19 August 2025 / Accepted: 26 August 2025 / Published: 29 August 2025
(This article belongs to the Special Issue Mixed Design of Integrated Circuits and Systems)

Abstract

This work proposes a methodology for the automated sizing of transistors in analog integrated circuits, based on a modular and hierarchical representation of the circuit. The methodology combines structured design techniques and systematic design flow to generate a hierarchy of simplified macromodels that define their specifications locally and are interconnected with other macromodels or transistor-level primitive blocks. These primitive blocks can be described using symbolic models or pre-characterized data from look-up tables (LUTs). The symbolic representation of the system is obtained using Modified Nodal Analysis (MNA), and the exploration of each block is performed using local design spaces constrained by top-level specifications. The methodology is validated through the design of low dropout voltage regulators (LDOs) for DC-DC integrated power systems using open-source tools and three process design kits: Sky130A, GF180MCU, and IHP-SG13G2. Results show that the methodology allows the exploration of several topologies and technologies, demonstrating its versatility and modularity, which are key aspects in analog design.

1. Introduction

The design of analog integrated circuits (ICs) faces numerous challenges in the technology landscape, which demands increasingly efficient and robust solutions, particularly in terms of power consumption, area usage, and tolerance to process variability [1]. These circuits are essential for linking the physical and digital worlds, enabling signal conditioning and data conversion for electronic systems [2]. Despite their importance, analog IC design remains constrained by the lack of abstraction and standardized tools that can simplify the design process and promote a repeatable and systematic design flow [3,4]. As a result, analog design is often considered a bottleneck in integrated system development and a major barrier to improving the productivity of design teams [5,6].
The increasing demand for more efficient and portable analog integrated circuits has further exposed the limitations of traditional design flows, which are highly dependent on designer expertise and iterative manual tuning. Unlike digital design, analog design automation remains a significant challenge because of the high sensitivity of circuit behavior to process variations and its inherent nonlinearity such as temperature effects and dead-time design in Power Management Integrated Circuits (PMICs) [7].
Within this context, Low Dropout Regulators (LDOs) represent a particularly relevant case study. These circuits are widely used in battery-powered and mixed-signal systems and are required to simultaneously satisfy multiple performance specifications, such as loop gain, power supply rejection ratio (PSRR), phase margin, and current efficiency [8,9]. This multi-objective nature makes the sizing of LDOs a complex and often unsystematic task.
Several methods have emerged to address analog design automation, including machine learning models, numerical optimization techniques, and topology-specific template-based strategies [10,11]. However, these approaches still exhibit key limitations: lack of interpretability, difficulty in generalizing across different circuit topologies, and persistent dependence on expert intervention during critical phases of the flow. Moreover, many of these techniques do not fully exploit the inherent modularity and reusability of analog building blocks. In the specific case of LDOs, a general automation approach has been demonstrated in [12]; it adopts a systematic, symbolic methodology but does not address this aspect, and its scalability to higher-complexity designs is not established.
This paper proposes a hierarchical and modular methodology for the automated sizing of transistors in analog circuits. The approach combines structured design principles—where the circuit is decomposed into functional building blocks—with systematic design flow, which allows efficient circuit design exploration. Each block is abstracted as a macromodel with a simplified symbolic representation generated via Modified Nodal Analysis (MNA) [13], and locally explored using precomputed Lookup Tables (LUTs) [14]. This hybrid representation enables efficient design space exploration, reduces simulation overhead, and facilitates reuse across technologies and topologies.
This paper extends our previous conference work presented in [15], by generalizing the methodology to support multiple topologies, proposing a scalable exploration flow, and validating the approach across three open PDKs with fully automated transistor sizing. The contributions of this paper are three main points: (1) the proposal of a scalable and topology-independent design methodology for analog circuits, (2) the integration of symbolic modeling and LUT-based exploration in a hierarchical automation flow, and (3) the validation of the approach through the implementation of different topologies of LDOs using open-source tools and three different open PDKs. Thus, the key innovation of this work is a portable and modular design framework that minimizes designer intervention while preserving electrical interpretability.
The rest of this paper is organized as follows. Section 2 presents the theoretical foundations of structured and systematic analog design among other key concepts. Section 3 describes the proposed methodology in detail. Section 4 shows validation results using LDO designs implemented across different topologies and PDKs: Sky130A [16], GF180MCU [17], and IHP-SG13G2 [18]. Finally, Section 5 discusses conclusions and future perspectives.

2. Background on Structured and Systematic Analog Design

2.1. Structured Analog Design

Structured analog design is a methodology that organizes the development of analog circuits based on a hierarchy of reusable functional blocks [19]. Instead of approaching design from individual transistor behavior, this paradigm focuses on composing systems from a limited set of well-defined primitives, each responsible for a specific electrical function.
The primitives, which are shown in the Figure 1, serve as building blocks for more complex subcircuits, which in turn are composed into complete analog systems. Each block fulfills a dedicated role within the circuit and can be characterized using a small number of electrical parameters, such as gain, impedance, transconductance, or current consumption. This abstraction enables early specification of requirements at the system level and modular verification at the block level.
In the structured methodology, the set of analog primitives is classified into three main categories, based on their role in circuit operation:
  • Amplification Structures: These include differential pairs, simple gain stages, and cascode amplifiers. Their purpose is to provide voltage amplification and signal processing.
  • Load and Bias Structures: This group includes resistive loads, current mirrors, and cascode current mirrors. They define the output impedance and enable current control and replication.
  • Biasing Networks: These comprise voltage bias stacks and startup circuits, ensuring proper operating points for active devices throughout the system.
A key advantage of the structured approach is that the number of fundamental building blocks is finite, and their behavior is well understood. By combining them in a hierarchical manner, designers can construct complex circuits with predictable properties. This supports hierarchical reasoning, reuse, and facilitates automation [20,21].
In this work, structured design is used to define a macromodel library, where each macromodel encapsulates a functional block defined by:
  • A symbolic netlist derived from a small-signal model;
  • A set of internal electrical variables;
  • Exploratory parameters (e.g., currents, dimensions);
  • A connection interface to other macromodels or primitives.
This organization enables the proposed methodology to operate in a recursive manner, exploring local design spaces, verifying constraints, and propagating specifications throughout the system in a scalable and reusable fashion.
An additional contribution of this work to structured design is the introduction of a higher level of abstraction, where different primitives can be represented through a common symbolic structure, provided that their electrical parameters are redefined according to the specific topology. For example, a common-source configuration and its cascode counterpart can share the same simplified symbolic model once their small-signal representations are replaced and further reduced. As shown in Figure 2, this leads to an identical structural model with distinct expressions for parameters such as g d s , g m and C i n . This approach differs from traditional structured design that was presented in [19], where separate strategies are defined for each primitive without applying a unified abstraction. Instead, this unified symbolic structure simplifies the treatment of basic blocks within the automated flow.
Nevertheless, while structured design facilitates hierarchical organization and the derivation of electrical equations, it remains insufficient for transistor sizing. This step still relies on analytical models such as the quadratic approximation or EKV model, which present several limitations; they require specific algebraic manipulation for each block, do not scale easily to more complex structures, and lose accuracy in modern technologies where these models fail to capture the true behavior of transistors.
These limitations motivate the transition to systematic design, which addresses sizing directly using preprocessed technological data via LUTs and design space exploration techniques, as detailed in the following section.

2.2. Systematic Design

Systematic analog design refers to a methodology where electrical specifications guide the selection of circuit parameters using formalized models and structured procedures [22]. Rather than relying on trial-and-error or designer intuition, this approach establishes direct relationships between performance metrics and electrical quantities such as transconductance, output resistance, or bias current.
A key element of systematic design is the use of analytical equations or precharacterized data to estimate the behavior of a circuit block without the need for full transistor-level simulations at each step. For instance, expressions for gain, bandwidth, or output swing can be derived from simplified small-signal models and used to constrain the values of internal variables before committing to device-level implementations.
Systematic design supports techniques such as:
  • g m / I D -based design, where the ratio between transconductance and drain current determines device sizing and inversion level;
  • Voltage/current domain separation, which simplifies the estimation of biasing and signal parameters;
  • Lookup Tables (LUTs) derived from PDK-level simulations, enabling accurate prediction of electrical parameters over a wide range of operating points.
In this context, systematic design serves as a sizing philosophy that can be integrated into automated frameworks. It enables fast evaluation of circuit configurations, supports constraint-driven design, and improves portability across different process technologies.
The methodology proposed in this work builds upon these principles to structure local block-level exploration based on symbolic models and precomputed data, as further discussed in Section 3.

2.3. Symbolic Analysis and MNA

Symbolic analysis is a technique that derives analytical expressions describing the electrical behavior of a circuit using algebraic manipulation rather than numerical simulation. In this work, the analysis is based on the MNA method, which constructs a system of equations relating the voltages and currents at each node of the circuit.
Each analog block is represented by a symbolic netlist, where components are modeled using their small-signal equivalents. For example, MOSFETs may be abstracted using transconductance ( g m ) and output resistance ( r o ), while current sources and resistors are inserted directly as algebraic terms. The MNA process then systematically generates a set of equations of the form:
A · x = b
where the matrix A contains symbolic expressions involving parameters like gm, ro, and load resistance, and the vector x contains the node voltages or currents of interest. Solving this system yields transfer functions, gains, impedances, and other circuit characteristics in symbolic form. This representation enables:
  • Insight into parameter dependencies, showing how performance metrics evolve with design variables;
  • Efficient local exploration, where symbolic equations can be evaluated rapidly over different input values;
  • Compatibility with automation, as the symbolic form can be programmatically manipulated to extract or verify electrical constraints.
The symbolic analysis is performed automatically using Python3.10-based tools, enabling each block in the design to be characterized algebraically before committing to numerical validation or transistor-level implementation.

2.4. Lookup Tables (LUTs) for Design Exploration

The use of LUTs is a well-established technique in systematic analog design to avoid expensive iterative simulations. LUTs store precharacterized data obtained through sweeping transistor parameters under specific process design kits (PDKs), enabling the retrieval of electrical parameters such as transconductance, output resistance, or saturation voltage for given device dimensions and bias conditions.
In the proposed methodology, LUTs are used to provide accurate device-level data for primitive blocks during the exploration phase, enabling rapid evaluation of design alternatives while preserving PDK fidelity. This allows each macromodel to transition from an estimated symbolic model to a numerically accurate instance once the primitives are resolved.

3. Proposed Methodology

This work proposes a methodology that integrates the principles of structured design and systematic analog design to enhance the automation of analog circuit sizing. The key concepts behind these approaches were introduced in Section 2.1 and Section 2.2.
From structured design, the methodology adopts the hierarchical decomposition of the circuit into functional blocks called macromodels. Each macromodel may contain internal sub-macromodels or terminal primitives. It also incorporates the derivation and propagation of specifications, allowing design constraints to be transferred from the system level down to the fundamental circuit elements. This modular structure facilitates the analysis, optimization, and reuse of analog blocks.
From systematic design, the methodology introduces efficient design space exploration based on LUTs, reducing reliance on iterative SPICE simulations. This significantly shortens the exploration time and removes the need for manual tuning in each design iteration. The methodology is organized into three main stages, as illustrated in Figure 3:
Stage 1—Pre-exploration: The circuit is decomposed to build the hierarchical tree. Testbenches are defined, and the technology-specific LUTs are generated. LUT generation is the only automated step in this initial stage.
Stage 2—Global exploration—derivation of specifications: The hierarchy tree is explored. Specifications are propagated and feasible solutions are filtered.
Stage 3—Local exploration: While technically part of the global exploration, this is the core optimization step, responsible for generating the full design space that will later be constrained and filtered.

3.1. Stage 1: Pre-Exploration

The first stage of the proposed flow is responsible for preparing all necessary circuit data and models prior to automated exploration. This includes the modularization of the circuit, the definition of testbenches for each block, and the generation of technology-specific Lookup Tables (LUTs).
The process is shown in the Figure 4 and begins with the modularization of the circuit, performed following the same principles presented in structured analog design. The circuit is decomposed into functional blocks—referred to as macromodels—and organized into a hierarchy tree that captures the dependencies between macromodels, submacromodels, and terminal primitives at each level. This tree serves as the structural foundation for managing the flow of specifications and guiding the exploration process across the design.
Next, testbenches are defined to evaluate each macromodel according to its specifications. These are SPICE-compatible circuits that include the necessary stimulus and connections to simulate the behavior of the block in isolation, avoiding the need for manual equation solving. Since each macromodel must meet specific design objectives, a dedicated testbench is created for every level in the hierarchy. This stage also includes an automated LUT generation process. For each device and technology under consideration, a Lookup Table is created using Python scripts that drive controlled simulations to extract key electrical parameters. Once configured, this process runs autonomously, allowing systematic LUT generation across multiple PDKs with minimal manual input. This preparatory stage ensures that all structural and electrical data required for the next phases of the methodology are correctly established and formatted.

3.2. Stage 2: Global Exploration

The second stage of the proposed flow corresponds to the global exploration, where the hierarchy of macromodels and primitives defined in the previous stage is systematically explored. During this phase, the parameters of each macromodel are optimized in a hierarchical fashion, ensuring consistency with the structural constraints imposed by the circuit. This stage follows a bidirectional exploration strategy that combines two complementary analysis flows:
  • Top-down flow (Specification derivation): Circuit specifications are propagated from the top level down to the primitives at the base of the hierarchy, defining constraints for each macromodel and subblock.
  • Bottom-up flow (Design space propagation): Once the lower levels are evaluated, the results are propagated upward, updating and optimizing the parameters of higher-level macromodels.
The strategy minimizes the number of evaluations required. In the top-down flow, the number of combinations does not grow exponentially since it depends only on the default parameters of submacromodels. However, in the bottom-up direction, if the design space is not properly filtered, the number of combinations can increase exponentially, impacting computational efficiency and execution time.
To traverse the hierarchy efficiently, the global exploration uses a Depth-First Search (DFS) algorithm [23]. This allows each macromodel to be evaluated while ensuring that derived constraints are correctly propagated, improving convergence toward optimal solutions.
The top-down process is shown in Figure 5a and consists of the following steps:
  • Select the current macromodel under evaluation.
  • If the macromodel contains primitives, generate its corresponding design space.
  • Perform local exploration using predefined parameters and the values obtained from its primitives.
  • Filter the results to ensure compliance with design constraints.
  • If the macromodel contains submacromodels, derive new constraints from the exploration results.
  • Use these derived constraints to explore the submacromodels, repeating the process until the lowest level is reached.
The bottom-up process, which is shown in the Figure 5b, proceeds as follows:
  • Once a macromodel with no submacromodels is reached, return its exploration results to the next level up in the hierarchy.
  • Use the obtained values to update previously predefined parameters in the parent macromodel.
  • Re-optimize the results to meet the derived specifications.
  • If another adjacent macromodel exists, mark it as next and resume the global exploration flow.
This mechanism maintains consistency with system-level constraints by restricting the design space at each hierarchical level based on lower-level results. To avoid exponential growth in parameter combinations, design space filtering is applied using top-down constraints and optimization criteria that prioritize efficiency in power, area, and performance. As a result, the system focuses only on feasible configurations, significantly enhancing exploration efficiency.

3.3. Stage 3: Local Exploration

The diagram of this stage is shown in Figure 6; each macromodel is analyzed individually using its corresponding testbench. The analysis considers both the internal electrical parameters of the block and its hierarchical dependencies with other subcircuits. The process involves two main steps:
  • Symbolic analysis: This step extracts the system of equations that describe the behavior of the testbench using MNA. Solving the resulting linear system enables the explicit definition of the transfer function or any other target equation required for the design objective.
  • Vectorized evaluation: Once the symbolic equations are formulated, all design-space equations are computed in a single batched array operation, treating the parameters set as arrays. This eliminates explicit Python loops and accelerates the exploration.
This stage takes as input the hierarchy tree, which defines the structural composition of the circuit, and the testbenches, which contain the specifications that each macromodel must satisfy. Together, these inputs and processes enable the local optimization of each block within the context of the global design constraints.

4. Implementation

4.1. Context and LDO Architecture

Low Dropout Regulators are a key component of integrated DC-DC power management systems [7]. Unlike switching converters, LDOs provide low-noise, linear regulation, making them essential for powering sensitive analog or mixed-signal blocks within system-on-chip (SoC) designs. Their fully integrated implementation simplifies system complexity and reduces area and electromagnetic interference (EMI), but also imposes stricter constraints on performance metrics such as dropout voltage, power supply rejection ratio (PSRR), and loop stability [24].
A typical integrated LDO, as shown in Figure 7b, comprises three main building blocks:
  • Error Amplifier: Compares the output voltage with a reference and amplifies the error.
  • Pass Element: A power transistor (typically PMOS or NMOS) that regulates the current flow from input to output.
  • Feedback Network and Compensation: Sets the regulation point and ensures stability.
The pass element dominates power efficiency and dropout voltage, while the error amplifier defines loop gain and dynamic response. These blocks must be co-designed to meet the overall specifications under varying load and supply conditions.

4.2. Design Objectives

The design specifications adopted in this work were derived from a review of recent literature on fully integrated DC-DC power management systems. Based on the typical constraints of on-chip analog supplies, a set of target performance metrics was defined to guide the design space exploration and architectural choices [25,26,27].
In addition to numerical specifications, three LDO topologies were selected to validate the flexibility of the proposed methodology:
  • Topology A (Figure 8a): Two-stage amplifier Miller OTA With PMOS pass device.
  • Topology B (Figure 8b): Single-stage amplifier with a basic error amplifier and PMOS pass device.
  • Topology C (Figure 8c): Folded cascode amplifier and PMOS device.
These architectures differ in complexity, stability behavior, and transistor count, making them ideal for testing the generality of the methodology across a range of realistic design challenges. The target design metrics for all topologies are summarized in the Table 1. There are some fixed values such as V i n , V o u t , V r e f , I l o a d , m a x and parameters such as C l o a d in Table 1, which are not design-optimization parameters but design objectives. The rest are also optimization parameters. These optimization parameters were enforced during the automated sizing and evaluation stages of the methodology, and all topologies were tested under the same conditions to ensure comparability across designs and technologies. They were enforced during the automated sizing and evaluation stages of the methodology, and all topologies were tested under the same conditions to ensure comparability across designs and technologies. Due to space constraints, the following implementation analysis focuses on Topology A using the IHP SG13G2 technology. However, the same exploration process is applied to the other two topologies, and evaluating different technologies requires only replacing the LUTs, thanks to the structured and modular nature of the proposed methodology.
Throughout this paper, the term “area” denotes a size metric defined as the width W plus the length L of every transistor, following [12]. This choice emphasizes variations in device sizing during schematic-level exploration of analog circuits, where W L .

4.3. Stage 1 Implementation

In this section the first step of the proposed methodology is implemented. It begins with the decomposition of the LDO into functional blocks, followed by the definition of testbenches for each macromodel, and concludes with the generation of technology-specific Lookup Tables (LUTs).

4.3.1. Modularization

The LDO circuit was decomposed into functional blocks following the structured design methodology introduced in Section 2.1, as shown in the Figure 9. The modularization was performed from the top level, identifying the primary macromodel as the full LDO regulator, which is then divided into three key sub-blocks: the error amplifier, the pass device, and the compensation network. The resistive feedback network is not considered a key sub-module. Its divider ratio is predetermined by the specified output and reference voltages, and the resistor values are set once and kept fixed (not optimization parameters) throughout the exploration.
Each of these sub-blocks was further broken down into sub-macromodels or primitives, depending on their complexity and level of abstraction. For example, the error amplifier includes multiple gain stages and biasing structures, while the pass device and compensation blocks are typically modeled using simpler primitives or fixed-parameter blocks.
This decomposition results in a hierarchy tree that defines the dependencies between blocks and allows recursive execution of the design flow. Local specifications can be defined at each level, enabling targeted exploration and optimization while maintaining consistency with system-level requirements.

4.3.2. Testbenches

To evaluate each macromodel against its target specifications, dedicated SPICE-compatible testbenches were created. These testbenches allow small-signal analysis and ensure that the defined metrics can be extracted automatically during the design space exploration.
Four specifications were selected as primary targets for the main LDO macromodel: PSRR, Dropout, load regulation and phase margin. PSRR was evaluated using a testbench that applies an AC signal at the power supply input in the closed loop configuration, as shown in Figure 10a, Dropout was directly extracted from the pass transistor primitive, load regulation uses the same configuration as PSRR but as the difference between two DC operating points, while the phase margin was measured by breaking the feedback loop using high-value series components ( C o l , R o l ) that preserve DC bias while isolating the loop in small-signal, as shown in Figure 10b.
For the two-stage amplifier macromodel, the testbenches targeted gain, output resistance, equivalent transconductance, and phase margin. Gain and output resistance were measured using distinct small-signal testbenches, while transconductance was computed by dividing gain by output resistance. Each macromodel also includes internal degrees of freedom—electrical variables or parameters not directly defined by the specifications. These variables are swept during the exploration phase to identify feasible operating regions within the allowed design space.

4.3.3. LUT Generation

LUTs were generated for each of the three target technologies. For IHP-SG13G2, low-voltage (1.8 V) NMOS and PMOS devices were used. For Sky130A, low-threshold voltage (LVT) devices at 1.8 V were selected to enhance operation in moderate inversion. In GF180MCU, the lowest-voltage available devices were 3.3 V transistors, as no shorter-channel devices are available at lower voltages.
Device characterization was carried out by sweeping electrical variables while keeping the transistor width W constant, selected to match the expected operating region. Execution times for generating each LUT were 19 s (IHP-SG13G2), 1 min 50 s (Sky130A), and 21 s (GF180MCU). For NMOS vs. PMOS, the only difference in the sweep configuration was the sign of the applied voltages (positive for NMOS, negative for PMOS).

4.4. Stage 2–3 Implementation

To illustrate the operation of the proposed methodology, this section presents a graphical overview of the exploration sequence across the LDO hierarchy. Figure 11 shows the order in which local explorations are performed, as determined by the global exploration process implemented in Stage 2 of the methodology.
In the diagram, each arrow represents a transition between macromodels. When the direction is from a higher-level to a lower-level macromodel, it corresponds to the propagation of specifications. Conversely, arrows from a lower to a higher level indicate the propagation of resolved design parameters back up the hierarchy.
While the figure summarizes the full sequence of transitions, only a subset of key steps will be presented to exemplify how the methodology filters the design space and updates parameters throughout the hierarchy.
The diagram is provided solely as a visual aid, as all transitions and calculations are performed automatically by the flow. The next subsections describe representative transitions that showcase the methodology in action.

4.4.1. Exploration Results

This section presents a selection of key transitions from the LDO hierarchy, each illustrating essential steps of the exploration process. For conciseness, only the most representative transitions are shown, highlighting the hierarchical flow, the propagation of specifications, and the resolution of design parameters.
Transition 1: From LDO to Error Amplifier
The first local exploration is performed on the top macromodel. The exploratory parameters include the OTA output voltage ( V o t a ) and the pass transistor channel length ( L p t ), which define the design space for the pass transistor. Default values for R a and g m a are used in the simplified OTA model.
A total of 45,000 points were evaluated, resulting in a single pass transistor configuration that satisfies the specifications, with dimensions of W = 547 μ m and L = 0.4 μ m. This directly sets unique values for V o t a and the pass transistor input capacitance C i n , eliminating degrees of freedom for these variables in subsequent stages and significantly reducing the design space.
The derived OTA specifications include a minimum gain of 64.4 dB and a bandwidth below 1 kHz. The resulting design space is shown in Figure 12, where it is evident that PSRR, load regulation, and phase margin are strongly dependent on the amplifier’s gain, while the dropout voltage depends exclusively on the pass transistor dimensions.
Transition 2 and 3: From Amplifier to Primitives
The second transition corresponds to the local exploration of the two-stage OTA macromodel, using the specifications defined at the LDO level. In this step, 312,000 points were evaluated, but no additional constraints were derived from this exploration.
Transition 3 initiates the first propagation of the design space within the hierarchy. Since no specific constraints were passed down from the OTA macromodel, the exploration of its first stage, composed of three primitive blocks, was constrained only by the minimum transistor size requirements. The design space was generated based on the exploratory parameters of these primitives, resulting in 825,000 evaluated points, from which only 410 configurations satisfied the sizing constraints. This represents a 99.95% reduction in the number of candidates.
Figure 13 presents the resulting design space for the single-stage OTA, showing the feasible solutions after this substantial reduction.
Transitions 4, 5 and 6: Exploration of Intermediate Blocks
The fourth transition corresponds to a new exploration of the two-stage OTA macromodel, this time incorporating the constraints propagated from the lower levels. From this analysis, new specifications were derived, including a minimum gain of 35 dB for the second stage and a compensation capacitance c o t a constrained between 3.16 pF and 17.8 pF. In the fifth transition, the local exploration of the second gain stage was performed, evaluating 3125 points, of which only 46 configurations satisfied all specifications. The sixth transition explores the combined design space of the two gain stages, consolidating the results obtained so far. A total of 188,600 points were evaluated, with only 19 valid configurations meeting the required constraints. At this stage, the complete design space for the two-stage OTA is fully defined, allowing the amplifier to be reused in other designs if needed.
Figure 14 shows the resulting design space for the two-stage OTA after this exploration and filtering. Note that the hierarchical nature of our LDO design example inherently demonstrates the general-purpose capabilities of the framework. For instance, a two-stage Miller OTA is directly generated by it, and the design space is already shown in Figure 14. This can be generalized to other building blocks that rely on the gm/ID technique, such as different amplifier topologies, various LDO topologies, blocks with different specifications, and larger circuits such as analog front-ends.
Transition 7: Final Resolution of the LDO
Once all subblocks are resolved, the top-level macromodel is validated using the actual values obtained from the primitives. This final transition confirms that the selected configuration satisfies all original specifications, including PSRR and stability.
Figure 15 displays the final filtered solution set for the complete LDO, illustrating how the hierarchical exploration converges to a feasible design that meets all constraints.

4.5. Evaluation of Alternative Topologies and Technologies

As introduced earlier, three LDO topologies were selected to evaluate the generality of the proposed methodology. After completing the full exploration flow for the two-stage OTA architecture, the same process was applied to the remaining two configurations: a single-stage amplifier with cascode differential pair, and a telescopic OTA. All three designs share the same pass device, which was reused without modification across topologies.
The initial experiments were carried out using the IHP SG13G2 technology. In this case, only the two-stage OTA successfully met all design specifications. The other two topologies failed to provide feasible solutions, primarily due to their increased stacking of transistors. This results in reduced voltage headroom across individual devices, especially in operating points with higher output voltage, which compromises gain and saturation conditions.
To evaluate cross-technology portability, the three topologies were also implemented using two additional open-source PDKs: Sky130A and GF180MCU. With Sky130A, once again only the two-stage OTA yielded valid results. In contrast, all three topologies were successfully explored and resolved using GF180MCU. This can be attributed to the use of 3.3 V transistors in this technology, which offer greater flexibility for stacked designs and improve feasibility margins in headroom-limited scenarios.
To summarize the performance trade-offs across topologies and technologies, Figure 16 presents the resulting Pareto frontiers. Each point corresponds to a valid configuration that meets the required specifications. In addition, Table 2 details the optimal points in terms of area for each combination of topology and technology. The results show that:
  • Single-stage OTAs provide higher phase margins due to simpler stability requirements, but generally at the cost of greater area.
  • The two-stage OTA achieves a better balance between stability and compactness.
  • Among the technologies, IHP SG13G2 enables valid designs with minimal area; Sky130A offers a moderate trade-off; and GF180MCU, while requiring more area, supports all topologies thanks to its higher-voltage devices.
These results confirm the scalability and portability of the proposed methodology across both architectural and technological domains.

5. Conclusions

The proposed methodology successfully enabled the automated exploration and sizing of analog integrated circuits using a modular and hierarchical approach. During its application to a complete LDO design, a progressive reduction in the number of evaluated design points was observed at each stage, as shown in Table 3. This result highlights the advantage of combining symbolic modeling and constraint propagation in a structured flow, as opposed to flat or template-based approaches. Furthermore, the final design meets performance targets that are comparable with recent state-of-the-art solutions in the literature, as summarized in Table 4.
In [28], a manual LDO design is presented, based on an internally compensated topology and implemented in UMC 180 nm CMOS technology. The complete design methodology is disclosed in the cited work, and therefore serves as a baseline for specification comparison. In addition, the LDO design results of three automation approaches are included [12,29,30]. Although the employed topologies and process technologies differ across methods (e.g., a simple architecture with Miller OTA in 40 nm CMOS [12], a simple architecture with folded cascode in 130 nm CMOS [12,29], and a digital LDO in 65 nm CMOS [30]), the comparison shows that our generated design provides a balanced solution, achieving the best DC PSRR among the alternatives.
To complement this evaluation, Figure 17 shows the execution times associated with MNA and vectorized evaluation stages. The MNA resolution time remains constant regardless of the number of points, indicating that its complexity depends solely on the circuit topology. In contrast, the evaluation time grows linearly with the number of configurations. This underscores the importance of reducing the number of design points early in the process, which the proposed hierarchical exploration inherently achieves.
For benchmarking purposes, an attempt was made to symbolically resolve the topology used in [12]. Unlike the current methodology, that design does not simplify the circuit before analysis, which significantly increases symbolic complexity. In multiple trials, the symbolic solver failed to produce results within two hours. This suggests the use of high-performance computing resources or alternative methods in that reference, whereas the approach proposed in this work remained efficient using standard open-source tools.
Numerically, both methods achieve comparable throughput during LUT evaluation. However, the number of degrees of freedom plays a critical role; in unsimplified or monolithic topologies, the exponential growth of design points drastically affects runtime. This emphasizes the importance of symbolic simplification and hierarchical modularization as core enablers of scalable analog design automation.
In summary, this work presented a systematic and structured methodology for the automation of transistor-level design in analog circuits, validated through the implementation of LDO regulators across three topologies and three open-source technologies. By combining hierarchical modeling, symbolic analysis, and LUT-based exploration, the methodology enables specification-driven design while avoiding the need for iterative simulations. It allows for module reuse, early pruning of infeasible solutions, and fine-grained control over design complexity.
This framework provides a solid and extensible foundation for scalable analog design automation, and opens the door for future extensions such as layout integration, broader circuit classes, and the incorporation of machine learning to assist in exploration and decision making.

Author Contributions

Conceptualization, D.A., J.M. and C.A.R.; software, D.A. and K.H.; formal analysis, D.A.; investigation, D.A., J.M., K.H. and C.A.R.; resources, C.A.R., J.M., K.H., J.G. and S.W.; writing—original draft preparation, D.A., J.M., C.A.R. and J.G.; writing—review and editing, C.A.R., J.M., J.G., K.H. and S.W.; visualization, D.A., J.M. and S.W.; supervision, C.A.R. and J.M.; project administration, C.A.R., J.M. and K.H.; funding acquisition, C.A.R., J.M., K.H., J.G. and S.W. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by AC3E (ANID/BASAL/AFB240002), by ANID + Fondecyt de Exploración 2025 + 13250147, by ANID + FONDECYT Initiation Research Project 11240947, by ANID + FONDECYT Regular Project 1240537, by ANID/FONDAP/1522A0006.

Data Availability Statement

The original contributions presented in the study are included in the article; further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Primitive table.
Figure 1. Primitive table.
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Figure 2. Primitive simplification example.
Figure 2. Primitive simplification example.
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Figure 3. General flow diagram.
Figure 3. General flow diagram.
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Figure 4. Stage 1 diagram.
Figure 4. Stage 1 diagram.
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Figure 5. Stage 2 diagram. (a) Top-down flow. (b) Bottom-up flow.
Figure 5. Stage 2 diagram. (a) Top-down flow. (b) Bottom-up flow.
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Figure 6. Stage 3 diagram.
Figure 6. Stage 3 diagram.
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Figure 7. LDO context and configuration. (a) LDO operation in a DC-DC system [7]. (b) Basic LDO topology.
Figure 7. LDO context and configuration. (a) LDO operation in a DC-DC system [7]. (b) Basic LDO topology.
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Figure 8. Topologies to be explored. (a) LDO with a two-stage Miller OTA. (b) LDO with a one-stage OTA but a differential cascode. (c) LDO with telescopic OTA.
Figure 8. Topologies to be explored. (a) LDO with a two-stage Miller OTA. (b) LDO with a one-stage OTA but a differential cascode. (c) LDO with telescopic OTA.
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Figure 9. LDO hierarchy diagram.
Figure 9. LDO hierarchy diagram.
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Figure 10. LDO macromodel testbenches. (a) Closed-loop testbench configuration. (b) Open-loop testbench configuration.
Figure 10. LDO macromodel testbenches. (a) Closed-loop testbench configuration. (b) Open-loop testbench configuration.
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Figure 11. Transition flow diagram extracted from global exploration. The numbers represents the order of the transitions.
Figure 11. Transition flow diagram extracted from global exploration. The numbers represents the order of the transitions.
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Figure 12. Design space of the first local exploration. Green dots indicate the points that meet the requirements.
Figure 12. Design space of the first local exploration. Green dots indicate the points that meet the requirements.
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Figure 13. Design space of the local exploration of the OTA’s first stage.
Figure 13. Design space of the local exploration of the OTA’s first stage.
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Figure 14. Design space of the two-stage Miller OTA. Green dots indicate the points that meet the requirements.
Figure 14. Design space of the two-stage Miller OTA. Green dots indicate the points that meet the requirements.
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Figure 15. Final LDO design space. Green dots indicate the Pareto frontiers.
Figure 15. Final LDO design space. Green dots indicate the Pareto frontiers.
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Figure 16. Design space of the different topologies and technologies.
Figure 16. Design space of the different topologies and technologies.
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Figure 17. Timing results of the methodology implementation.
Figure 17. Timing results of the methodology implementation.
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Table 1. Design objectives of the LDO.
Table 1. Design objectives of the LDO.
SpecificationDesign Objective
V i n 1.8 V
V o u t 1.2 V
V r e f 0.9 V
PSRR (100 Hz)<−60 dB
Dropout<400 mV
Load regulation<1 mV/mA
Phase margin>60°
C L o a d 0.5 pF
I L o a d , m a x 5 mA
Current efficiency>98%
W of pass transistor<15 mm
W of amplifier transistors1 μm < W < 200 μm
Table 2. Minimal-area designs.
Table 2. Minimal-area designs.
Topology
Technology
A
IHP
A
SKY
A
GF
B
GF
C
GF
Area [mm]0.600.791.011.121.2
PSRR [dB]−62.08−65.71−76.15−60.05−64.65
Loadreg [ mV mA ] 0.1850.4560.0220.6930.756
Dropout [mV]326.78333.82380.67380.67380.67
Phase Margin [ ] 85.7789.9873.2989.8989.95
Table 3. Evaluated point reduction.
Table 3. Evaluated point reduction.
TransitionNo Before FilterNo After FilterReduction Percentage
1 45,000
2 312,000
3 825,000 410 99.95 %
4 1,281,250
5312546 98.53 %
6 188,600 19 99.98 %
77623 69.7 %
Table 4. Comparison between final design and the state of the art.
Table 4. Comparison between final design and the state of the art.
Specification[28][12][29][30]This Work
Automatic flowNoYesYesYesYes
V r e g (V) 1.8 1 1.2
I L o a d _ m a x 70 mA5 mA10 mA25 mA 5 mA
PSRR@DC (dB) 57 40.02 44.1 62
PSRR@1MHz (dB) 11 20
PM (°)7478.2 58
I Q t o t a l ( μ A)4710398 100
Dropout (mV)35014419780 326
Load regulation (mV/mA) 0.714 2.24 0.35 0.34
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Arévalos, D.; Marin, J.; Herman, K.; Gomez, J.; Wallentowitz, S.; Rojas, C.A. A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics 2025, 14, 3448. https://doi.org/10.3390/electronics14173448

AMA Style

Arévalos D, Marin J, Herman K, Gomez J, Wallentowitz S, Rojas CA. A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics. 2025; 14(17):3448. https://doi.org/10.3390/electronics14173448

Chicago/Turabian Style

Arévalos, Daniel, Jorge Marin, Krzysztof Herman, Jorge Gomez, Stefan Wallentowitz, and Christian A. Rojas. 2025. "A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs" Electronics 14, no. 17: 3448. https://doi.org/10.3390/electronics14173448

APA Style

Arévalos, D., Marin, J., Herman, K., Gomez, J., Wallentowitz, S., & Rojas, C. A. (2025). A Topology-Independent and Scalable Methodology for Automated LDO Design Using Open PDKs. Electronics, 14(17), 3448. https://doi.org/10.3390/electronics14173448

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