Exploring Circuit-Level Techniques for Soft Error Mitigation in 7 nm FinFET Full Adders

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

81 "investigated"
92 "recently shows" fix this grammar
96 "Alsom THE DCELL technique" fix grammar here
105 NV is descibed what is NTV
Why was there a recommnedation to use 3 fin instead of 1 fin
155 "the initial"
156 A charge collection depth of 21nm makes no sense and is not mentioned in the refernce [36] please correct this
How are the devices sized in Figure 2 this is a critical piece of information for udnerstandning the total capacitance at a node and hence the LET sensitivity
Also what is the threshold of these devices it would be good to know if you are lowering the supply how much headroom do we have
Please detail the exact geometry of the pulse you are using in the time domain
Also you give a formula for calcuatling the error rate but not the LETth, that would be more useful. I checked reference 37 and it does mention LETth hwoever there is no formula.
228 what is Table S11 and why is [38] referenced
NTV means "near threshold voltage" is that right? please add near the start of the paper where you define NV
One thing is with these predictive models, what do the models have and don't have for very small sub 10nm processes most of the dominant parasitics both R and C come from the actual metal wiring between devices does the model have a pre-layout estimation or RF model you are using otherwise your parasitics that you are simulating will be off and hence the results off
Another thing though is if you like at the trend of device ft it is increasing until about 32nm, after that ft actually starts to decline across feature size. How would you say this plays into the overall SEU sensitivty if nodal capacitances are actually going up at small feature sizes?
For the current pulse you are using is it actually just a double exponential source? More recent research has found that it is actually a double exponential source followed by more of a hold period and THEN it decays off, please check on this.
Why are you comparing designs with and without buffering on the outputs, all of these would be buffered
Please detail the exact load capactiance that you use for each circuit.
628 "applying the sizing technique to the transistors change the behavior" fix grammar here, also this is why it is key to show the sizing of ALL of the devices in the designs since the entire analysis depends on this
You are not showing in your paper anywhere were DCELL is added and how large it is wouldn't this affect dynamic circuit performance? Why don't we just put 10pF?? This needs to be detailed in your work exactly how much capacitance you are adding.

 

Overall, the authors need to go through the paper and very clearly show exactly what they are modeling. This includes detailing the predictive 7nm model they are using, the current source for the SEU, the LET threshold formula, the SIZING of the devices in the schematics, etc. There are many key things missing from this report to make it a complete analysis that is simulation only.

Author Response

Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

Review Report on the electronics-3714576-peer-review-v1.pdf

This manuscript presents a comprehensive study on radiation-induced soft error mitigation in FinFET-based full adders (FAs) using circuit-level techniques. The work is technically sound, methodologically rigorous, and addresses an important gap in radiation-hardened circuit design. However, several improvements are needed to enhance clarity, depth, and impact. Below are detailed recommendations for revision.

1. The study evaluates three mitigation techniques (DCELL, TS, and combined) across four FA topologies, providing valuable insights for radiation-prone environments.
2. Extensive SPICE simulations and LET threshold (LETth) analysis under nominal/NTV conditions strengthen the findings.
3. The combined DCELL+TS approach shows consistent error reduction (up to 70%), making it useful for aerospace/space applications.
4. Clarify Contributions in Introduction

• Issue: The introduction lists broad goals but lacks a concise summary of key findings (e.g., which topology/technique performs best).
• Fix: Add a paragraph explicitly stating the top-performing FA topology (e.g., Mirror FA with DCELL+TS) and its LETth improvement (3.3×).

5. Justify FinFET Technology Choice

• Issue: While FinFET advantages are mentioned, a comparison with other radiation-hardened technologies (e.g., SOI) is missing.
• Fix: Include a brief discussion in Section 2 (Related Work) on why FinFETs were chosen over alternatives for this study.

6. Expand Methodology Details

• Issue: Section 3 lacks specifics on HSPICE setup (e.g., solver settings, convergence criteria).
• Fix: Add a subsection titled "Simulation Setup" with parameters like reltol, abstol, and pulse injection methodology.

7. Improve Figure Readability

• Issue: Figures 6–11 use small fonts and lack axis labels (e.g., Figure 6: "Total Error" axis units are unclear).
• Fix: Redraw figures with larger fonts, labeled axes, and consistent color schemes. Embed legends directly in plots.
  • Example for Figure 6:

8. Discuss Voltage Scaling Trade-offs

• Issue: NTV operation’s impact on power consumption vs. reliability is not quantified.
• Fix: Add a table comparing power-delay product (PDP) for NV vs. NTV with/without mitigation.

9. Strengthen Critical Node Analysis

• Issue: Section 4.1 identifies critical nodes but does not explain why they are vulnerable (e.g., node "g" in Mirror FA).
• Fix: Add a schematic (e.g., Figure 2a) highlighting sensitive transistors/nodes and their charge collection mechanisms.

10. Address Measurement Limitations

• Issue: Radiation experiments are simulation-only; real-world validation is absent.
• Fix: Acknowledge this limitation in the Conclusion and propose future work with laser/particle beam testing.

11. Standardize Error Rate Presentation

• Issue: Error rates in Tables 1–4 mix percentages and raw counts (e.g., "13% of errors" vs. "21 errors").
• Fix: Use percentages consistently and add a footnote explaining error-count normalization.

12. Compare with Prior Art

• Issue: Table 5 compares topologies but omits prior work (e.g., [30]’s DCELL results).
• Fix: Add a column to Table 5 listing LETth values from recent literature for direct comparison.

13. Clarify Hit-Type Dominance

• Issue: N-hit’s prevalence (Section 4.4) lacks a physics-based explanation.
• Fix: Reference FinFET charge collection asymmetry (e.g., NMOS fins collect more charge) in Section 2.

14. Optimize Tables for Readability

• Issue: Table 1 (LETth for Mirror FA) is overly dense and hard to parse.
• Fix: Split into two tables (NV/NTV) and use heatmap formatting for LETth values.

15. Future Work Suggestions

• Issue: The Conclusion briefly mentions a "radiation-hardened cell library" but lacks specifics.
• Fix: Propose 2–3 concrete steps (e.g., "Extend to 5 nm FinFETs" or "Integrate into EDA tools").

16. Some Minor Revisions

• Grammar/Clarity:
• Fix typos (e.g., "in-fluenced" → "influenced" in Abstract).
• Replace passive voice (e.g., "It was observed" → "We observed").
• Acronyms: Define all acronyms at first use (e.g., "PTL" in Section 4.5).
• References: Update citations to include 2023–2024 papers on FinFET radiation hardening.

Comments on the Quality of English Language

N/A

Author Response

Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The paper discusses about 3 kinds of  mitigation  techniques for 4 kinds of full adders. The paper is interesting. Following are some suggestions for the paper. 

1,  In line 36, there seems a grammar error. "The objective of this work is analyze circuit-level methods aimed at mitigating the  Single Event Transient (SET) effects on a set of four FA circuits considering circuit-level  mitigation strategies. " I think it should be "The objective of this work is to analyze... " or "The objective of this work is analyzing ..." . Could the author please modify the grammar error?

2, In line 119 , there is an expression like this "LET threshold (LETth)," and in line 122 , there is an expression like this "The Linear Energy Transfer  (LET) ", and in line 77, there is an expression like this " the Linear Energy Transfer  (LET) [20]". For abbreviation like "LET", explanation of the abbreviation " Linear Energy Transfer  " appears only once is enough. For example, it appears first time in line 77 , then it is enough. You don't need to repeat the explanation time and again in line 122.  And for other abbreviations , it is also similar. We only need to explain the abbreviations once. Could the author please delete the unnecessary repeated explanation of abbreviations in the paper?

3, The author did a lot of work upon simulation of the 4 kinds of full adders. Could the author please provide some measurement results to verify that your simulation results are reliable? As we know, for chip design, measurement results are pretty important. Post simulation is not enough. 

4, Could the author please provide a comparison of your work with others like in references [7-32], to show advantage and  innovation of your work? 

5. Please improve the English style of the paper. 

Comments on the Quality of English Language

 Please improve the English style of the paper. 

Author Response

Thank you for reviewing our submission. We sincerely appreciate your comments and constructive feedback on our manuscript. Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

Comments for the manuscript of electronics-3714576-R1

The revised paper presents a thorough investigation of radiation effects on FinFET-based full adders, employing robust simulation methodologies with ASAP7 7nm FinFET PDK. The dual-voltage analysis (nominal and near-threshold) provides valuable insights into voltage-dependent vulnerabilities. The focus on aerospace applications and the inclusion of NTV operation analysis addresses critical needs for radiation-hardened, low-power computing systems. All comments and suggestions have been revised.

This manuscript makes substantial contributions to the field of radiation-hardened circuit design and is unconditionally recommended for publication. The work demonstrates:

• Methodological rigor through exhaustive HSPICE simulations
• Novel findings in FinFET radiation sensitivity patterns
• Practical mitigation techniques with quantified improvements
• Comprehensive analysis spanning multiple evaluation metrics

The paper is well-structured, technically sound, and presents findings that will be valuable to both researchers and practitioners in radiation-hardened electronics. The inclusion of detailed simulation parameters (Table 1) and topology comparisons (Table 6) ensures reproducibility and facilitates technology transfer.

However, there are some minor ​suggestions for improvement in final submission as follows.​​

1. The power-delay tradeoff discussion in Section 5.5 could benefit from more explicit design guidelines - perhaps a summary table ranking topologies by application scenario (high-reliability vs. power-constrained).
2. While the supplementary materials are referenced, a brief summary of key additional findings in the main text might help readers appreciate the full scope of results.
3. The conclusion could be strengthened by adding specific recommendations for designers (e.g., "For NTV operation, Mirror FA with combined mitigation is preferred when power allows, while TFA may suit stricter power budgets").

Comments on the Quality of English Language

N/A

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The paper is interesting, and the authors have done a lot of work.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf