Exploring Circuit-Level Techniques for Soft Error Mitigation in 7 nm FinFET Full Adders

Abstract

This work investigates the effects of radiation on FinFET-based full adders, which are crucial components of arithmetic units, particularly in aerospace and space applications. While FinFETs offer significant advantages, they remain susceptible to single-event transients (SETs) induced by radiation, which can cause computational errors. We assess three circuit-level mitigation techniques against SETs in FinFET adders: decoupling cells (DCELLs), transistor sizing (TS), and a combined approach incorporating both methods. Our results demonstrate that the most sensitive nodes and critical vectors in the adders vary depending on the mitigation strategy, underscoring their impact on overall radiation resilience. By analyzing these techniques alongside critical node evaluation, we identify their advantages and limitations, providing insights to enhance the robustness of FinFET-based processors in radiation-prone environments.

1. Introduction

The advancement of technology scaling has made possible the development of more efficient and sophisticated electronic devices [1]. This progression enables higher transistor density per die. As a result, it has increased computational capability while reducing the overall area, consequently driving down the costs associated with integrated circuits. However, as voltage operation and device size are scaled down, electronic components become increasingly vulnerable to radiation-induced interference. This phenomenon significantly impacts their reliability and performance in electronic systems [2]. This vulnerability even affects new technologies, such as multigate devices, which are proposed to continue the miniaturization of devices, overcoming the more critical short-channel effects faced by bulk CMOS devices.

This susceptibility to radiation is particularly relevant when considering Single Event Effects (SEE), which occur when energetic particles from space or terrestrial noise interact with silicon. With the advent of nanometer technologies, the minimum charge required to induce a Soft Error decreases. This reduction can be attributed to factors such as decreased nodal capacitance, lower supply voltages, and higher-frequency operations.

One of the most crucial components in computer systems is the FA [3]. The FA is generally part of the critical path in most systems, making this digital component a strong influence on the overall performance of the entire system. Despite the FA’s relevance, most of the reliability research focuses on the radiation effects on memory cells [4,5,6,7,8,9,10], and few studies have evaluated circuit-level mitigation strategies for robust FA design [11].

The objective of this work is to analyze circuit-level methods aimed at mitigating the Single Event Transient (SET) effects on a set of four FA circuits by considering circuit-level mitigation strategies. Additionally, this work provides information about the robustness to radiation and the susceptibility of SET for the selected FA topologies. It will consider how input vectors and current pulse types influence these aspects across different voltage operations. This article is a revised and expanded version of a paper entitled Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing, which was presented at the Symposium on Integrated Circuits and Systems Design (SBCCI), 2022 [12,13]. The main contributions of this work are as follows:

• To explore radiation sensitivity across two voltage operation scenarios.
• To assess the efficacy of two circuit-level techniques for mitigating the effects of SETs.
• To demonstrate the mitigation tendency when different radiation particle characteristics are integrated into circuit-level design.
• To provide an overall comparison between all techniques employed in this discussion.

These contributions will underscore the critical importance of topology selection and mitigation strategy for improving the SET radiation tolerance. The combined application of DCELL and Transistor Sizing consistently yields the highest error reduction and LETth improvements across all topologies. Notably, the Mirror FA emerges as the top-performing topology under combined mitigation at near-threshold voltage (NTV), achieving the highest Linear Energy Transfer (LET) threshold improvement of nearly 3.30×. While the Hybrid FA demonstrates greater robustness than Mirror FA when using Decoupling Cell alone, Mirror FA robustness is still superior when applying Transistor Sizing or combined techniques. This paper brings a related work review in Section 2. Section 3 describes the methodology adopted in the evaluation environment. Next, Section 4 discusses how the SET affects the nominal behavior of the four FA topologies regarding critical node, error rate, input vector sensitivity, and radiation-induced pulse. Section 5 analyzes the effects of introducing the circuit-level mitigation approaches. Finally, Section 6 underlines the most relevant observations.

2. Related Work

The main types of radiation effects that digital circuits experience are Single Event Effects, Total Ionizing Dose (TID), and Displacement Damage (DD) [14]. A SEE occurs when a strongly ionizing particle impacts a material, resulting in an energy pulse within the material. These effects are categorized as either destructive or non-destructive [15]. Destructive effects permanently impair circuits [16,17]. Conversely, non-destructive effects do not cause permanent damage but can alter information within combinational circuits, leading to SET, or within sequential circuits such as memory devices, causing Single Event Upsets (SEU) [2]. The advancement of computing architectures, enabled by smaller, faster, and more affordable microelectronic components, has led to the fabrication of increasingly capable systems. However, the decreasing charge representing stored information and the associated voltage scaling have heightened the susceptibility of CMOS devices to SEE.

Multigate devices have been introduced to address short-channel effects [18] and provide relevant mechanisms to mitigate the continuous transistor scale reduction. Among different multigate devices [19,20,21,22,23,24], one of the most common is the FinFET, mainly due to the similarity of the manufacturing process with conventional planar technologies. The FinFET structure is a 3D device with a vertical fin-like structure that allows better control of electrical current flow. Various manufacturing methods exist for FinFET devices, including Silicon-On-Insulator (SOI) FinFET and bulk FinFET. Figure 1 illustrates the comparison between FinFETs implemented on conventional wafers, SOI, and bulk with insulator. Bulk FinFET utilizes the triple gate model [25]. In this design, the fins share the same silicon substrate, as illustrated in Figure 1a. The decision to employ bulk FinFETs was motivated by lower manufacturing costs and the application of the planar CMOS fabrication model, despite having slightly lower electrical characteristics compared to SOI FinFETs. In contrast, SOI FinFETs feature physically isolated fins achieved by an oxide layer, as seen in Figure 1b. Additionally, bulk FinFETs can be constructed with a dense insulator to prevent inversion between the fins, as shown in Figure 1c.

Despite the FinFET attractive attributes for mitigating radiation-induced soft errors, due to the restrictive charge collection mechanism in the fin [27,28], it is essential to recognize that SEE still has the potential to deposit enough amount of energy required to induce a soft error. This energy is quantified by the LET [29]. Even more relevant is to consider low-power constraints, mainly for aerospace applications. The traditional voltage reduction strategy may impose side effects such as lowering frequency operation, increasing leakage power, and increasing the sensitivity of soft errors. FinFET technology was selected in this work to evaluate the impact of radiation effects on advanced nanometer technology nodes, primarily due to the availability of an open-access process design kit, the ASAP 7 nm [30]. It is important to emphasize that, although FinFET devices offer improved short-effects channel control and reduced dopant concentration, radiation-induced effects remain non-negligible in multi-gate architectures. Similar concerns may extend to other radiation-hardened technologies, such as SOI devices. However, most of these are proprietary nodes with restricted access, limiting their use for open research. The adoption of the ASAP 7 nm FinFET technology enables future studies to reproduce our experiments and perform fair comparative evaluations.

This underscores the importance of examining SET effects on FA circuits for radiation-sensitive applications. Some researchers have presented discussions about a variety of FAs using different logic styles [3] proposed for performance and power-efficiency. Other works have investigated the impacts of process variability on the performance and power, and explored mitigation strategies to deal with it [12,31,32,33]. However, we identify a few contributions about the SET effects on multigate FA circuits other than our previous initial evaluation of radiation effects on a FinFET-based Mirror FA topology [11,13]. On the other side, SEE effects have been deeply studied for individual devices or SRAM cells [28,34,35,36,37,38], flip-flops [39,40], and sets of basic combinational cells [41,42]. However, as far as we know, there is a lack of evaluation of circuit-level strategies to mitigate the radiation robustness of FinFET-based full adders.

Schmitt-trigger (ST)-based approaches show a large impact on leakage power and dynamic power [33,41]. Similar to the Schmitt-trigger circuit, the DCELL technique was initially created to improve noise [43] and reduce SEE [44]. However, DCELL-based approaches have recently shown potential to process variability mitigation on digital designs, with minimal impact on area and power [43]. The DCELL technique was used to filter the SET pulses generated by low energy particles in a set of logic gates designed in a 130 nm bulk CMOS digital library [44], and presented as a potential approach to mitigate process variability effects on a set of basic logic gates [41].

3. Methodology

This work aims to evaluate the sensitivity of full adder circuits, observing the impact of SET faults. To achieve this, the work compares a selected group of well-known full adder designs: Mirror, Hybrid, TFA, and TGA topologies. These topologies were previously analyzed in the literature for their susceptibility to process variability [32]. FA topologies based on elementary gates were not included in this evaluation because designs using such gates tend to occupy significantly larger area, for example, a full adder implemented with elementary gates typically requires about 42 transistors, impacting also delay, and power consumption. Figure 2 provides a visual summary of the methodology described above, outlining each stage of the process. In this work, these topologies are evaluated under two distinct voltage conditions: nominal voltage (NV) and near-threshold voltage, allowing for a comprehensive understanding of their SET robustness under typical and voltage-constrained scenarios. The next subsections detail the simulation setup.

3.1. Simulation Setup

Initially, the chosen full adder topologies are described and implemented within the SPICE simulation environment. The circuits were simulated with the 7 nm ASAP7 model [30].

Table 1. The main parameters of the electrical simulation.

Parameter		Value
Gate Length (LG)		21 nm
Fin Width (WFIN)		6.5 nm
Fin Height (HFIN)		32 nm
Oxide Thickness (Tox)		2.1 nm
Channel Doping		$1\times {10}^{22}{\mathrm{m}}^{-3}$
Source/Drain Doping		$2\times {10}^{26}{\mathrm{m}}^{-3}$
Threshold Voltage	NFET	0.35–0.40 V
	PFET	0.40–0.45 V
Work Function	NFET	4.3720 eV
	PFET	4.8108 eV
Voltage	Nominal	0.7 V
	Near-Threshold	0.35 V
Temperature		25 °C

presents the main parameters adopted in the electrical simulation. The first eight lines present the electrical and physical parameters for the 7 nm FinFET devices [30]. The voltage and temperature parameters define the environmental conditions adopted in the experiments. The nominal operation adopts the nominal voltage for Low Voltage Technology (LVT) devices (0.7 V) and the NTV (0.35 V). We are adopting the low-voltage LVT device model from the ASAP 7 nm PDK [30]. Considering the typical process corner, the threshold voltage values are between 0.35 V and 0.40 V for NFET devices and between 0.40 V and 0.45 V for PFET devices [30]. To emulate a realistic input slope, we insert two inverters in the input signals. The load capacitance is set to correspond to a fanout of 4 (FO4), providing a standardized and consistent output condition that allows us to isolate the intrinsic behavior of each full adder design without the added complexity of carry propagation effects from cascaded stages.

The transistor sizing adopted in the experiments with the standard full adder topologies, i.e., without any mitigation technique, is configured to all transistors on all circuits adopting the minimum size of 1-fin. This condition is assumed despite the recommendation of using a minimum of 3-fin transistors presented in the 7 nm ASAP PDK for ensuring internal cell routing adopted in the basic 3-fin NMOS and PMOS standard cell architectures of this PDK [30], in order to represent the critical scenario for robustness tests.

3.2. SET Simulation and Evaluation

In the second step, electrical simulations are conducted to obtain important metrics such as LET threshold (LETth), total error propagated, and error rate for each node. Using the HSPICE tool, a series of electrical simulations is conducted for each topology operating at both NV and NTV levels. These simulations represent the default condition of the circuits before any fault mitigation techniques are applied. This stage is crucial for identifying the most critical internal nodes within each circuit—those most susceptible to SET-induced disruptions—as well as determining the critical current levels required to generate a SET event. These insights form the foundation for developing targeted mitigation strategies.

When an energetic particle hits a transistor junction, the impact triggers the charge collection mechanism of the device, collecting charge while the particle tracks into the depletion region [27]. As an approximate metric, we have assumed that the collected charge is approximately equal to the deposited charge, based on the Linear Energy Transfer (LET) of the particle and the collection depth. In our work, we define the SET pulse as the voltage glitch occurring at the output of a logic gate, which is influenced by the quantity of deposited charge. Within our analyzed circuits, the transistor demonstrates sensitivity to charge collection when it is reverse-biased and when there exists a low-resistance path between the affected node and the output. Depending on the location of impact from the incident ion, there are two types of single-event hits: n-hit and p-hit. An n-hit results in a high-to-low transition at the sensitive node and typically occurs at nodes connected to NMOS transistors, where the node is normally held high. In contrast, a p-hit causes a low-to-high transition and typically occurs at nodes connected to PMOS transistors, where the node is normally held low [45]. The pulse can be modeled as a low-to-high (010) transition to reflect p-hits or a high-to-low (101) to n-hits.

The radiation effect of a particle hitting at the junction of a device is described as a double exponential transient pulse in this work, adopting the equation model defined in [46,47,48]. The charge deposition mechanism proposed in [49] is widely used to form a current source whose behavior is modeled as a double exponential. The modeling of the transient current is given by Equations (1)–(3), where ${\mathrm{Q}}_{COLL}$ is the collected charge due to a radiation particle strike, ${\tau }_{\alpha }$ is the collection time constant of the junction, and ${\tau }_{\beta }$ is the ion track establishment time constant, and L is the charge collection depth that decreases with the technology scaling. For every 1 MeV·cm²/mg, an ionizing particle deposits about 10.8 fC of electron-hole pairs along each micron of its track [50]. Equation (4) presents the LET equation obtained from the previous equations. In this work, the geometry of the pulse that we are adopting in the experiments are a double exponential pulse, where the collection time constant is set to 200 ps, the initial constant time is set to 10 ps [10,48]. Due to differences in the charge collection mechanism of FinFET devices [51], we adopt the gate length of the fin as the charge collection depth restriction. Thus, the charge collection depth for the FinFET devices in these experiments is set to 21 nm, which is the gate length of the adopted devices. A comprehensive evaluation of the charge mechanism for FinFET devices is discussed in [28], presenting some levels of differences in charge collection between NMOS and PMOS, which can influence the n-hit and p-hit on the evaluated circuits. The fault simulation is performed at the circuit level using HSPICE, and the radiation pulse is introduced as an independent current source at the target junction of the device, which is represented by a circuit node in the simulation and evaluation. The current value is increased at 0.5 $\mathsf{\mu }$A step to determine the minimum current to provoke the unexpected behavior on one of the FA outputs.

$$I_P\left(t\right)=I_0\times (e^{-{\displaystyle \frac{t}{{\tau }_{\alpha }}}}-e^{-{\displaystyle \frac{t}{{\tau }_{\beta }}}})$$

(1)

$$I_0={\displaystyle \frac{Q_{COLL}}{({\tau }_{\alpha }-{\tau }_{\beta })}}$$

(2)

$$Q_{COLL}=10.8f\times L\times LET$$

(3)

$$LET={\displaystyle \frac{I_P\left(t\right)\times ({\tau }_{\alpha }-{\tau }_{\beta })}{10.8f\times L\times (e^{-\frac{t}{{\tau }_{\alpha }}}-e^{-\frac{t}{{\tau }_{\beta }}})}}$$

(4)

The experiments involve determining the minimum current required to induce an output flip in the circuit, which is then used to calculate the minimum LET, i.e., the LET threshold. The experiment is stopped when the simulation requires a LETth value greater than 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ (in this case, the node is considered robust). The circuit-level abstraction with electrical simulations allows us to evaluate all internal nodes and all input vectors, observing the fault propagation to each output function of the FA. The error susceptibility rate is the relation between the number of errors per node (or vector) and the total errors observed on the circuit. Thus, this metric is adopted to evaluate the robustness of an under-evaluation cell.

In our investigation of SETs in FA circuits, understanding the distribution of errors across different nodes is vital for pinpointing vulnerable areas and devising effective mitigation strategies. The formula used to calculate the error rate is presented in Equation (5), providing an error rate analysis with respect to the input vector. This expression involves two key variables: $E_n$, which represents the total errors found for a specific node, and $E_{total}$, which signifies the total errors observed in the entire topology. The error rate is determined by calculating the ratio of errors at the specific node. This ratio is then multiplied by 100 to express the result as a percentage. The resulting $E_r$ represents the proportion of errors attributed to the specific node in relation to the total errors observed in the topology.

$$E_r={\displaystyle \frac{E_n}{E_{total}}}\times 100$$

(5)

By analyzing the impact of each input vector, it becomes possible to identify specific combinations that are more prone to generating errors. This information is important for localizing and understanding the sources of errors within the circuit.

3.3. Insertion of Mitigation Techniques

In the fourth stage of the work, specific fault mitigation techniques are applied at the circuit level to enhance the radiation robustness of the full adder topologies. After integrating these techniques into the original circuit designs, a second round of HSPICE simulations is performed, again at both NV and NTV, to observe the impact of the changes.

To mitigate the impact of radiation, three distinct approaches are employed: DCELL [43,44], TS, and a combined strategy utilizing both DCELL and TS. The techniques employed include the DCELL approach, which is applied exclusively to the same target node used for the particle strike injection in each topology, and transistor sizing, which is applied to all devices in the investigated topologies during the simulation tests. The DCELL circuit adopted in the experiments is the circuit described in [44], with all the devices with the minimum number of fins, i.e., with 1 fin. The transistor sizing technique is applied uniformly across all devices, increasing the number of fins to 3. When combining DCELL + TS, the devices on the DCELL are also sized to have 3 fins. The implementation of these techniques involves incorporating specific modifications into the SPICE descriptions of the transistor network constituting the evaluated FA circuit. These tailored modifications precede the rerun of simulations to assess the effectiveness of each mitigation technique. Subsequently, the results derived from applying these techniques are examined and discussed to evaluate their impact on enhancing the circuit’s resilience against radiation-induced effects.

The final stage of the study centers on analyzing the results obtained after the mitigation techniques have been applied. This analysis evaluates the effectiveness of each technique in enhancing circuit robustness by increasing LETth, reducing the total number of errors, and lowering the error rate. Through this comprehensive evaluation, the study provides valuable insights into the comparative resilience of the selected full adder topologies and the effectiveness of specific mitigation strategies in enhancing their fault tolerance.

4. Results Analysis

The evaluation of radiation sensitivity begins by testing the circuits at their nominal voltage and subsequently at near-threshold voltage. Throughout this process, LETth values exceeding 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ are used to identify nodes that are not sensitive to single-event transients (SETs). Figure 3, Figure 4, Figure 5 and Figure 6 illustrate the LETth values for various circuit nodes, highlighting those deemed critical due to their notably low LETth values. These figures visually represent the data provided in the tables available in the Supplementary Material, reinforcing the analysis and facilitating interpretation. The Supplementary Material provides a complete data generated for all the evaluations that we present here. By focusing on these critical nodes, the analysis provides valuable insights into potential vulnerabilities in the circuit’s radiation tolerance, forming the basis for developing targeted mitigation strategies to enhance overall system reliability.

4.1. Critical Nodes

In the Mirror full adder, nodes g, and j exhibit the lowest LETth value of 14 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, indicating high sensitivity to radiation-induced effects. These internal nodes are particularly critical due to their greater vulnerability compared to others, especially output nodes. Nodes c, f, h, i, k and l show moderate sensitivity, with LETth values ranging from 19 to 20 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, as

Table 2. LETth for all nodes of Mirror FA at nominal voltage ($\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$). Robust results are indicated by (-) representing the cases where the LETth values are over 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. Critical values are highlighted in red.

Pulse	Input	Nominal
		a	b	c	d	e	f	g	h	i	j	k	l	Sum	Cout
010	000	-	-	-	-	-	-	-	-	-	-	97	-	45	45
	001	-	-	-	-	-	-	-	96	-	-	67	97	-	45
	010	-	-	-	-	-	-	-	-	-	-	52	59	-	45
	011	-	-	-	-	-	27	-	-	47	-	-	-	45	-
	100	-	-	-	-	26	-	-	-	-	-	98	-	-	45
	101	27	-	-	-	-	27	-	-	48	-	-	-	45	-
	110	51	27	-	-	-	27	-	48	-	-	-	-	45	-
	111	-	-	-	-	-	60	-	-	-	-	-	-	-	-
101	000	-	-	-	42	21	46	14	89	-	14	20	40	-	-
	001	-	41	-	-	26	20	27	20	-	47	52	59	37	-
	010	-	41	-	26	26	20	27	97	-	47	97	-	37	-
	011	83	-	39	85	53	-	20	-	-	-	71	-	-	37
	100	41	-	-	-	78	21	27	96	20	47	66	97	37	-
	101	-	-	40	-	83	-	20	-	-	-	20	20	-	37
	110	-	-	39	55	43	-	20	-	-	-	20	-	-	37
	111	-	-	19	-	80	-	19	-	-	-	27	48	37	37

highlights. While less vulnerable than g and j, disruptions at these nodes can still impact the circuit’s correctness. Output nodes Sum and Cout present significantly higher LETth values of 37 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, suggesting lower sensitivity to SETs. This reduced vulnerability may stem from output loading effects that help attenuate transient glitches and prevent error propagation. Figure 3b further highlights g and j as the most SET-sensitive nodes, under reduced voltage operation. Lowering the supply voltage leads to a 14-fold degradation in their LETth, dropping from 14 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ under nominal conditions to just 1 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ at NTV operation, presented in Table S9. These findings underscore the importance of targeting mitigation strategies at these critical internal nodes to enhance the robustness of the Mirror FA.

In the Hybrid full adder, node c is identified as the most sensitive under nominal voltage operation, as

Table 3. LETth for all nodes of Hybrid FA considering worst fault propagation at nominal voltage ($\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$). Robust results are indicated by (-) representing the cases where the LETth values are over 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. Critical values are highlighted in red.

Pulse	Input	Nominal
		a	b	c	d	e	f	g	h	i	j	Cin	Sum	Cout
010	000	51	-	-	-	-	-	-	-	-	-	-	45	45
	001	78	-	-	-	-	-	-	-	-	26	-	-	45
	010	-	-	-	-	-	29	62	59	-	64	-	-	45
	011	-	96	26	26	27	25	66	47	-	-	-	45	-
	100	-	29	-	-	-	30	-	59	54	65	-	-	45
	101	-	25	26	-	27	25	-	47	69	-	-	45	-
	110	65	-	-	49	26	-	-	-	46	-	-	45	-
	111	73	-	49	49	49	-	-	-	46	31	-	-	-
101	000	-	-	-	39	20	59	-	38	38	24	-	-	-
	001	-	-	8	39	20	51	-	94	38	-	-	36	-
	010	20	-	40	59	20	-	19	20	96	-	-	36	-
	011	28	-	12	14	-	-	28	-	-	39	-	-	36
	100	19	12	40	-	20	-	91	20	20	-	-	36	-
	101	28	13	12	-	-	-	-	-	-	39	-	-	36
	110	-	19	-	21	-	85	-	-	-	20	-	-	36
	111	-	20	19	19	-	58	-	-	-	-	-	36	36

shows, with a lowest LETth value of 8 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. This highlights its critical role and heightened susceptibility to SETs. Nodes b and d also show notable vulnerability, with LETth values of 12 and 14 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, respectively, indicating a significant risk of radiation-induced errors despite being more resilient than node c. All other nodes demonstrate moderate sensitivity, with LETth values above 20 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, suggesting a reasonable tolerance to SETs.

Under NTV operation, as expected, the internal nodes of all evaluated full adders show increased sensitivity under low-voltage conditions. The Hybrid FA sensitivity is depicted in Figure 4b. Most nodes, including b, c, and d, reach a critical LETth value of 2 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, further confirming their vulnerability. In contrast, nodes Sum, Cout, and especially Cin display significantly higher LETth values, with Cin maintaining a value above 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ and emerging as the least critical node, as shown in Table S11 from Supplementary Material. This consistent resilience of Cin across voltage levels suggests a unique robustness within the topology. The use of a combination of complementary logic and pass-transistor logic (PTL) likely contributes to this vulnerability, indicating that this design approach may not be ideal for applications in radiation-prone or noisy environments. Based on these results, nodes b, c, and d are prime candidates for targeted mitigation techniques to improve the radiation tolerance of the Hybrid FA under both nominal and NTV operations.

The radiation-induced error analysis of the TGA FA reveals critical vulnerabilities in specific nodes, particularly under varying operating voltages, as

Table 4. LETth for all nodes of TGA FA considering worst fault propagation at nominal voltage ($\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$). Robust results are indicated by (-) representing the cases where the LETth values are over 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. Critical values are highlighted in red.

Pulse	Input	Nominal
		B	b	A	d	Cin	f	g	h	Sum	Cout
010	000	45	-	48	-	47	-	28	-	28	27
	001	45	-	48	-	-	-	28	-	-	27
	010	-	47	46	-	47	-	-	46	100	28
	011	-	48	45	-	-	47	-	47	28	-
	100	46	-	-	-	47	-	-	45	100	28
	101	46	-	-	-	-	47	-	55	28	-
	110	-	54	-	46	47	-	27	-	28	-
	111	-	54	-	47	-	-	28	-	-	-
101	000	-	39	-	-	-	-	-	39	-	-
	001	-	39	-	-	38	95	-	40	21	-
	010	36	82	-	38	-	37	22	89	21	-
	011	36	80	-	37	37	-	22	89	90	21
	100	-	52	38	96	-	37	22	91	21	92
	101	-	56	42	-	37	-	24	90	90	21
	110	38	-	38	-	-	-	88	39	-	21
	111	38	-	38	-	38	95	88	52	21	21

highlights. At NV, the nodes associated with the primary outputs, Sum and Cout, exhibit the lowest LETth values, measured at 22 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. This identifies them as the most susceptible to SETs, making them the dominant contributors to the circuit’s soft error rate. Node g also demonstrates comparatively low LET values, further highlighting its potential as a critical site for radiation-induced disruptions. This behavior contrasts with more robust internal nodes such as h and b, which show significantly higher LET thresholds, indicating enhanced resilience to transient faults.

A distinguishing factor in this increased vulnerability, particularly at the output stage, is the lack of buffering and the reliance on Pass Transistor Logic in the TGA topology. These design choices reduce signal drive strength and noise margins, rendering output nodes more sensitive to ionizing particle strikes. This is in contrast to other adder architectures, where internal logic nodes typically dominate in terms of criticality.

When the TGA adder operates at NTV, the susceptibility to radiation effects escalates dramatically, illustrated in Figure 5b. A sharp reduction in the critical LET threshold is observed, dropping from 22 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ to just 2 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, representing over a 21× increase in sensitivity for the same critical nodes. Notably, the Sum and Cout nodes remain the most vulnerable, preserving their critical status under NTV; values are presented in Table S13 from Supplementary Material. In addition, node g also emerges as a critical node under these conditions, reaching the same low LET threshold. As illustrated in Figure 5b, the transition to NTV operation amplifies the effects of design limitations inherent in the TGA architecture. The findings emphasize the necessity of reconsidering output stage design, potentially through the inclusion of radiation-hardened buffers or alternative logic styles, when deploying the TGA full adder in radiation-prone or ultra-low-power environments.

The analysis of the TFA FA under radiation exposure highlights Sum as the most critical node, exhibiting the lowest LET threshold of 14 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ at nominal voltage, shown in

Table 5. LETth for all nodes of TFA FA considering worst fault propagation at nominal voltage ($\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$). Robust results are indicated by (-) representing the cases where the LETth values are over 100 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. Critical values are highlighted in red.

Pulse	Input	Nominal
		B	b	A	Cin	e	f	Sum	Cout
010	000	55	-	55	47	34	-	28	27
	001	51	-	47	-	29	-	-	27
	010	-	44	48	47	-	43	-	28
	011	-	43	45	-	83	47	27	100
	100	47	-	-	41	-	42	-	28
	101	46	-	-	-	84	47	27	-
	110	-	53	-	47	29	-	28	-
	111	-	48	-	-	27	-	-	-
101	000	-	-	-	-	-	-	-	-
	001	-	-	-	37	-	46	21	-
	010	39	97	-	-	21	85	14	-
	011	37	92	-	38	19	-	-	21
	100	-	67	40	96	23	85	14	93
	101	-	65	40	38	23	-	-	21
	110	37	-	38	-	-	52	-	21
	111	37	-	38	37	-	67	21	21

. This low value indicates a pronounced vulnerability to single-event transients (SETs) and identifies Sum as the primary contributor to radiation-induced faults in the circuit. In addition, nodes e and Cout also emerge as critical, with LET thresholds of 19 and 21 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, respectively. These relatively low values suggest that these nodes are particularly susceptible to ionizing particle strikes, posing a significant threat to the circuit’s reliability. In contrast, nodes b and f exhibit notably higher LET thresholds of 43 and 42 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, respectively, indicating a more robust behavior under radiation. These nodes are less likely to propagate transient errors, thus contributing to the overall resilience of the TFA topology.

The LET threshold for Sum at NTV drops from 14 to just 1 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, marking a 14× increase in vulnerability, with values presented in the Supplementary Material in Table S15. Moreover, while Cout was already identified as moderately vulnerable at NV, it now becomes a critical node at NTV, also showing a reduced LET threshold of 2 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$. These trends are visually captured in Figure 6.

These findings suggest that while certain nodes within the TFA design exhibit natural resilience, others, particularly the outputs, demand targeted mitigation strategies, such as hardened logic or buffer insertion, to ensure reliable operation in radiation-prone or ultra-low-power environments.

This sensitivity analysis not only informs us about vulnerability in specific nodes but also sets the stage for further exploration into mitigation strategies tailored to enhance the robustness of these critical nodes. As we delve deeper into our study, we aim to correlate these critical nodes with observed errors and Pattern routing investigate potential circuit-level techniques to mitigate the impact of SETs on each FA topology.

4.2. Error Rate

Based on the total error analysis for each node, we can identify the most and least sensitive nodes. The total error is indicative of the robustness of each node in the face of faults, with lower values signifying less sensitivity. The analysis of LETth for the four evaluated FAs provides critical insights into the sensitivity of individual nodes to transient errors under both nominal and NTV conditions. Under nominal voltage operation, the Mirror FA node k exhibits the highest susceptibility to error generation, accounting for approximately 12% of all observed transient faults, presented in Table S1. This highlights its pivotal role in the overall fault profile of the Mirror FA topology. Other nodes, including e, f, g, l, Sum, and Cout, also demonstrate moderate sensitivity, each contributing between 8% and 9% of the total error occurrences. These nodes are notably affected by variations in input pulse conditions. Nodes that are topologically distant from the outputs tend to be more resilient against transient faults. This increased robustness can be attributed to the ability of the transistor network to attenuate signal glitches, particularly in nodes driven by multiple transistors. For example, nodes b, c, i, and j exhibit lower fault sensitivity, indicating an inherent resistance to error propagation. When operating at NTV, the total number of transient faults increases significantly, by approximately 19%, compared to nominal conditions, as shown in Table S9 from Supplementary Material. Notably, node a, which was relatively robust at nominal voltage, becomes substantially more error-prone under NTV, contributing to around 11% of all computed errors. Furthermore, nodes d, h, and i also emerge as significant contributors to output interference at NTV, revealing shifts in the error distribution profile due to voltage scaling. In summary, node k plays a central role in fault susceptibility under nominal conditions, while nodes e, f, g, l, Sum, and Cout exhibit moderate sensitivity to transient errors. In contrast, nodes farther from the outputs, such as b, c, i, and j, demonstrate higher resilience, likely due to glitch attenuation along their paths. At near-threshold voltage, previously resilient nodes like a becoming significantly more error-prone. Errors more frequently propagate to the Sum output, indicating that the internal structure offers greater protection to the Cout path.

On the Hybrid FA under NV, nodes c and d emerge as the most sensitive components, showing the highest probabilities of generating transient faults, as presented in Table S3 from Supplementary Material. Nodes a, e, f, h, i, j, Sum, and Cout demonstrate similar, moderately sensitive behavior, contributing comparably to the overall error profile. Notably, node Cin displays exceptional robustness, with zero observed errors across all evaluated pulse scenarios, suggesting its fault resilience is context-independent. These findings offer a comprehensive perspective on fault propagation paths within the Hybrid FA and provide a foundational basis for exploring fault mitigation strategies to reinforce its most vulnerable nodes. As shown in Table S11 from Supplementary Material for the Hybrid FA evaluated under NTV conditions, nodes a, b, d, f, and g exhibit substantial sensitivity to soft errors, each contributing close to 10% of the total fault occurrences. Among these, node d stands out as the most vulnerable, responsible for approximately 12% of all recorded errors at NTV. Collectively, these five nodes account for nearly 50% of total transient faults, marking them as critical points of failure. Furthermore, a comparison with nominal voltage results highlights a significant increase of 33% in total error occurrences at NTV. Overall, the Hybrid FA demonstrates a diverse sensitivity profile across different nodes, with node d consistently ranking among the most susceptible at both voltage levels. While some nodes maintain moderate fault sensitivity, the sharp rise in error rates under NTV—particularly among nodes a, b, d, f, and g—emphasizes the need for topology-aware fault mitigation strategies. The robustness of node Cin remains noteworthy, serving as a potential architectural reference for designing more resilient logic paths.

The LETth analysis of the TGA FA highlights nodes b, h and Cout as the most vulnerable under both nominal and NTV conditions, jointly contributing to about 39% of all transient faults. This emphasizes their critical role in error propagation within the TGA topology. Unlike other FA configurations, TGA shows reduced output-level robustness, with Sum being more prone to SETs than many internal nodes. Additionally, nodes Sum and g show moderate sensitivity that varies with input pulse conditions. Although node Sum may appear less sensitive in specific cases (e.g., under pulse 001), its cumulative fault contribution confirms its criticality in the overall fault profile. When operating under NTV conditions, the TGA FA experiences a substantial degradation in reliability, with a 39% increase in total error occurrences compared to nominal voltage, as shown in Table S13. In this scenario, node h emerges as error-prone, exhibiting a slight increase in sensitivity—approximately 1% more than nodes Cin and Cout. Despite this shift, nodes h and Sum remain among the most critical contributors to overall errors. Furthermore, nodes Cout and e display a notable increase in sensitivity under NTV, warranting their inclusion in the critical node set for fault mitigation considerations. These findings indicate that the TGA FA topology is particularly vulnerable at the output nodes, with h and Cout consistently ranking as the most sensitive components under both voltage regimes. Nodes b, g, and Cout show moderate to high sensitivity, depending on the operating condition and pulse pattern. The significant rise in error rates at NTV, particularly from nodes b, h, and Cout, highlights the necessity of robust fault-tolerant design strategies to ensure reliable operation in low-voltage environments.

Similar to the behavior observed in the TGA topology, one of the most vulnerable nodes in the TFA design is the output node Cout, which consistently emerges as a critical point of failure, as results presented in Table S7 from Supplementary Material. This recurring sensitivity in output nodes across both topologies may stem from the lack of buffering at the output stage, as suggested by the structural layouts in Figure 6. At nominal voltage, nodes e and Cout each account for approximately 14% of the total error count, indicating a high level of fault sensitivity. Additionally, nodes positioned near the outputs show elevated susceptibility, with error rates that in some cases approach those of the most critical nodes. The behavior of node Sum is notably variable, exhibiting sensitivity that fluctuates depending on the input pulse scenario, thereby highlighting the need for a context-specific assessment to fully understand its role in transient fault propagation. Under NTV operation, the TFA FA topology experiences the most severe degradation among all topologies analyzed, with a marked increase of over 54% in total error occurrences, as shown in Table S15 from Supplementary Material. In this low-voltage regime, node b remains the most susceptible, contributing 14% of the total errors, while nodes e and Cout also emerge as critical fault sources, each accounting for approximately 13% of the total errors. This consistent vulnerability of output-related nodes across voltage levels highlights a systemic weakness in the TFA design, necessitating the development of targeted fault mitigation strategies, particularly under reduced voltage conditions. The context-dependent nature of node Sum adds complexity to the analysis, reinforcing the need for comprehensive, pulse-specific evaluation methods. Overall, the TFA’s high error increases under NTV positions; it is the least robust among the full adder designs examined in this study.

4.3. Input Vectors

In the context of a FA circuit, an input vector combination refers to a specific arrangement of input values applied to the circuit to perform a computation. In the realm of radiation hardness, the sensitivity of a circuit to radiation events can vary depending on the specific combination of input vectors applied. Certain input vector combinations may lead to conditions where the circuit is more vulnerable to radiation-induced errors [52].

For the Mirror FA operating at NV, 14% of the total errors manifest in response to the input vector 011, presented in Table S2 from Supplementary Material. Vector 100 also contributes significantly to error propagation, albeit with a slightly lower rate of 12%. The critical LETth values are associated with the input vector 000, establishing it as the pivotal input combination with the lowest LETth and, consequently, the most critical for the Mirror circuit under nominal conditions. Under NTV operation, the error behavior shifts. Input vector 100 exhibits the highest susceptibility to error generation, as shown in Table S10 from Supplementary Material. Furthermore, vectors 001 and 010 contribute notably to error propagation, together accounting for over 46% of the total SET occurrences. Consistent with nominal voltage operation, vector 000 maintains the lowest LETth, reaffirming its role as the most critical input combination for the Mirror topology across both voltage domains.

Shifting focus to the Hybrid FA, a distinct pattern in error behavior is observed under different operating voltages. At nominal voltage, the input vector 000 exhibits the lowest error rate, accounting for only 8% of the total error occurrences, while vector 011 demonstrates the highest error rate at nearly 15%, results available in Table S4 from Supplementary Material. Notably, vector 001 is associated with the lowest LETth, identifying it as the critical input combination for this topology under nominal conditions. Under NTV operation, the error profile shifts slightly, as presented in Table S12 from Supplementary Material. Input vectors 010, 011, 100, and 101 each present a high and nearly uniform error rate of approximately 14%, indicating increased vulnerability to error generation in the NTV regime. These same vectors are linked to the lowest LETth values under NTV conditions, designating them as the most sensitive inputs for the Hybrid FA at reduced supply levels. Consistent with the nominal case, vector 000 remains the most resilient, once again displaying the lowest error rate at just 8%.

For the TGA FA, the input vector 011 emerges as the most error-prone under both nominal and NTV conditions. At nominal voltage, vector 011 accounts for approximately 17% of the total error occurrences and is also associated with the critical LETth value. Interestingly, aside from the 000 input vector, all other input combinations eventually reach a LETth of 21 MeV · cm²/mg, indicating that for this topology, the critical LET threshold is largely independent of specific input combinations. When operating at NTV, the error distribution remains similarly concentrated around vector 011, which contributes 16% of the total SET events, reinforcing its status as the most sensitive input. Furthermore, as shown in Table S14, multiple vectors share the lowest LETth value of 2 MeV · cm²/mg, including vectors 001, 010, 011, 100, 101, and 111. This suggests a broader vulnerability across different input combinations at lower voltages, depending on the specific node affected by radiation. As observed in the Hybrid and Mirror topologies, vector 000 consistently presents the lowest error rate, confirming its robustness under both operating conditions.

For the TFA FA, the input vector 011 is consistently among the most error-prone across both voltage domains, presented in Table S8. At nominal voltage, this vector accounts for approximately 18% of the total error occurrences, highlighting its high susceptibility to transient fault generation. However, the critical LETth values for this topology are associated with the input vectors 010 and 100, rather than 011. Meanwhile, vector 000 stands out as the most robust input combination, contributing only 6% of the total observed errors. Under reduced voltage conditions the TFA topology experiences a more pronounced sensitivity to radiation-induced disturbances. As shown in Table S16 from Supplementary Material, vectors 010 and 100 become even more critical, with LETth values dropping to just 1 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, indicating a heightened vulnerability at reduced supply levels. Despite this, vector 011 remains the most error-prone, contributing up to 21% of the total SET events, thus reaffirming its status as the most sensitive input vector under NTV operation. Consistent with the nominal case, vector 000 continues to demonstrate the lowest error rate, underscoring its robustness across both operating conditions.

This comprehensive analysis of input vectors sheds light on specific combinations that significantly influence error rates, aiding in the identification of critical scenarios and potential avenues for targeted mitigation strategies. The findings aid in identifying critical scenarios and offer potential avenues for targeted mitigation strategies.

4.4. Type of SEE Hit

In the context of radiation-induced effects on digital circuits, different electrical pulse types, specifically observing the n-hit and p-hit effects, result from the interaction of energetic particles with the circuit components.

Examining the impact of different radiation hits on the Mirror FA, the n-hit emerges as the most critical pulse type under both nominal and NTV operations. At nominal voltage, the n-hit generates the lowest LETth values across all outputs, underscoring its significance in inducing transient errors. This pulse type is responsible for nearly 57% of the total transient errors observed in simulations, a rate that is up to 20% higher than that associated with the p-hit, further emphasizing the dominant role of n-hits in error propagation. For the NTV conditions, the n-hit remains the critical SET pulse, accounting for approximately 58% of the total observed SET events across the combined Sum and Cout outputs. It continues to produce the lowest average LETth values for both outputs, reinforcing its criticality in low-voltage operation. These findings demonstrate the persistent dominance of n-hits in error generation for the Mirror FA, irrespective of the supply voltage.

The analysis of the Hybrid FA reveals that n-hits are the primary contributors to error generation across both nominal and NTV conditions. At nominal voltage, n-hits account for approximately 58% of the total errors, making them the dominant source of transient faults in this topology. This hit type not only generates the highest error rate but also corresponds to the critical LETth values, exhibiting the lowest LETth on average. When operating at NTV, the trend persists, with n-hits maintaining a slightly higher error rate compared to p-hits and remaining responsible for the critical LETth values. The 58% error contribution from n-hits highlights their continued significance in influencing the overall error susceptibility of the Hybrid FA at reduced supply voltages. These results underscore the dominant role of n-hits in shaping the error characteristics of the Hybrid topology, irrespective of the operating voltage.

In the TGA FA, the n-hit is the predominant cause of transient errors across both nominal and NTV operations. At nominal voltage, n-hits are responsible for up to 57% of total errors, with 44% of these manifesting specifically at the Sum output. This highlights the criticality of the n-hit in this topology, likely due to signal paths that are more vulnerable to charge deposition and resultant transient faults during high-to-low pulse transitions. During NTV operation, the n-hit remains the most significant contributor, accounting for 53% of total error occurrences. However, both n-hits and p-hits generate critical LETth values, particularly when the radiation strike impacts the Sum node. This indicates that the Sum output is sensitive to both types of hits in the TGA topology, emphasizing a broader susceptibility to transient errors at reduced supply voltages.

In contrast to the other examined topologies, the Transmission Gate Full Adder (TFA) exhibits a distinctive and balanced response to radiation-induced transient errors across both n-hit and p-hit types. At nominal voltage, error rates for both hit types are approximately 50%, indicating a symmetric vulnerability to transient faults. Analyzing individual outputs, the Cout node consistently shows an error rate around 17%, while the Sum output is more susceptible, with error rates reaching about 34% for both hit types. This uniform distribution suggests that the TFA topology is equally affected by radiation pulses, causing both rising and falling transitions. Under NTV conditions, the error profile shifts, with n-hits significantly increasing their impact and accounting for nearly 53% of total errors observed. Notably, the high-to-low (n-hit) pulses are responsible for generating all critical LETth values during the simulations, highlighting the growing dominance of n-hit-induced errors at reduced supply voltages. This behavior underscores a voltage-dependent shift in the TFA’s susceptibility to radiation, favoring n-hit effects under NTV operation.

4.5. Evaluation Overview

Examining circuits across diverse corner scenarios sheds light on potential techniques to enhance robustness in both operational contexts. This analysis seeks to uncover the nuances of how circuits react to varying voltage conditions. Identifying critical nodes, components, and operational behaviors becomes crucial in this exploration. These insights are fundamental for customizing effective mitigation strategies to fortify the resilience of FA circuits across diverse scenarios of operation. The results found across both voltage scenarios are summarized in

Table 6. Comparison of sensitive nodes, critical nodes, critical input vectors, and critical hit types for each FA topology under nominal and NTV operations.

FA Topology	Sensitive Nodes (Error Rate)	Critical Nodes (Lowest LETth)	Critical Vectors	Critical Hit Type
Mirror FA (Nominal)	k (13% of errors)	g, j (14 MeV·cm2/mg)	000	n-hit
Mirror FA (NTV)	c (11% of errors)	g, j (1 MeV·cm2/mg)	100	n-hit
Hybrid FA (Nominal)	c, d (20% of errors)	c (8 MeV·cm2/mg)	001	n-hit
Hybrid FA (NTV)	d (12% of errors)	almost all nodes (2 MeV·cm2/mg)	010, 011, 100, 101	n-hit
TGA FA (Nominal)	h, Sum (28% of errors)	Sum, Cout (22 MeV·cm2/mg)	011	n-hit
TGA FA (NTV)	b (11% of errors)	Sum, Cout, g (2 MeV·cm2/mg)	011	n-hit
TFA FA (Nominal)	e, Cout (14% of errors)	Sum (14 MeV·cm2/mg)	010, 100	n-hit, p-hit
TFA FA (NTV)	e (14% of errors)	Sum (2 MeV·cm2/mg)	011	n-hit

.

When comparing the two voltage operations for the Mirror FA, the most susceptible node can vary depending on the scenario analyzed. However, it is noteworthy that the node Cout consistently exhibits the highest susceptibility rate in both scenarios. On the other hand, nodes k and l also warrant attention for improving robustness regarding voltage operations due to their high susceptibility to propagate radiation events. In the case of the Hybrid FA, error susceptibility is more balanced among nodes, with several nodes exhibiting approximately the same error rate. Notably, among the different voltage scenarios analyzed, nodes a, c, d, and f stand out as the most susceptible to propagate interference noise to the outputs. Examining the TGA topology reveals that, despite some nuances across different voltage operations, nodes b, h, sum, and cout consistently remain among the most susceptible nodes to propagate SET errors. In the case of the TFA topology, nodes d, e, and cout consistently maintained critical values. It is noteworthy that node e remained the most susceptible to propagate errors regardless of the voltage operation.

In terms of input vectors, different combinations show varying error rates. In the case of the Mirror FA at NTV, vector 100 emerges as the most error-prone. For the Hybrid FA, vectors 010, 011, 100, and 101 exhibit similar error rates. The TGA topology indicates that vectors 010 and 011 have higher error rates. In contrast, the TFA topology shows that vectors 010 and 011 are more prone to propagating errors. Critical input vectors are identified as follows: 000 for the Mirror FA, 001 for the Hybrid FA, and, for the TGA, all inputs except for vectors 00 and 101 can propagate the lowest LETth values. Lastly, the TFA topology designates vector 100 as the critical input, as it consistently results in the lowest LETth values across experiments.

Concerning SET hit types, the n-hit consistently emerges as critical for all topologies analyzed under both voltage operation conditions, except for the TFA topology in NTV operation, where the pulse n-hit exhibits a higher error rate. However, it is noteworthy that the critical LETth values are predominantly generated by the n-hit across the various scenarios.

Critical nodes vary between the FA topologies. For the Mirror FA, nodes g and j remain the most sensitive in both voltage operations. In the Hybrid FA, despite a higher increase in critical nodes in NTV, nodes c and d consistently exhibit the lowest LETth in both scenarios. In the TGA topology, nodes Sum and Cout consistently emerge as critical in propagating SETs regardless of the voltage scenario. Finally, for the TFA, nodes e and Sum stand out as critical nodes, presenting the lowest LETth values in both scenarios.

In conclusion, the voltage comparison across various FA topologies revealed nuanced sensitivities and critical nodes under different operating conditions. Each topology exhibited distinct responses to voltage variations, emphasizing the importance of tailored mitigation strategies. Analyzing these scenarios provides valuable insights into our investigation and enables us to explore strategies for optimizing robustness and reliability in integrated circuits facing diverse voltage conditions, contributing to the advancement of radiation-hardened circuit design.

5. SET Mitigation Techniques

The previous evaluation shows the SET sensitivity of the FA considered in this work, even adopting a multigate technology. Thus, mitigation techniques must be explored in the design to reach more elevated levels of SET robustness. This work investigates the application of three different mitigation approaches: Transistor Sizing, Decoupling Cells, and finally a combination of both techniques, targeting the most sensitive nodes within these circuits. It is important to note that the DCELL is always applied to the same node under evaluation for the fault injection scenario, i.e., the node where this particular particle strike is simulated, in order to assess how effectively it can dissipate the collected charge.

5.1. Total Error

The total number of error occurrences across the topologies (i.e., the absolute count of SET-induced errors propagated through the outputs) is presented in Figure 7. Without mitigation strategies, each FA topology reported a different total error occurrence, i.e, 100, 94, 88, and 70 absolute total error occurrences for the Mirror, Hybrid, TGA, and TFA, respectively.

At nominal voltage operation, the Mirror FA exhibited a reduction of nearly 26% in observed errors when applying DCELL or TS. However, combining both techniques resulted in up to a 70% decrease in errors, as highlighted in our work. For the Hybrid FA, using the DCELL technique led to a reduction of approximately 13%, while employing TS led to a reduction of about 49%. The most significant improvement for the Hybrid topology was achieved by combining TS and DCELL, resulting in a remarkable 68% reduction in errors. The TGA also showed a modest reduction in total errors when using DCELL, around 5%. However, employing the TS technique increased this reduction to up to 45%. Furthermore, the most substantial improvement was observed when both techniques were combined for this topology, resulting in almost a 60% reduction in errors. Finally, for the TFA, similar behavior for the last topologies was observed, with a reduction of approximately 13% when using DCELL, 54% when considering sizing adjustments, and nearly 63% fewer errors when combining both techniques.

In the case of the Mirror FA at NTV, the application of DCELL results in a reduction of total errors by up to 32%, as presented in Figure 8. The TS technique exhibits a more modest decrease of nearly 22% in the error count. The most promising results are achieved by combining both techniques, yielding a reduction of up to 35%. For the Hybrid FA at NTV, there is an increase of close to 33% in the total error occurrence compared to nominal values without mitigation techniques. The application of DCELL on the target nodes for this topology results in a 26% decrease in the total error count, while sizing the transistors reduces it by almost 25%. The most favorable outcomes are observed when combining both techniques, achieving a total reduction of 40% in the error count. The TGA topology at NTV presented an expressive increase of almost 39% in the total number of errors compared to its implementation at nominal voltage. The use of DCELL for this topology reduced the total error occurrence by only 8%. Similarly, the use of TS reduced the errors by close to 11%. The best outcome for the TGA was achieved by combining both techniques, resulting in an expressive reduction of close to 52% in the propagated errors. For the TFA topology at NTV, the observed errors were 54% larger than its implementation at nominal voltage, making it the critical topology when compared to switching to lower voltage operation. The usage of DCELL helps to reduce the errors by up to 21%, while sizing the transistors yields similar results with a reduction of 23%. Following the same trend as previous topologies, the best results were found when combining both techniques, with a significant reduction of up to 44%. Despite the voltage reduction potentially increasing the number of propagated errors, the results show that the use of mitigation techniques can still help improve sensitivity while preserving the potential reduction in power consumption that working at NTV can provide.

The combination of DCELL and transistor sizing consistently provides the most significant reduction in total errors across all analyzed topologies and voltage conditions, making it the most effective technique for enhancing circuit robustness. While each method, i.e, the DCELL or sizing, individually contributes to error mitigation, their combined application amplifies the benefits. This effectiveness stems from two factors: sizing adjustments reduce node susceptibility to charge collection, thereby lowering the likelihood of SETs, while DCELL adds capacitance that stabilizes critical nodes against voltage fluctuations caused by radiation. Together, these techniques improve signal integrity and reliability under radiation exposure. However, it is important to note that the transistor sizing will introduce a consequence effect for high LET particles. In these conditions, the transistor sizing will imply a larger device area, and higher charge-collection efficiency may offset the transistor sizing as a mitigation approach [53].

5.2. Input Vectors

The most susceptible vector to generate an error in the Mirror FA while applying the DCELL technique is 110; this vector contributes to 16% of the total error for the topology. However, vectors 001 and 010 have major contributions to propagating the pulse to the outputs. Together, they represent close to 30% of the total error occurrence. On the other hand, for the scenario using the TS vector, 110 and 111 became the most susceptible to generate errors, and when combining both techniques, the vector 011 is the most sensitive. Except for the TS scenario where the critical LETth was observed for 111 vector, all critical LETth values were generated for the combination 000 in the Mirror topology. On the other hand, at NVT operation and using DCELL, it is possible to observe that vectors 001, 010, and 101 are the most susceptible to generating errors, presenting together up to 42% of the total errors. On the other hand, with TS, the vector 001 generates most errors, and when combining techniques, the vectors 001 and 010 are the ones that generate up to 28%. However, for all scenarios at NTV, vector 000 is the critical one, presenting the lowest LETth values despite the mitigation technique at the low voltage operation.

For the Hybrid implementation applying DCELL at nominal operation, vector 100 propagated 20 errors, representing up to 26% of the total error occurrence, being the most sensitive ones for this scenario. Vectors 010 and 011 are also among the most susceptible that can propagate errors for the DCELL scenario. Using TS, we reduced the total errors, and fewer errors were propagated by each vector, as shown in Figure 9. Applying the sizing technique to all transistors, as described in the methodology section, alters the circuit behavior, making the input vector 011 the new critical one, and the vector 011 becomes the critical one, propagating approximately 21% of the observed errors. Combining both techniques presented the best results in total error occurrence; however, vector 011 still represents one of the most sensitive ones, along with vector 100.

At NTV, and using DCELL, all vectors present the same susceptibility error rate up to 13% of the total error, except for vectors 001 and 110, which show a smaller rate of close to 12% on average. When using TS at NTV for the Hybrid topology, only vector 011 presents the highest error susceptibility of almost 16%. On average, for all scenarios, vector 010 is the critical vector for the Hybrid FA operating at NTV, as Figure 10 shows.

For the TGA FA at nominal voltage, vectors 011 and 100 are the most error-prone under DCELL, each with 21 errors, followed by 110. TS alone reduces the overall error count and distributes errors more evenly, though 011 still stands out. The combined TS + DCELL approach achieves the lowest error rates, with no vector exceeding six errors, though 000 remains slightly more sensitive, indicating some residual vulnerability. At NTV, error susceptibility increases, with vector 011 showing the highest count (30 errors) in the unprotected case, followed by 110 and 001. DCELL and TS reduce errors slightly, but 011 remains dominant across all techniques. The combined approach further lowers total errors, yet vectors 011, 001, and 110 continue to show heightened sensitivity. Overall, vector 011 is consistently the most critical across both voltage regimes and mitigation strategies.

For the TFA full adder at NV, vectors 011 and 100 are the most error-prone in the unprotected case, with 19 and 17 errors, respectively. Applying DCELL slightly increases total errors, with 011 remaining the most critical, followed by 100 and 010. TS reduces overall errors and distributes them more evenly, though 100 still stands out. The combined TS + DCELL scenario yields a nearly uniform distribution (12–14 errors per vector), indicating effective equalization but limited reduction in total faults. Vector 100 consistently shows higher susceptibility. At NTV, the TFA becomes more error-sensitive overall, with vector 011 leading at 27 errors, followed by 110, 100, and 010. DCELL maintains this pattern, with 011 still dominant. TS reduces errors moderately, but 011 and 100 remain critical. Under TS + DCELL, error rates drop slightly, yet 011 and 110 continue to show higher vulnerability. Across all scenarios and voltages, vector 011 emerges as the most consistently sensitive, suggesting the need for targeted mitigation.

5.3. Hit Type

Analyzing the SET hit type for all the outputs of the Mirror FA applying the DCELL technique at nominal voltage, p-hit is responsible for up to 52% of the total error occurrence, as Figure 11 shows. Despite that, n-hit generates, on average, all the lowest LETth, including the critical value for the circuit. For the TS technique, the n-hit type is responsible for most errors, accounting for up to 57% of all errors. When combining the techniques, also pulse high-to-low is responsible for 56% of the total error. Thus, n-hit is critical to consider in this operational mode for Mirror FA, regardless of the mitigation technique used.

In the Hybrid FA, employing DCELL results in p-hit accounting for nearly 52% of the total errors, while n-hit emerges as critical in the TS scenario, contributing approximately 65% of the total errors. This scenario exhibits the largest disparity between the two hits used in the experiments. Additionally, n-hit is responsible for generating all the lowest LETth values in the scenario with transistor sizing and DCELL. This indicates that transitions induced by negative charge collection are more prone to propagation in the evaluated topologies. Investigating the TGA topology, both hit types exhibit similar error rates, despite the mitigation technique employed. However, when employing DCELL, n-hit shows a slight increase compared to p-hit. This trend persists when sizing the transistors, with only a 1% difference observed between the two hit types. Once again, n-hit emerges as critical for the TGA topology. Similarly to the TGA, in the TFA topology, the difference between the two hit types is minimal across all mitigation technique scenarios. When employing DCELL, n-hit leads to a mere 4% gap in the observed errors compared to pulse p-hit. This consistent trend underscores the significance of n-hit as a potential critical factor in the TFA topology.

Reducing the voltage operation alters the critical pulse dynamics across the evaluated scenarios, as highlighted in Figure 12. In the case of the Mirror FA, employing DCELL shifts n-hit to be the most susceptible pulse, responsible for 54% of errors, highlighted in Figure 12. Conversely, with the TS technique, p-hit emerges as critical, accounting for 54% of errors. Combining DCELL and TS maintains n-hit as critical, with a 55% error rate. For the Hybrid FA, differences in error rates between hit types are reduced compared to the nominal voltage implementation. The DCELL technique in this topology predominantly propagates errors from n-hit to the output. With TS and TS + DCELL implementations, both hit types contribute equally to errors, with n-hit being critical across all scenarios.

In the TGA topology at NTV, DCELL maintains n-hit as critical, responsible for 52% of errors. Similarly, TS results indicate that n-hit causes 53% of errors. Combining both techniques also highlights the high-to-low hit as critical for error propagation. Similar to the other topologies, the n-hit can be defined as the critical one for the TGA topology. Finally, for the TFA topology, voltage reduction alters the critical hit behavior. With DCELL, both hit types exhibit similar error rates, each contributing 50% to total errors. However, with TS and the combined scenario, the p-hit becomes critical, accounting for 51% of errors. Notably, the low-to-high hit emerges as critical, generating most errors on average across scenarios.

The results demonstrate that hit type dynamics are closely tied to the effectiveness of mitigation techniques and the impact of voltage scaling on error rates. Across different topologies, techniques like DCELL and transistor sizing influence how high-to-low (n-hit) and low-to-high (p-hit) pulses propagate errors. DCELL tends to reinforce the dominance of n-hits as the critical source of errors, while TS often balances the error contribution between both hit types. Moreover, voltage reduction significantly alters hit behavior—what is critical at nominal voltage may shift under near-threshold conditions, underscoring the complex interplay between voltage, hit type, and mitigation strategy. Understanding these relationships is essential for tailoring robust circuit designs in radiation-prone environments.

5.4. Critical Nodes

In the investigation of critical LETth values to pinpoint the most sensitive regions at nominal voltage, we focused on the Mirror FA implementation as our reference. At nominal voltage, analysis across all topologies reveals that mitigation techniques—DCELL, TS, and their combination—consistently enhance circuit resilience by increasing LETth values, though with varying effectiveness, as Figure 13 highlights. For the Mirror FA, DCELL yields a modest 1.14× improvement, with node j remaining critical and node g showing notable gains (16 to 22 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$). TS nearly doubles LETth, shifting the critical node to b, while the combined application achieves a 3× enhancement, particularly benefiting node j, which remains consistently critical. In the Hybrid FA, critical nodes vary by technique: DCELL highlights nodes e and j (1.52× increase), TS shifts focus to node c with a 1.68× improvement, and their combination delivers a 2.30× increase. All techniques contribute to increased LETth, but critical node locations shift depending on the method used. For the TGA topology, outputs Sum and Cout are persistently the most sensitive, with DCELL raising LETth by 1.59× (to 22 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$), TS by 2.20× (to 31), and the combination by 2.31×. Similarly, in the TFA, the smallest improvement is seen with DCELL (1.11×), while TS provides a 1.83× boost, making node Sum critical at 26 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$; combining both yields a 1.93× improvement. Across all scenarios, output nodes such as Sum and Cout consistently exhibit the lowest LETth, underscoring their vulnerability and the importance of targeted mitigation.

Reducing the voltage to near-threshold operation significantly impacted the critical LETth across all evaluated topologies. The Mirror FA continues to serve as a reference, with node j consistently presenting the lowest LETth values. At NTV, DCELL alone results in a LETth of 1 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ for node j, while TS improves this by 3.07×, though j remains critical. When combining TS and DCELL, both nodes g and j reach an improved LETth of 3.30×, confirming node j as a consistently critical node across voltage scenarios. In the Hybrid FA, DCELL at NTV leaves nearly all nodes equally sensitive with a LETth of 2 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, whereas TS targets only nodes a and g, improving LETth by 2.77×. Combining both techniques yields a further increase to 3.27 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$, with TS proving slightly more effective in mitigating errors at NTV. For the TGA topology, DCELL boosts LETth by 1.68×, affecting nodes g, Sum, and Cout, while TS raises it by 2.15×. The combined approach results in a 2.46× increase, with output nodes remaining the most critical across all cases. Similarly, in the TFA topology, DCELL leads to a modest 1.31× improvement, TS doubles LETth to 2 $\mathrm{MeV}·{\mathrm{cm}}^2/\mathrm{mg}$ for output nodes, and the combined technique achieves a 2.23× increase, particularly improving the robustness of node Sum. Across all topologies and mitigation methods, output nodes consistently emerge as critical at NTV, emphasizing the importance of targeted hardening in these regions.

In summary, the critical nodes in the analyzed topologies exhibit varying degrees of sensitivity under nominal and NTV voltage conditions. While the Mirror FA consistently identified critical nodes across different scenarios, the Hybrid FA exhibited fluctuations in critical node identification, depending on the mitigation technique employed. On the other hand, the TGA topology maintained its critical output nodes across all scenarios, highlighting the importance of output node robustness. Finally, the TFA topology demonstrated that output nodes consistently remained critical, emphasizing their significance in determining overall circuit robustness. These findings underscore the need for tailored mitigation techniques to address specific vulnerabilities to the different circuit topologies under diverse voltage conditions.

5.5. Drawbacks of the Mitigation Approaches

Finally, we have included a discussion about the drawbacks of the insertion of the mitigation approaches on the power consumption and delay characteristics for the four full adder topologies considered, also observing the impacts at nominal and near-threshold operation.

5.5.1. Power Consumption

The data presented in

Table 7. Power consumption for all topologies in all scenarios.

Topology	Nominal				NTV
	Standard	DCELL	TS	TS + DCELL	Standard	DCELL	TS	TS + DCELL
Mirror	17.60 $\mathsf{\mu }$W	17.65 $\mathsf{\mu }$W	22.41 $\mathsf{\mu }$W	22.40 $\mathsf{\mu }$W	511.00 nW	532.27 nW	636.89 nW	616.99 nW
Hybrid	12.47 $\mathsf{\mu }$W	12.71 $\mathsf{\mu }$W	17.79 $\mathsf{\mu }$W	17.82 $\mathsf{\mu }$W	378.09 nW	340.76 nW	518.29 nW	541.50 nW
TGA	11.64 $\mathsf{\mu }$W	11.64 $\mathsf{\mu }$W	17.70 $\mathsf{\mu }$W	19.72 $\mathsf{\mu }$W	373.36 nW	475.37 nW	553.92 nW	573.66 nW
TFA	8.53 $\mathsf{\mu }$W	14.96 $\mathsf{\mu }$W	14.89 $\mathsf{\mu }$W	18.28 $\mathsf{\mu }$W	312.75 nW	428.07 nW	499.90 nW	525.23 nW

offers a comprehensive comparison of power consumption across four different FA topologies evaluated under the mitigation techniques at both nominal voltage NTV conditions.

Under nominal voltage, the TFA topology emerges as the most power-efficient design. It achieves the lowest power consumption, consuming close to 8.53 $\mathsf{\mu }$W, outperforming all other configurations. Even when enhanced with mitigation techniques such as DCELL or sizing, TFA maintains relatively low power overhead compared to its baseline. In contrast, the Mirror topology consistently shows the highest power consumption under nominal voltage. This is particularly evident in the sizing and combining of both techniques, where the power increases above 22 $\mathsf{\mu }$W, suggesting that this design may not be suitable for power-constrained applications, especially when mitigation techniques are introduced.

TGA also presents a good performance at nominal voltage, especially without mitigation techniques, matching the Hybrid topology results closely. However, under NTV, the power consumption increases noticeably when sizing and DCELL are included. This indicates that mitigation techniques introduce additional overhead that affects the TGA design more significantly than others. For instance, the combined techniques configuration for TGA results in 573.66 $\mathsf{\mu }$W, which is notably higher than its standard NTV counterpart. This behavior suggests that while TGA is a strong candidate for nominal voltage applications, its efficiency under NTV may be compromised by the inclusion of fault-tolerant enhancements.

Across all topologies, the application of NTV leads to a dramatic reduction in power consumption by an order of magnitude compared to nominal voltage. This confirms the effectiveness of near-threshold operation in reducing energy use, a critical consideration in ultra-low-power design. However, it also highlights the importance of topology choice, as the relative power advantages between topologies shift somewhat under NTV.

The impact of mitigation techniques such as DCELL and sizing is heavily topology-dependent. While DCELL often introduces a small power overhead due to increased transistor count, in certain cases like the Hybrid topology, it actually results in reduced power consumption under NTV. This suggests that for certain topologies, DCELL might optimize critical paths or rebalance current flows in a way that minimizes leakage, especially at NTV. Sizing generally increases power consumption, as expected, due to larger transistor widths increasing capacitance and leakage. When both mitigation strategies are combined, power consumption is generally the highest, reflecting the compounded effect of both overheads. Even so, topologies such as TFA handle this combination better than others, maintaining relatively modest increases in power.

In conclusion, the TFA topology stands out as the most power-efficient option across both voltage domains and under various mitigation strategies. Its minimal power overhead makes it suitable for energy-critical applications, particularly in NTV regimes. The Hybrid topology, especially when paired with DCELL, presents a compelling balance between resilience and power efficiency, showing promising results under NTV. Conversely, the Mirror topology appears to be the least efficient in terms of power, especially when mitigation techniques are applied, making it a less suitable candidate for low power design. These insights can guide the selection of appropriate full adder designs in future fault-tolerant and energy-efficient digital systems.

5.5.2. Critical Delay

The results shown in

Table 8. Critical delay for all topologies in all scenarios.

Topology	Nominal				NTV
	Standard	DCELL	3-Fin	3Fin + DCELL	Standard	DCELL	3-Fin	3Fin + DCELL
Mirror	17.90 ps	21.58 ps	18.06 ps	19.91 ps	112.82 ps	112.11 ps	126.50 ps	132.42 ps
Hybrid	43.62 ps	47.52 ps	14.01 ns	14.01 ns	186.70 ps	215.54 ps	14.08 ns	14.08 ns
TGA	19.45 ps	16.29 ps	25.86 ps	25.86 ps	141.22 ps	164.42 ps	130.09 ps	194.31 ps
TFA	23.48 ps	29.36 ps	31.54 ps	35.84 ps	138.83 ps	176.82 ps	134.70 ps	260.50 ps

detail the critical delay behavior for the topologies across the scenarios evaluated in this work. The measurements are given for both nominal and NTV conditions, providing insight into how each topology and mitigation technique affects performance in different conditions.

Under nominal voltage, the Mirror topology demonstrates relatively low critical delays across all configurations, with no mitigation techniques presenting a delay of 17.90 ps and only slight increases with the addition of mitigation techniques. The use of DCELL increases the delay to 21.58 ps, while the sizing adds a small overhead to 18.06 ps. Combining both techniques raises the delay further to 19.91 ps. These values suggest that the Mirror topology is inherently fast under nominal conditions and that the impact of mitigation techniques on delay is modest, maintaining its suitability for high-speed applications in standard voltage regimes.

The Hybrid topology presents a very different behavior. While its nominal operation and applying DCELL show moderate delays at 43.62 ps and 47.52 ps respectively, the introduction of sizing results in a dramatic increase in delay to 14.01 ns, a value orders of magnitude higher than the others. This excessive delay persists even when DCELL is added alongside sizing. These results indicate a severe performance bottleneck when sizing is applied to the Hybrid topology, possibly due to an unfavorable combination of increased capacitance and the internal logic structure. These results show that the Hybrid design does not scale well with increased drive strength under nominal voltage, and the resulting degradation in delay is substantial.

The TGA topology shows relatively stable and efficient delay performance under nominal conditions. Adding DCELL actually improves its delay slightly from 19.45 ps to 16.29 ps, suggesting that the redundancy structure may contribute positively to signal propagation in this particular design. However, sizing alone increases the delay to 25.86 ps, and combining it with DCELL maintains this level. This indicates that while DCELL alone may optimize the path in some way, the sizing overhead hides any such benefits when applied.

TFA under nominal conditions displays modest delays, with the standard configuration at 23.48 ps. As mitigation techniques are added, the delays progressively increase, reaching 35.84 ps in the combined techniques case. While the delay trend is logical and expected due to the addition of transistor count and drive strength, the increments are not catastrophic. TFA remains relatively stable and predictable across configurations, though not as fast as Mirror or TGA in its unprotected form.

Under NTV conditions, delays naturally increase due to slower transistor switching, and this effect is observed across all topologies. For Mirror, the critical delay rises from 112.82 ps without mitigation to 132.42 ps with full combined mitigation. The growth is linear and moderate, maintaining the Mirror topology as a fast, although power-hungry, design. Hybrid again demonstrates an extreme reaction to sizing, with the delay increasing from 186.70 ps in the standard case to 14.08 ns with sizing, whether DCELL is included or not. This confirms that the sizing technique may be incompatible with the Hybrid topology under low voltage operation, severely degrading its performance.

TGA shows a more mixed behavior in NTV. Its standard delay of 141.22 ps increases when DCELL is added, reaching 164.42 ps. The sizing configuration reduces the delay slightly to 130.09 ps, though the combination with DCELL presents the delay up to 194.31 ps. This variability suggests some sensitivity of TGA to process and structural changes under low voltage, but its delays remain within a usable range overall.

TFA maintains moderate delay increases under NTV, with the standard delay at 138.83 ps and rising to 260.50 ps in the combined configuration. Similar to the nominal case, the delay progression is steady and expected, reinforcing the consistency even as mitigation techniques are introduced.

From this analysis, the delay behavior across these topologies is heavily influenced by the combination between the logic structure of each topology and the mitigation technique applied. While Mirror is the most delay-efficient, TFA offers a more balanced and predictable response. Hybrid, despite some power advantages, presents limitations in delay when sizing is introduced, particularly under NTV, and the performance for TGA topology is generally acceptable but somewhat sensitive to structural changes. These insights are critical when selecting the most appropriate FA topology for applications with performance and reliability constraints.

5.6. General Overview Considering Robustness, Power and Delay

The analysis of power consumption and critical delay indicates that while mitigation techniques like DCELL and transistor sizing can enhance robustness, they invariably introduce overheads, dependent on the chosen full adder topology and the operating voltage. This leads to explicit design guidelines for selecting appropriate full adder (FA) topologies based on desired performance characteristics and the need for fault tolerance.

For designs where absolute minimum power consumption is paramount, even before considering fault tolerance, the TFA topology is the option. Its inherent efficiency (8.53 $\mathsf{\mu }$W nominal, 312.75 nW NTV) makes it the most energy-efficient choice. The TFA’s ability to maintain relatively low power overheads with mitigation techniques suggests that its internal structure is less susceptible to the increased capacitance and leakage from DCELL and sizing. Designers prioritizing low power should select TFA and then evaluate the specific power penalty of their chosen mitigation. TFA’s power efficiency advantage becomes even more pronounced at NTV. This indicates that at lower voltages, where leakage components become more dominant, topologies with inherently fewer leakage paths or transistors offer more significant benefits. The Mirror topology should be avoided in power-constrained applications, as it consistently consumes the most power, particularly with mitigation (above 22 $\mathsf{\mu }$W nominal). Its high transistor count or specific gate arrangements likely lead to increased switching activity and leakage that are detrimental to power budgets.

The Mirror FA is the most recommended topology for High-Performance, Power-Agnostic Designs. It offers the lowest critical delays (17.90 ps nominal standard) and maintains competitive performance even with mitigation. Designers targeting high-performance computing should consider Mirror, understanding the associated power penalty. On the other hand, the Hybrid topology with transistor sizing is not recommended if delay is a concern. This combination results in a large increase in delay for applications requiring a balance between power efficiency and predictable delay performance with mitigation, TFA is a robust choice. Its delays are not the lowest, but they increase steadily and predictably with mitigation. The consistent increase in TFA’s delay with mitigation reinforces its reliability as a predictable design. While it might not be the fastest, its performance is less prone to unexpected degradation compared to, for example, the Hybrid. This makes it suitable for designs where performance variations are undesirable.

To provide explicit design guidelines, we define four application scenarios described in

Table 9. Application scenarios.

Application Scenario	Primary Goal
1. High Reliability, High Performance, Power Not Critical	Max Performance, SET robustness
2. Ultra-Low Power, Moderate Speed, Moderate Reliability	Min Power, SET robustness
3. Robustness against Variability (requiring sizing)	SET robustness (via Sizing)
4. DCELL for Potential Speed Improvement	SET robustness + Performance

with different reliability, performance, and power conditions. Considering these scenarios,

Table 10. General overview of recommended topologies.

Application Scenario	Recommended Topology (s)	Operating Voltage	Avoid Topology (s)
1	Mirror	Nominal/NTV	Hybrid, TFA/TGA
2	TFA	NTV	Mirror
3	TFA, Mirror, TGA	Nominal/NTV	Hybrid
4	TGA	Nominal	Hybrid, Mirror/TFA

summarizes the recommended full adder topologies based on common application scenarios, considering both operating voltage and mitigation needs. For scenario 1, Mirror FA is the best option with mitigation techniques adding minimal delay overhead; however, Mirror FA presents higher power consumption. It is recommended to avoid Hybrid, despite the good outcomes on SET reliability, due to the sizing impact on delay, and the TFA/TGA due to the slower native performance. On the opposite side, for scenario 2, the TFA shows up as the best option considering battery-powered, IoT, or biomedical devices due to the inherent low power and predictable delay behavior. Scenarios 3 and 4 are specific niche cases, considering situations where the transistor sizing is necessary (3) or DCELL can be explored to improve the delay (4). The best option when transistor sizing is a necessary mitigation strategy, for example, in applications where sizing is explored to combat process variation or improve drive strength, the Hybrid must be avoided, and we recommend detailed characterization of the exact power/delay trade-offs considering the transistor sizing requirements. Finally, for scenario 4, TGA with DCELL slightly reduced the delay due to its redundancy structure that might introduce parallel, faster paths or optimize signal propagation in specific scenarios. In this case, a specific characterization for the DCELL is also required.

Due to the complex interactions between topology, operating voltage, and mitigation techniques, detailed simulations, as demonstrated by these results, are necessary in the context of design for reliability. Designers should not rely on generalized assumptions but validate performance for their specific design choices. By following these guidelines, designers can make more informed decisions, selecting the full adder topology and mitigation approach that best aligns with their application’s specific requirements and constraints, avoiding costly pitfalls in the process.

6. Conclusions

This work evaluated the radiation robustness of FinFET-based circuits by analyzing four common full adder topologies—Mirror FA, Hybrid FA, TGA, and TFA—under two voltage conditions and using three mitigation scenarios. Two techniques, DCELL and Transistor Sizing, were applied to assess their effectiveness in reducing error rates and enhancing node-level resilience. Results show that combining both techniques consistently provides the most substantial improvement in total error reduction and LETth across all topologies, outperforming the application of each technique individually.

The adoption of mitigation techniques reduced total error occurrences by up to 60% at nominal voltage, depending on the topology, and more than 35% at NTV. The Hybrid topology exhibited, on average, 2% fewer errors than the Mirror FA at nominal voltage, but 5% more at NTV. Among the pass-transistor logic styles, the TFA showed 12% fewer errors than the TGA at nominal voltage and up to 11% at NTV. Critical nodes varied with the technique applied. For both voltage conditions, nodes g and j were critical in the Mirror FA, while nodes associated with the Cin path were critical in the Hybrid FA. In the TGA, output nodes were critical across both voltage domains, whereas in the TFA, the Sum output nodes remained critical.

LETth improvements reached up to 3.30× with combined mitigation techniques and averaged 2.74× across all topologies. DCELL alone provided a moderate enhancement of approximately 1.48×. The Hybrid FA was, on average, twice as robust as the Mirror FA when using DCELL across both voltage operations. However, with TS alone, the Mirror FA exhibited the most significant improvement, with LETth values 2× greater than those of the Hybrid implementation. The greatest improvement was observed in the Mirror FA at NTV using both techniques, resulting in nearly a 3.30-fold increase in critical LETth. Although the TGA and TFA also showed improvements under both voltage conditions, the LETth increase did not exceed 2.2×. Combining both techniques yielded the best improvements across all topologies and scenarios, with a minimum improvement of more than 2× in LETth.

The most susceptible input vectors varied depending on the mitigation technique. Nevertheless, for Mirror, Hybrid, and TGA topologies, most errors resulted from particle collisions that occurred during n-hit transitions when the output capacitance was charging. An exception was found in the TFA at NTV, where p-hit transitions became critical. Overall, the n-hit condition was the dominant source of errors and was associated with nearly all the lowest LETth values recorded in the experiments.

Transistor sizing mitigates soft errors by increasing the critical charge of sensitive nodes, while DCELL stabilizes node voltages through added capacitance, suppressing radiation-induced voltage fluctuations. Across all topologies, mitigation strategies influenced the propagation of error-inducing pulses differently. PTL styles demonstrated heightened vulnerability due to the easier propagation of errors from internal nodes to outputs, despite having a lower overall error count.

Understanding the interaction between pulse types, circuit topology, and mitigation strategies is essential for improving the radiation tolerance of integrated circuits. These insights guide the development of tailored hardening techniques suited to specific logic styles and node sensitivities. The comprehensive analysis presented in this work lays a foundation for the continuous advancement of radiation-hardened standard cell libraries, enabling rapid and validated ASIC implementation for the evaluated adder topologies and mitigation techniques. Future work will focus on extending the full adder evaluation when considering laser/particle beam testing and developing a compact, radiation-hardened standard cell library at 7 nm FinFET technology to allow for the integration of a set of robust cells exploring DCELL and transistor sizing approaches in the EDA tools, providing a standardized approach to robust design for radiation-prone environments.