Buck Converter with Improved Efficiency and Wide Load Range Enabled by Negative Level Shifter and Low-Power Adaptive On-Time Controller

Abstract

This paper introduces a high-efficiency buck converter designed for a wide load range, targeting low-power applications in medical devices, smart homes, wearables, IoT, and technology utilizing WiFi and Bluetooth. To achieve high efficiency across varying loads, the proposed converter employs a low-power adaptive on-time (AOT) controller that ensures output voltage stability and seamless mode transitions. An adaptive comparator (ACP) with variable output impedance is introduced, offering a variable DC gain and bandwidth to be suitable for different load conditions. A negative-level shifter (NLS) circuit, with its swing ranging from −0.5 V to the battery voltage (V_BAT), is proposed to control the smaller power p-MOS transistors. By using an NLS, the chip area, which is mostly occupied by power CMOS transistors, is reduced while the power efficiency is improved, particularly under a heavy load. A status time detector (STD) block which provides control signals to the ACP and NLS for optimized power consumption is added to identify load conditions (heavy, light, ultra-light). By employing a 180 nm CMOS technology, the active chip area occupies about 0.31 mm². With an input voltage range of 2.8–3.3 V, the controller’s current consumption ranges from 1.2 μA to 16 μA, corresponding to the output load current varying from 12 μA to 120 mA. Although the output load can vary, the output voltage is regulated at 1.2 V with a ripple between 3 and 12 mV. The proposed design achieves a peak efficiency of 96.2% under a heavy load with a switching frequency of 1.3 MHz.

1. Introduction

System-on-Chip (SoC) technology is crucial for low-power devices such as smartwatches, implantable medical devices, and IoT applications [1,2,3,4], which exhibit dynamic power demands as shown in Figure 1. These devices consume microwatts power in standby for tasks such as notification checks and low-power wireless communication, enabling rapid wake-up. During active processing, power consumption can range from milliwatts to hundreds of milliwatts depending on the executed functions. Buck converters in these low-power devices are employed with the controller blocks using ultra-low current to maximize battery life and efficiency, especially during standby [5,6]. DC-DC converters are not only needed to maintain a stable output voltage over a wide input voltage range due to fluctuations in battery charge, but also for handling significant load current variations during operation [7,8]. Therefore, minimizing power consumption, maximizing efficiency across a wide load range, and optimizing device dimensions are critical for prolonged device operation and reduced recharging frequency [9,10,11].

Recently, several power management units (PMUs) [12,13] often utilize multiple control modes with switching frequencies tailored to specific load conditions. However, the seamless mode conversions can be challenging due to decision making and mode-switching delays [14,15]. The pulse width modulation (PWM) [16] for high and medium loads and the pulse frequency modulation (PFM) [17] for light loads are used to reduce switching losses. However, such approaches can complicate the controller design, potentially increasing current consumption and output ripple in PFM mode [18,19]. Single-controller approaches such as a single bounded hysteresis control (SBHC) [20] and a dynamic on/off time (DOOT) control [21] are used for a high efficiency across a wide load range. However, due to fixed low-bias current comparators, the designs [20,21] suffer from a slow response and poor regulation under heavy loads [22,23]. Consequently, combining controllers with adaptive bias current comparators is necessary for high efficiency across a wide load range [24].

In order to respond to heavy output load, the large power transistor switches (PTSs) are needed for a high current throughput, which causes the chip area to increase. For instance, the design in [25] uses a PMOS and NMOS PTS occupying 2.7 and 1.7 mm², respectively, along with the high-power gate drivers. The level shifting (LS) techniques used in [26] can increase the gate-source voltage (V_GS) of CMOS transistors, enabling smaller PTS for high current throughput. However, these designs [25,26] still occupied significant areas about 7 mm² and 0.78 mm², respectively. Other approaches [27,28,29] using both a PMOS and NMOS PTS with level shifters and bootstrap configurations are used to reduce PMOS on-resistance (R_ON) and PTS sizing, but still result in relatively large active areas (0.75, 1.4, and 1.404 mm²). To achieve high performance with low fabrication costs, low current consumption, small chip size, while maintaining efficiency across variable loads, is a big challenge during the design DC-DC converter [30].

This paper presents a proposed buck converter with low power consumption and high efficiency across a wide output current load range (12 μA to 120 mA). A negative level shifter (NLS) with its output swing from a negative voltage (V_NEG) to V_BAT is proposed to reduce the PMOS PTS on-resistance (R_ON) without increasing its size. By employing an adaptive on-time (AOT) controller, a novel adaptive comparator (ACP) operating with dual-mode currents, and NLS, the proposed DC-DC buck converter achieves a high efficiency higher than 90% and 65% to approximate 90% with the output current load of from 40 to 120 mA and lower than 40 mA, respectively. Simulated in 180 nm CMOS technology, the proposed design occupies a small chip area of 0.31 mm². With an input voltage range of 2.8–3.3 V, the low-power AOT controller consumes 1.2 to 16 μA as the output current load changes from 12 μA to 120 mA. The output voltage is regulated at 1.2 V with the voltage ripple varying from 3 to 12 mV across different output loads. The subsequent sections of this paper detail the AOT control buck converter architecture and circuit implementations (Section 2), the simulation results (Section 3), and the conclusions (Section 4).

2. The AOT Control Buck Converter Architecture and Circuit Implementations

2.1. The Operating Mechanism of the Architecture

Figure 2 shows the block diagram of the proposed buck converter using AOT and NLS. In order to achieve low power consumption and high efficiency, a control block operating at a supply voltage V_DD = 1.2 V is designed to drive the PTS (S₁, S₂, S₃, S₄). The bandgap reference 1,2 (BGR1,2) blocks are utilized to produce the reference bias voltages to reduce the effect of the ambient temperature. The Soft-Start block generates a start voltage (V_S) which gradually increases from a V_SS to the reference voltage (V_REF), ensuring system stability and reducing negative factors during the start-up phase. The current sensor block is built from the resistors R_S = R_Z = 150 kΩ, capacitor C_S = 8 pF, and the inductor current (I_L) flowing through the inductor L =4.7 μH, which is converted to a voltage sensor signal (V_SEN). In order to regulate the output voltage (V_OUT), a type III compensator based on a differential difference amplifier (DDA), which is used and analyzed in reference [31,32], and biased with an ultra-low current is employed to not only respond immediately and optimally to changes in the output but to also generate an error-amplifier voltage (V_EA) at the DDA’s output. The compensator, which employed passive components such as capacitors C₁ = 40 pF, C₂ = 3.2 pF, C₃ = 4 pF, C₄ = 2 pF, and resistors R_f1,2 = 1.5 kΩ, R_1,2 = 1 MΩ, are used for system stability. During T_SLEEP under a light load and full cycle work in the ultra-light load mode, the ACP bias current is 30 nA, and 4 µA under a heavy load. The ACP is utilized to compare V_EA with V_SEN to generate a compared control signal (S_C), which is used to set the control signals C_LKP and C_LKN. The on-time detector (OTD) is applied to generate a fixed on-time T_ON, which is used to determine the inductor’s charging time. When the output experiences a light load and ultra-light load, the zero-current detector (ZCD) is enabled to detect the sleep time of the PTS S₂, preventing an inversed current in the inductor L. The control bias generates the control signals S_A and S_B. The S_A controls the bias current of the ACP, while the S_B is the input control signal for the status time detector (STD). The oscillator generates a clock signal (C_LK), which is used to control the negative voltage generator (NVG) block. The C_LK’s frequency is dependent on another clock signal C_LKP, which is generated by the control logic and the dead time block. The NVG is employed to produce a negative voltage V_NEG during the T_ON cycle to control PTS S₁. We note that V_NEG is created to help the output swing of the NLS increasing from V_NEG to the V_BAT voltage. This extended swing increases the throughput current of PTS S₁ to be increased while its size is maintained. In addition, STD is employed to generate the detector load condition signal EN_1,2. The EN_1,2 are bits of <11>, <10>, and <00> when the output load experiences a heavy, light, and ultra-light load, respectively. When the output current load is reduced to lower than the ultra-light current load, the T_ON of C_LKN is also reduced to zero, leading to the PTS S₂ being completely turned off, and the output voltage V_OUT is not controlled. In this design, the S_{OFF_M} generated by the off-min (OM) block with fixed cycle is employed so that the falling edge of the C_LKN is reduced to the falling edge of the S_{OFF_M}. This means that the PTS S₂ is turned on for a short time, maintaining control on V_OUT. The control logic and dead time block are used to produce the high side and low side, and to generate the delay time to avoid overlap between C_LKP and C_LKN.

In order to reach the goals mentioned in the introduction section, the proposed low power control (LPC) is designed using a voltage supply V_DD = 1.2 V. V_DD is generated from V_BAT by an internal low drop output voltage (LDO) circuit. Depending on the output load, the LPC uses adaptive bias current due to only using suitable blocks for each operation mode to reduce power loss in internal circuits improving efficiency of the design. Each operation mode of STD is turned on/off based on the changed the output current load and the C_LKP and C_LKN during on-time (T_ON), off-time (T_OFF), and sleep time (T_SLEEP) cycles, as shown in Figure 3.

2.2. The Circuit Implementation

The ACP’s schematic is shown in Figure 4a. The ACP can be use in dual-mode with variable output current and impedance, leading to its DC gain and bandwidth being varied, following the output current load transition. The control logic block generates the control switch signal S_A depending on the output load conditions. With heavy and light loads, EN₁ = ‘1’, S_A can be equal to ‘1’ or ‘0’, and when EN₁ = ‘0’, S_A = ‘0’ the proposed design operates in standby mode (ultra-light load), as shown in Figure 4b. Figure 5 illustrates, both the DC gain and bandwidth of the ACP. In order to reduce output ripple in the heavy load, the PTS switching frequency is set at around 1.3 MHz, thus needing enough bandwidth. Thus, if S_A = ‘1’, this leads to M_A1,2 being added to reduce the output impedance. Simultaneously, when the ACP is biased with 4 µA, the ACP’s bandwidth is improved, leading to a faster comparison and transition. In this case, the DC gain is about 52 dB while having a 10 MHz bandwidth. As a result, the ACP can work at a high frequency. In the ultra-light load mode, the PTS switching frequency can work at a low frequency of 0.25 kHz, the S_A can be set to ‘0’, and M_A1,2 are separated to increase the output impedance, and simultaneously the ACP bias current is now 30 nA, improving DC gain; therefore, the ACP is enabled to operate with high precision at low frequencies. Although the ACP achieves a high gain of 90 dB at a low frequency, the ACP’s bandwidth is reduced to 100 kHz; hence, the ACP’s operation in this case is suitable for ultra-light load conditions.

Figure 6a shows the schematic of the proposed oscillator, which generates a square wave with two different frequencies of 25 MHz (Cycle T = 40 ns) and 10 MHz (Cycle T = 100 ns) during T_ON and T_OFF, respectively. This structure reduces power consumption due to the average current dissipation depended on the changing frequency [33]. In order to generate a high negative voltage, the characteristics of capacitively coupled capacitors [34,35] are applicable. In Figure 6b, the negative generator (NEG) circuit uses high-frequency C_LKA pulses on one plate of the capacitors C_m4,7, and a negative voltage is generated on the other plate of the capacitors C_m4,7. The circuit operates with two phases, C_LKA and C_LKB, reducing charge leakage and reversal losses. The generating negative voltages uses n-MOS due to physical properties, all n-MOS are isolated upon implementation. The isolation loops are designed with separated deep n-wells. According to simulation results, three NEGs are connected in series to obtain a negative voltage of –0.5 V.

A negative voltage for the low side of S_WP signal generated by NLS is used to control PTS S₁. This helps reduce the on-resistance and sizing, leading to the parasitic C_GS of PTS S₁ also being reduced. Therefore, the current consumption of the gate driver (GD) can be reduced. Under heavy loads, the low side of S_WP is a high negative voltage level, which is only required during the T_ON. A schematic of the proposed NLS is illustrated in Figure 7a. To implement on-chip, the size of C_m4,5,6,7 must be small, leading to their lower charge. To use a negative voltage of −0.5 V, the charges in the C_GS (which is bigger than C_m4,5,6,7) of PTS S₁ must be discharged completely to V_SS and then charged to the negative voltage V_NEG produced by NEG circuit. The discharge time of the C_GS of PTS S₁ is very short, equal to the charging time of C_m8. In the heavy load mode, the S_WP signal swings from −0.5 V to V_BAT. While in the light and ultra-light load modes, the swing of S_WP is between V_SS to V_BAT. The control signal of PTS S₁ is shown in Figure 7b. The EN₂ signal generated by the STD block is used to control the operation of the NLS. The S_N signal, which is produced by a level shifter, is always at a high level, and the low side of the S_WP signal is V_SS.

Figure 8a illustrates a current source providing small and stable current, which is continuously refreshed by the C_LKP cycle. In addition, an operational transconductance amplifier (OTA) with a low bias current of 15 nA is used to minimize power consumption. In Figure 8b, the STD detect light and ultra-light load conditions. In comparison to other structures, the STD can detect ultra-light load conditions with very low power consumption using low current consumption comparators (CPs). The sample and hold (S&H) circuits help the voltages (V_H1, V_S1) and (V_H2, V_S2) to maintain balance when the converter operates under heavy loads. When the buck converter operates under the light load mode, the charging of C_H2 is fast, being discharged through M_46,47 during T_SLEEP, leading to V_H2 being reduced faster. During T_ON, the charging of C_S2 is discharged to C_H2, and thus, V_S2 is also reduced. When V_S2 is lower than V_FB, then EN₂ is at a low level (V_SS). As a result, the light load mode is detected. In another case, the buck converter operates under the ultra-light load mode, and C_H1 is discharged through M₄₂ during T_SLEEP, leading to V_H1 also being reduced. During T_ON, the charging of C_S1 is discharged to C_H2, and thus, V_S2 is also reduced. When V_S1 is lower than V_FB, EN₁ is at a low level (V_SS). Thus, the ultra-light load mode is determined. The transistors M₃₃, M₃₅, M₃₇, and M₃₉ work as charge storage elements to mitigate the voltage drop and reduce the noise for V_S1 and V_S2. As shown in Figure 3, there are EN₁ and EN₂ signals, for which the high and low side are dependent on the T_SLEEP cycle to control the modes of the buck converter. When T_SLEEP cycles occur consecutively, V_S1 and V_S2 are adjusted gradually, and then compared to the fixed voltage V_FB according to the operating modes of the buck converter, as shown in Figure 8c.

The delay time (T_{DL_CP}) is added, using a comparator (CP) with a low power consumption. In a buck converter, the duration of T_ON is controlled by the OTD as shown in Figure 9a. The comparator in OTD are periodically activated and deactivated based on EN signal, which is an inverted C_LKP1. By using the comparator in OTD, V_D is compared with sawtooth signal V_R, which is created by R_ON and C_ON circuit characteristics, to create S_TRIG; when V_R is higher than V_D, S_TRIG is used to detect the end of T_ON duration. When S_TRIG = <1>, EN will be <0>, leading to V_D being low due to discharging through M₅₁ and M₅₂ while the comparator in OTD is turned off. The timing variation of C_LKP1 and C_LKP is defined as T_delay which is generated from the control logic and deadtime. The duration of T_delay for the heavy load mode and light/ultra-light modes are shown in Figure 9b and Figure 9c, respectively.

In the light load and ultra-light load modes, the discrete operation of PTS CMOS results in a inversed current in the inductor, which discharges to V_SS, leading to energy loss in the inductor. A zero-current detector (ZCD) has been added to identify the inversed current in order to mitigate inverter current in the inductor L. Figure 10 shows the schematic of the ZCD and its associated signal for ZCD operation. The ZCD block operates only during the T_OFF to reduce energy consumption. The M₆₂ switch remains continuously activated to maintain balance between V_N and V_P. During T_OFF, M₆₄ is activated, and V_SW is compared directly to V_N, utilizing the difference between V_N and V_P to ascertain the inductor’s current. In T_OFF, under the heavy load mode, the V_P signal consistently exhibits a lower magnitude than V_N. In the light and ultra-light load modes, when S_ZCD is elevated and the T_OFF time concludes, by initiating the T_SLEEP time, the S_ZCD signal set up high. The schematic of the off-min (OM) block is presented in Figure 11a, while the schematic of the control logic and deadtime are shown in Figure 11b. The OM is incorporated into the proposed design to produce the signal S_{OFF_M} with a fixed cycle controlling PTS S₂. In the proposed converter operations, the reference voltage V_T is determined by the external voltage, which establishes the duration of the S_{OFF_M} signal. When the S_TRIG signal concludes, the S_{OFF_M} signal begins. The proposed converter operates using the S_{OFF_M} signal, even when the output load is below ultra-light output loads. In this scenario, the C_LKN signal is not entirely deactivated, resulting in the DC-DC buck converter transitioning to standby mode. In Figure 11b, the schematic of the control logic block is used to regulate the duration of T_ON and T_OFF in real-time. The signal S_ZCD is used to prevent inversed current (I_L) of the inductor, the low side of S_C is established for T_OFF, the high side of S_TRIG is established for T_ON duration. The special signal S_{OFF_M} is used to ensure that the proposed converter is not turned off when the output load is too small. In addition, a deadtime duration (T_DT) is generated by delay components to prevent p-MOS and n-MOS switches working simultaneously, as shown in Figure 12a for the heavy load mode and Figure 12b for the light load and ultra-light load modes.

As shown in Figure 13a, the schematic of the level shifter 1 (LS1) is shown. LS1 is used to increases the high-level voltage from V_DD to V_BAT to control the gate drive (GD). The schematic of the level shifter 2 (LS2), as shown in Figure 13b, is used to help achieve a lower slope for the output signal, making logic signal more accurate. Figure 14 shows the schematic of a differential difference amplifier (DDA) with two folded input pairs and sharing cascode with a bias current of 15 nA for each differential pair. The compensation based on the DDA circuit is complex, but it has the advantage of providing a quick response during transients. A conventional error amplifier typically has a differential pair of negative feedback inputs that force the difference between the two input voltages to be small. However, when the DDA circuit is used, there are no significant differences between the pairs V_IN1(−) and V_IP1(+) with V_IN2(−) and V_IP2(+), and at the same time, the fluctuating voltage V_EA does not affect the voltage V_FB. When DDA is in the stable state, V_IN1(−) = V_IP1(+) and V_IN2(−) = V_IP2(+), at which point the voltage V_EA will be in a stable state. In the case of load changes, V_EA will change.

3. Simulation Results

The proposal for a buck DC-DC converter with low biased current consumption in the control block is simulated by using a CMOS 180 nm technology. The deep n-well techniques is implemented in the NVG block. The proposed design is combined with an external capacitor of 10 µF and an inductor of 4.7 µF during running simulation. The chip area occupies 0.31 mm², as shown in Figure 15. In order to avoid the crosstalk noise between the blocks, noise sensitivity, and process variation, we use the layout techniques such as common-centroid, symmetric placement, dummy devices for differential pairs and capacitors and CMOS transistors for each block. During the merging of all blocks, the analog and high-power switching blocks are physically isolated, with shielding and floor planning to minimize crosstalk and noise coupling. Moreover, to operate with a negative voltage of −0.5 V, the deep n-well technique is used during the design layout of the proposed chip.

Table 1. Synthesizing the performance of the proposed DC-DC converter.

Condition	Output Voltage (V)	Output Ripple (mV)	Frequency (kHz)	Efficiency (%)	Load (mA)	TSLEEP (μs)	Input Voltage (V)
Heavy load	1.24	3	1300	93.35	120	0	3.3
Light load	1.235	7	260	88	12	3.7
	1.23	10	30	83	1.2	30
Ultra light load	1.228	12	0.27	65	0.012	3800
Heavy load	1.231	2.8	1230	96.2	120	0	2.8
Light load	1.23	6.5	230	94	12	3.6
	1.228	9.2	28	89	1.2	28.5
Ultra light load	1.225	11.5	0.25	72	0.012	3750

shown the performance of the proposed DC-DC buck converter using AOT, ACP, STD, ZCD, and NLS. Table 1 helps synthesize the results of this proposed converter, also giving an overview on the consistency of performance and important parameters across varying load conditions and input voltages. The buck converter with the AOT control achieves the expected results in terms of performance and stable operation. The voltage of the signals V_OUT, V_SW, and I_L with each separate output load (given I_LOAD equal to 120, 12, 1.2, and 0.012 mA) are shown in Figure 16. In Figure 16a the V_OUT signal has a small ripple and V_SW has no damped oscillations during the falling edge of V_OUT because the C_LOAD capacitor has been charged and discharged at high frequency, and the average current I_L remains high under a heavy load. In this case, when V_OUT has exhibited an increasing ripple and V_SW has damped oscillations during the falling edge of V_OUT due to C_LOAD being charged and discharged at a low frequency, with the average load current I_L is low in the light and ultra-light load modes. The switching frequency and the average load current I_L have depended on the output load variation (I_LOAD). As shown in Figure 16b–d, the T_SLEEP time varies from 3.7 μs to 3.8 ms, the waveforms for V_SW and I_L annotated remain shape steady, while the V_OUT has a gradually increased ripple. To reduce the current loss in the inductor in the heavy load mode, both switches S_WP and S_WN have been turned off, creating an oscillation between L and C_LOAD, which causes the damped oscillations of V_SW during the falling edge of V_OUT.

In Figure 17, the simulation results of the adaptive on-time (AOT) controller generates the signal control S_WP and S_WN shown with two load conditions, which are set to 120 mA and 12 mA, respectively. In the heavy load condition of 120 mA, as shown in Figure 17a, the turn-on time (T_ON) is 450 nS, and the switching frequency is 1.3 MHz, with the S_WP achieves a negative voltage of −0.5 V. The utilization of two PTS S₁ and S₂ switches combined with the control logic block creates a dead time to prevent the conduction mechanism from being interrupted. Under the light load condition of 12 mA, as shown in Figure 17b, the switching frequency is only 250 kHz, and the T_ON is 205 nS. The S_WN turns off when a negative current is detected in the inductor to optimize efficiency. In this mode, noise may occur in the pulses at T_SLEEP due to the oscillation of L and C_LOAD when S_WN is closed. Figure 18a shows how the transient behaves when the load changes from 120 mA to 12 mA and reverses the process. The under voltage and overshoot voltage is 85/89 mV with a recovery time of 60/50 µS. Figure 18b shows the transient response with a light load of 12 μA to 12 mA. The output voltage occupies 20 µS to recover stably, with an undershoot of 79 mV. The current inductor (I_L) responds to changes in the condition of the output load optimizing the converter’s performance. Figure 19 shows the effect of varying temperatures on the output voltage with the input 2.8 and 3.3 V. Under a heavy load, the temperature impact is more pronounced due to higher power dissipation in the switching transistors. As the ambient temperature increases, the junction temperature rises, leading to an increased R_DS(ON) of the power switches, which in turn increases the conduction loss and causes a slight drop in V_OUT. Under a light load, temperature impact is less significant since the internal power dissipation is already minimal. However, control circuits, bias current sources, and analog references may be affected by temperature drift if not properly compensated. During the entire stabilization process, there is no disturbance or oscillation that causes the instability of the output voltage. In particular, the current consumption of the low power control when the current load of 120, 12, and 0.012 mA is depicted in Figure 20. It reflects the average current consumption of the control blocks using a voltage V_DD = 1.2 V from the LDO block. It can be observed that the current consumption of the blocks decreases as the load current decreases, indicating that the system operates optimally with quite efficient current consumption. When the output current load is changed from 12 µA to 120 mA: (1) As shown in Figure 21a, when the battery voltage V_BAT is 2.8 V, the efficiency is increased from 73% to 96.2%. Although the battery voltage V_BAT is increased to 3.3 V, the efficiency is also achieved, increasing from 65% to 93.35%. (2) When the battery voltage is investigated at 2.8 and 3.3 V, the ripple output voltage is as shown in Figure 21b, which changes insignificantly and shows stability around 1.2 V. (3) Figure 21c shows the situation where the switching frequency of the buck converter is varied from 250 Hz to 1.3 MHz. The low consumption of the low-power control block will improve the overall conversion efficiency while still maintaining the accuracy of the output voltage at 1.2 V.

The efficiency of the system can be calculated according to [36]:

$$\mathrm{\eta }={\displaystyle \frac{P_{OUT}}{P_{IN}·P_{Loss}}}$$

(1)

where η is the efficiency of the systems; P_IN and P_OUT are the power of the input and output; P_Loss [37] is the power loss of the buck converter a with the feedback loop.

$$\begin{array}{l}{P}_{Loss}=P_{in}-P_{out}=P_{Switching}+P_{Conduction}+P_{Gatedrive}+P_{Control}+P_{Other}\\ ={\displaystyle \frac{1}{2}}·V_{in}·I_{load}·(t_r+t_f)·f_{Sw}+I_{Load}^2{R}_{DS(ON)}+Q_g·V_{Gatedriver}·f_{Sw}+I_{Ctrl}·V_{DD}+P_{Other}\end{array}$$

(2)

where P_Switching is the switching loss due to non-ideal CMOS switching power; P_Conduction is the conduction loss due to R_DS(ON) in power CMOS; P_Gatedrive is the gate charge/discharge loss of the power CMOS; P_Control is the feedback control loop loss; P_Other is the equivalent series resistance (ESR) loss of inductors, capacitors, and ringing; V_in is the input voltage of the buck converter; I_Load is the output load of the buck converter; t_r and t_f are the clock rise/fall delay; f_sw is the switching frequency; R_DS(ON) is the power CMOS (PMOS and NMOS) on-resistor; Q_g is the gate charge (PMOS and NMOS); V_Gatedrive is the gate control voltage; I_Ctrl is the quiescent current consumed by the feedback loop; V_DD is the voltage supply to the feedback loop. This study requires that the buck converter achieves high efficiency across a wide load range; hence, minimizing P_Loss is essential, particularly under ultra-light load conditions. The AOT (adaptive on-time) controller is presented with a supply voltage V_DD that is less than V_IN to reduce the biased current I_Ctrl, thus reducing P_Control. Furthermore, the control frequency of 1.3 MHz under substantial load situations is employed to mitigate output voltage ripple, whereby P_Switching and P_Gatedrive are comparatively elevated but negligible due to the considerable output power P_OUT. Nonetheless, when the frequency decreases to 250 Hz in the ultra-light load mode, P_Switching and P_Gatedrive considerably impact efficiency due to the minimal P_OUT; however, these losses are substantially mitigated by the reduced switching frequency (f_Sw). For a fair comparison,

Table 2. Comparison between this work and other articles.

Parameter	[20]	[30]	[38]	[39]	[40]	[41]	This Work
Result	Meas.	Meas.	Meas.	Sim.	Sim.	Sim.	Sim.
Num. of Control	1	3	2	1	2	1	1
Operation Modes	AOT	PWM/PFM/RM	PWM/ PFM	AOT	PWM/ PFM	AOT	AOT
Process (μm)	0.13	0.13	0.18	0.18	0.18	0.18	0.18
Input Voltage (V)	1.8–3.3	2.2–3.3	2.2–5	5–12	3.3–5	5	2.8–3.3
Output Voltage (V)	1.2	1.7	1.8	0.33–1.2	0.5–3	1.2	1.2
Inductor (μH)	4.7	3	4.7	2.2	500–3000	1.5	4.7
Output Capacitor (μF)	4.7	3	1	47	50–200	20	4.7
Output Ripple Max (mV)	30	180	N/A	N/A	N/A	5	3
ILOAD Max (mA)	0.0001–2.65	0.01–20	0.2–200	5000	200	500	0.012–120
Efficiency (@12 μA) (%)	62	74.2	77	N/A	N/A	40	73
Peak Efficiency (%)	92.2	92.4	94	96	90	95	96.2
Chip Area (mm2)	0.14	1.1	0.405	N/A	N/A	N/A	0.31

N/A: not available.

contains various references with simulated results, including [36,37,38]. The most important design specifications such as input voltage, output voltage, output ripple, current load, efficiency, and chip area are summarized in the table to compare the achieved performance levels of the proposed design with the state-of-the-art research. It is important to observe that in the application, the input voltage V_BAT ranges from 2.8 V to 3.3 V, requiring the stabilization of the output voltage and the adjustment of capacitors C_F2 and C_F2 to maintain V_DD at 1.2 V. At a voltage of V_BAT = 3.3 V, with C_F1 = 10 nF and C_F2 = 18 nF, the value of V_DD is 1.19 V. At a voltage of V_BAT = 2.8 V, with C_F1 = 14 nF and C_F2 = 18 nF, the voltage V_DD is 1.224 V. Any alterations to the input application will impact BGR2. Consequently, it is crucial to change C_F1 and C_F2 externally to obtain the requisite V_DD voltage within a specified input voltage range of 2.8 to 3.3 V for proper conversion functionality.

4. Conclusions

This paper presents a high-efficiency, low-power buck converter designed for a wide load range, targeting for mobile, IoT, and medical applications. The integration of an adaptive on-time (AOT) controller with a negative clock generator enables the converter to attain substantial efficiency across various output loads. The control block functions at 1.2 V (V_DD) with an emphasis on reducing bias current usage in the BGR1, BGR2, ZCD, DDA, STD, OTD, and ACP blocks. The negative voltage generator (NVG) employs a deep n-well layout approach utilizing CMOS 180 nm technology, with the DC-DC buck converter occupying a chip area of 0.31 mm². The simulation findings indicate that throughout an input voltage range of 2.8 to 3.3 V, the output voltage remains constant at 1.2 V, with a ripple variation of about 3 to 12 mV. The proposed converter achieves a peak efficiency of 96.2% at an output current load of 120 mA and 75% at 12 μA. This indicates that a favorable comparison between the performance of the proposed DC-DC buck converter and the state of the art is possible.