Enhanced Short-Circuit Robustness of 1.2 kV Split Gate Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors for High-Frequency Applications

Abstract

Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (C_rss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the gate oxide and insufficient short-circuit (SC) robustness. In this paper, we propose a device structure to enhance the short-circuit withstand time (SCWT) of 1.2 kV SG-MOSFETs. The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region that expands the depletion region within the JFET region under both blocking mode and SC conditions. Compared to the conventional structure, this reduces the maximum electric field in the gate oxide, enabling a higher doping concentration in the JFET region, which can reduce the specific on-resistance (R_on,sp) to minimize power dissipation during device operation. The SC robustness of PSG-MOSFETs, with an R_on,sp identical to those of SG-MOSFETs, was investigated by adjusting the width of the P-shielding region (W_P). Furthermore, the C_rss,sp of PSG-MOSFETs was compared with that of SG-MOSFETs to analyze the relationship between the W_P and high-frequency figure of merit (HF-FOM), defined as R_on,sp × C_rss,sp. These results demonstrated that the PSG-MOSFET achieved an enhanced SC robustness and HF-FOM in comparison to the SG-MOSFET. Thus, the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications.

1. Introduction

Silicon carbide (SiC) devices, including Schottky barrier diodes (SBDs) and metal oxide semiconductor field-effect transistors (MOSFETs), have become key components in power electronic systems [1,2,3]. SiC devices offer a low specific on-resistance (R_on,sp), superior blocking capability, and excellent thermal conductivity compared to silicon (Si) insulated gate bipolar transistors (IGBTs) [4,5,6]. Furthermore, the fast switching speed of SiC devices, operating at frequencies exceeding 100 kHz, can achieve the advantage of reducing the volume of passive components in power electronic systems [7]. In particular, the utilization of SiC MOSFETs as switching components is becoming increasingly prevalent in DC–DC converters, on-board chargers, and inverters for electric vehicles due to their superior performance [8,9,10].

Reducing the R_on,sp and specific reverse transfer capacitance (C_rss,sp) is crucial for minimizing lower power dissipation, as a significant portion of the power dissipation occurs during the switching operation [11,12]. In particular, during the charging of the C_rss,sp, a simultaneous application of high voltage and current occurs, which can result in a significant power dissipation in SiC MOSFETs. Thus, it is crucial to achieve a lower high-frequency figure of merit (HF-FOM), defined as R_on,sp × C_rss,sp [13,14]. It has been demonstrated that the superior HF-FOM of 1.2 kV Split Gate SiC MOSFETs (SG-MOSFETs) can be achieved without an increase in R_on,sp [15,16,17,18,19,20]. However, electric field crowding occurs at the exposed edge of the poly-Si gate of SG-MOSFETs in the blocking mode, which may cause potential issues with the gate oxide [20,21,22].

Ruggedness and reliability, particularly short-circuit (SC) robustness, are also vital considerations for SiC MOSFETs. SiC MOSFETs exhibit a shorter short-circuit withstand time (SCWT) due to the higher electric field and current density compared to Si IGBTs [23,24]. Under the SC conditions, the lattice temperature of SiC MOSFETs rises rapidly, leading to thermal runaway and surges in drain current (I_D). These phenomena have the significant potential to result in device failure [24,25]. Several approaches for improving the SC robustness of SiC MOSFETs have been reported, but they should entail an increase in R_on,sp [25,26,27,28,29,30]. Additionally, the electric field crowding at the gate oxide of SG-MOSFETs results in a shorter SCWT than conventional MOSFETs (C-MOSFETs) [31]. Nevertheless, limited research has focused on enhancing the SC robustness of SG-MOSFETs.

In this paper, we proposed an approach to enhance the trade-off between the SC robustness and R_on,sp of 1.2 kV Split Gate SiC MOSFETs (SG-MOSFETs). The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region within the JFET region, which serves to expand the depletion region under SC conditions and in blocking mode. The depletion region induced by the P-shielding region can narrow the current path in the JFET region, which results in the suppression of the surge current under SC conditions. In blocking mode, the expanded depletion region of PSG-MOSFETs can serve to protect the gate oxide from the electric field and reduce the reverse transfer capacitance (C_rss).

2. Device Structures and Simulation Methods

Sentaurus TCAD simulations were employed to design and analyze 1.2 kV SiC MOSFETs based on a half-cell size. Figure 1a–c show the 2-D schematic cross-sectional views of the 1.2 kV SiC C-MOSFET, SG-MOSFET, and PSG-MOSFET, respectively. A SiC N-drift region with a background doping concentration of 8 × 10¹⁵ cm⁻³ and a thickness of 10 μm on a SiC N⁺ substrate was implemented. All devices were designed with an inversion channel, an identical channel length of 0.5 μm and a gate oxide thickness of 50 nm. In order to ensure the reliability of the gate oxide, the SG-MOSFET and PSG-MOSFET were designed with an identical length of the overlap region of 0.3 μm between the poly-Si gate and JFET region. The JFET region was designed with a width of 1.5 μm, and a depth of 0.8 μm. Additionally, the JFET region of the C-MOSFET and SG-MOSFET was designed with a doping concentration (N_JFET) of 3 × 10¹⁶ cm⁻³. Note that PSG-MOSFETs were designed with a higher N_JFET than C-MOSFETs and SG-MOSFETs due to their reduced E_ox,max. This can reduce the R_on,sp, which can minimize power dissipation during device operation.

All devices were created through following process simulations, and voltage was applied to each terminal of the devices to analyze its electrical characteristics through device simulations. Figure 2 shows the process simulation flow for the PSG-MOSFET. The PSG-MOSFET followed the same process flow as the C-MOSFET and SG-MOSFET. Note that all ion implantation processes used the Monte Carlo method for precision of simulations. The P-shielding region within the JFET region was formed through ion implantation for the P-source without any additional patterning steps. Additionally, the P-shielding region was designed with a depth of 0.5 μm and a width (W_P) ranging from 0.3 μm to 0.9 μm. Furthermore, it should be noted that the P-shielding region is electrically connected to the source, which effectively improves the electrical characteristics of PSG-MOSFETs. In order to achieve this connection, a contact placement for simulation was created on the surface of the P-shielding region and subsequently merged with the source contact placement.

Table 1. Device parameters used in TCAD simulations.

Parameters [Unit]	Values
Channel length [μm]	0.5
Gate oxide thickness [nm]	50
Half-cell pitch [μm]	3.4
Width of the JFET region [μm]	1.5
Depth of the JFET region [μm]	0.8
Thickness of the N-drift region [μm]	10
Length of the overlap region between the poly-Si gate and the JFET region [μm]	0.3
Width of the P-shielding region (WP) [μm]	0.3–0.9
Depth of the P-base [μm]	1.0
Doping concentration of the N-drift region [cm−3]	8 × 1015
Doping concentration of the JFET region (NJFET) [cm−3]	3 × 1016–1 × 1017
Doping concentration of the P-shielding region [cm−3]	1.2 × 1020

lists all device parameters used in TCAD simulations. Note that all device simulations were conducted with the same device area.

In order to enhance the precision of TCAD simulations, the following models were employed: the Shockely–Read–Hall recombination model and the Auger recombination model were used to predict the electrical characteristics of devices under different temperature conditions [32,33]; the Okuto–Crowell avalanche model was used to accurately predict the reliability and breakdown mechanisms of high-voltage devices [34,35]; and finally, the incomplete ionization model was used to accurately predict and design the conductivity of devices with high doping concentration [36]. The breakdown voltage (BV) was defined as the drain-source voltage (V_DS) when the maximum electric field in SiC, E_ox,max or I_D exceeded 3 MV/cm, 5 MV/cm or 10 μA, respectively. Furthermore, the R_on,sp was defined as the inverse of the slope at a V_DS of 2.3 V from the output curve under a gate-source voltage (V_GS) of 18 V, and the threshold voltage (V_th) was defined as the gate voltage at which the I_D reached 1 mA, following the extraction of the transfer curve under a V_DS of 5 V. Finally, the SCWT was defined as the gate pulse duration at which the drain current surges and thermal runaway occurs under SC conditions [24,25,26,27,28,29,30,31].

3. Results and Discussion

Figure 3 shows the electric field distribution of the SG-MOSFET in blocking mode with a V_GS of 0 V and a drain-source voltage (V_DS) of 1.2 kV. The SG-MOSFET exhibited an E_ox,max of 4.79 MV/cm because electric field crowding occurs at the exposed edge of the poly-Si gate. The critical electric field of SiO₂ in SiC MOSFETs is known to be 8–9 MV/cm [37]; however, the E_ox,max should be to 3 MV/cm or less to ensure the reliability of the gate oxide in the device [38,39]. In contrast, the PSG-MOSFET with a W_P of 0.3 μm achieved an E_ox,max of 2.95 MV/cm, representing a 38.28% reduction compared to the SG-MOSFET. This reduced E_ox,max of the PSG-MOSFET is due to the dispersion of the electric field from the gate oxide into the P-shielding region, which results in a maximum electric field in the P-shielding region of 2.32 MV/cm. In other words, the high electric field in the gate oxide is dispersed by the on-sided depletion region that occurs at the PN junction between the additional P-shielding region and the JFET region. Accordingly, this results in the suppression of the electric field crowding at the gate oxide of the PSG-MOSFET.

Figure 4 shows the E_ox,max of PSG-MOSFETs according to the W_P and N_JFET. As the N_JFET increases, the E_ox,max also increases due to a reduction in the width of the depletion region of the P-shielding region. Conversely, as the W_P increases, the E_ox,max significantly decreases. Since an increase in R_on,sp denotes an increase in conduction loss during device operation, optimization of N_JFET and W_P is crucial. These results indicate that the P-shielding region can effectively suppress electric field crowding at the gate oxide, despite the higher N_JFET of PSG-MOSFETs compared to the SG-MOSFET.

Figure 5 shows the R_on,sp of PSG-MOSFETs according to the W_P and N_JFET. As the N_JFET increases, the R_on,sp decreases due to the expansion of the current path of the device in the conduction mode. Conversely, as the W_P increases, the R_on,sp significantly elevates. In particular, the PSG-MOSFET (W_P = 0.9 μm and N_JFET = 1 × 10¹⁷ cm⁻³) exhibits a R_on,sp of 11.41 mΩ∙cm². In order to achieve an identical R_on,sp as the SG-MOSFET, it is required to design the N_JFET of the PSG-MOSFET with a W_P of 0.9 μm to be much higher than 1 × 10¹⁷ cm⁻³. However, the implementation of a significantly higher N_JFET results in a reduction in the V_th of the device. For the design of the inversion channel, the W_P with a range of 0.3 μm to 0.8 μm was employed, and devices with an identical R_on,sp as the SG-MOSFET were selected, as shown in

Table 2. Device structures with identical R_on,sp as SG-MOSFETs.

Descriptions	Conditions [Unit]		Ron,sp [mΩ∙cm2] (@VGS = 18 V and VDS = 2.3 V)	Vth [V] (@ID = 1 mA)
	WP [μm]	NJFET [cm−3]
Device #A	0.3	4 × 1016	3.78	3.84
Device #B	0.4	5 × 1016	3.67	3.67
Device #C	0.5	5 × 1016	3.81	3.67
Device #D	0.6	6 × 1016	3.80	3.52
Device #E	0.7	7.5 × 1016	3.82	3.37
Device #F	0.8	1 × 1017	3.75	2.96

.

TCAD mixed-mode simulations were conducted to analyze the SC robustness of devices. Figure 6 shows the schematic implemented in the SC test. The gate voltage (V_G) was pulsed from 0 V to 20 V in 0.1 μs. Additionally, an 800 V voltage source (V_DD) was employed at the drain stage. The external gate resistance (R_G) was set to 20 Ω, and the source/drain resistance (R_S and R_D) and inductance (L_S and L_D) were set to 1 mΩ and 1 nH, respectively.

Figure 7 compares the SCWT and R_on,sp of all the devices. The C-MOSFET has a R_on,sp of 3.65 mΩ∙cm² and SCWT of 5.8 μs. By comparison, the SG-MOSFET exhibits a 4.11% increase in R_on,sp (3.8 mΩ·cm²) and an 8.62% decrease in SCWT (5.3 μs), indicating a less favorable trade-off between SCWT and R_on,sp than the C-MOSFET. In contrast, the PSG-MOSFET achieves a superior trade-off between SCWT and R_on,sp as the W_P increases. Accordingly, it is observed that Device #F (N_JFET = 1 × 10¹⁷ cm⁻³ and W_P = 0.8 μm) exhibits the best trade-off between SCWT and R_on,sp. Note that PSG-MOSFETs did not make any sacrifices of static characteristics, including the R_on,sp, to achieve enhanced SC robustness.

Figure 8 shows the SC characteristics of all the devices. Additionally, the solid line indicates the I_D, while the dotted line denotes the maximum lattice temperature. Note that all the devices exhibited thermal runaway and drain surge current at the gate pulse duration of the SCWT. PSG-MOSFETs demonstrate enhanced SC robustness compared to the SG-MOSFET with identical R_on,sp. It is important to note that the proposed device reduces the probability of device failure due to thermal runaway under SC conditions, and does not require the sacrifice of static characteristics such as the R_on,sp to achieve this. Meanwhile, as W_P increases, PSG-MOSFETs exhibit a decrease in the peak drain current under SC conditions (I_SC) and peak value in maximum lattice temperature (T_peak).

Figure 9 shows the I_SC of the SG-MOSFET and PSG-MOSFETs under SC conditions. It should be noted that it is a comparison of the I_SC at the SCWT duration for each device. Device #F, which shows the best trade-off between SCWT and R_on,sp, exhibits an I_SC of 186 A, representing a 12.62% reduction relative to the SG-MOSFET. This reduction in I_SC can contribute to a lower rate of increase in lattice temperature (R_T) under SC conditions, effectively suppressing the positive feedback loop of the lattice temperature, which can enhance SCWT. Accordingly, Device #F exhibits an SCWT of 7.2 μs, representing a 35.85% enhancement in comparison to the SG-MOSFET.

Figure 10 shows the output characteristics of the SG-MOSFET and PSG-MOSFETs. Due to the comparable slope of devices at low V_DS, PSG-MOSFETs can achieve a R_on,sp similar to that of the SG-MOSFET. In contrast, it is observed that PSG-MOSFETs rapidly saturate the drain current at higher V_DS compared to the SG-MOSFET. Furthermore, this tendency appears to intensify as the W_P increases. This indicates that the I_SC is proportional to the drain saturation current (I_D,sat). Figure 11 shows the total current density of the SG-MOSFET (on the left) and Device #F (on the right) in conduction mode (at a V_DS of 20 V) and under SC conditions (at a V_DS of 800 V). Device #F exhibits a wider depletion region within the JFET region compared to the SG-MOSFET in conduction mode and under SC conditions. The narrower current path facilitated by the P-shielding region can effectively suppress the I_D,sat under SC conditions. According to Equation (1), the I_D,sat is inversely proportional to SCWT [40]. Thus, the reduction in I_D,sat can enhance the SC robustness of PSG-MOSFETs.

$$SCWT=A_{chip}\times {\displaystyle \frac{\left(T_{critical}-T_{initial}\right)\times W_{SiC}\times C_V}{I_{D,sat}\times V_{DS}}}$$

(1)

where T_critical is the critical temperature, T_initial is the initial temperature, A_chip is the chip area, W_SiC is the thickness of the chip, C_v is the volumetric specific heat capacity, I_D,sat is the drain saturation current, and V_DS is the drain-source voltage [40].

Figure 12 shows the lattice temperature distribution of the SG-MOSFET and PSG-MOSFETs under SC conditions. It should be noted that it is a comparison of the lattice temperature distribution at the SCWT duration for each device. As the W_P increases, the magnitude and area of lattice temperature of SiC is observed to decrease. In particular, Device #F exhibits a 6.21% reduction in T_peak compared to the SG-MOSFET. According to Equation (2), the I_D,sat is proportional to the R_T [40]. Due to the reduction in I_D,sat, the positive feedback of the lattice temperature is effectively suppressed, which results in the enhanced SC robustness of the PSG-MOSFET.

$$R_T={\displaystyle \frac{dT}{dt}}={\displaystyle \frac{K_T\times I_{D,sat}\times V_d}{A_{chip}\times W_{SiC}\times C_V}}$$

(2)

where K_T is the compensation factor for the non-uniform temperature distribution through the wafer thickness [40].

The C_rss,sp characteristics of all the devices were obtained at 1 MHz through TCAD mixed-mode simulation, as shown in Figure 13. Additionally, the C_rss,sp is normalized as the device area. The SG-MOSFET exhibits lower C_rss,sp than the C-MOSFET, which is a result of the split gate structure. However, the P-shielding region of PSG-MOSFETs has the effect of expanding the depletion region, which results in a reduction in depletion capacitance (C_dep). As a result, PSG-MOSFETs exhibit significantly lower C_rss,sp than the SG-MOSFET, according to Equation (3). Meanwhile, as the W_P increases, the C_rss,sp of PSG-MOSFETs is effectively further reduced.

$$C_{rss,sp}={\displaystyle \frac{1}{A_{active}}}\times {\displaystyle \frac{C_{ox}\times C_{dep}}{C_{ox}+C_{dep}}}$$

(3)

where A_active is the area of the active cell, C_ox is the oxide capacitance, and C_dep is the depletion capacitance.

Figure 14 compares the R_on,sp, C_rss,sp and HF-FOM [R_on,sp × C_rss,sp] across all the devices. As W_P increases, the HF-FOM of PSG-MOSFETs improves significantly. Accordingly, Device #F represents the optimized PSG-MOSFET, achieving the best HF-FOM and enhanced SC robustness compared to the C-MOSFET and SG-MOSFET.

Table 3. Summary of TCAD simulation results.

Electrical Characteristics [Unit]	C-MOSFET	SG-MOSFET	Device #A	Device #B	Device #C	Device #D	Device #E	Device #F
Ron,sp [mΩ∙cm2]	3.65	3.80	3.78	3.67	3.81	3.80	3.82	3.75
Vth [V]	4.0	4.0	3.84	3.67	3.67	3.52	3.37	2.96
BV [V]	1536	812	1649	1642	1752	1883	1817	1812
Eox,max [MV/cm]	4.08	4.79	3.56	3.35	2.84	2.49	2.13	1.81
SCWT [μs]	5.8	5.3	6.1	6.1	6.7	6.9	7.2	7.2
Crss,sp [pF/cm2] (@VDS = 1 kV)	196.19	62.04	30.71	26.89	22.59	18.47	14.33	10.87
Ron,sp × Crss,sp [pΩ∙F] (@VDS = 1 kV)	0.72	0.24	0.12	0.099	0.086	0.07	0.054	0.041

summarizes the TCAD simulation results in this work. The E_ox,max, R_on,sp, SCWT, C_rss,sp, and HF-FOM of Device #F were 1.81 MV/cm, 3.75 mΩ∙cm², 7.2 μs, 10.87 pF/cm², and 0.041 pΩ∙F, respectively. Compared to the SG-MOSFET, Device #F achieved a 62.21% decrease in E_ox,max, a 35.85% increase in SCWT, an 82.48% decrease in C_rss, and an 82.92% decrease in HF-FOM. This demonstrates that the P-shielding region of the PSG-MOSFET effectively enhances SC robustness and HF-FOM, without increasing the R_on,sp.

4. Conclusions

In this paper, 1.2 kV P-shielded Split Gate SiC MOSFETs were designed to enhance the SC robustness compared to SG-MOSFETs. In order to achieve this improvement, PSG-MOSFETs feature a P-shielding region within the JFET region, which can be formed without requiring additional patterning steps. The analysis of the R_on,sp, E_ox,max, and SCWT of PSG-MOSFETs in relation to the N_JFET and W_P demonstrated that the optimal trade-off between SC robustness and R_on,sp occurs at an N_JFET of 1 × 10¹⁷ cm⁻³ and a W_P of 0.8 μm. Under these conditions, the PSG-MOSFET achieved an E_ox,max reduction to 0.38×, an SCWT increase to 1.36×, and a HF-FOM [R_on,sp × C_rss,sp] reduction to 0.17×, while maintaining a R_on,sp identical to that of the SG-MOSFET. These results indicate that the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications.