Power-Law Negative Group Delay Filters
Abstract
1. Introduction
2. Integer-Order Negative Group Delay Filter Transfer Functions
3. Non-Integer Negative Group Delay Filter Transfer Functions
4. Implementations of the Power-Law Bilinear Negative Group Delay Filters
- (a)
- Employing the functional block diagram of a multi-feedback topology, e.g., the Inverse-Follow-the-Leader Feedback (IFLF), and using suitable active elements that offer electronic adjustment of the required time constants and scaling factors [32].Choosing Operational Transconductance Amplifiers (OTAs) as active elements, the resulting structure is depicted in Figure 4, with the realized transfer function being
- (b)
- Employing a Field Programmable Analog Array (FPAA) device, such as the Anadigm AN231E04 device [35,36], where programmability is achieved through the utilization of the switched-capacitor technique. For this purpose, the transfer function in (26) is alternatively expressed as a sum of high-pass, band-pass, and low-pass biquad filters
- (c)
- Employing the concept in [37], the transfer function in (26) is expressed as a ratio of two impedances, i.e., . According to [31], the choice of the impedances depends on the transfer function that will be realized. Additionally, in order for the impedance to be realizable by a Cauer or Foster network, its frequency response must have the form of a low-pass filter. Inspecting the gain responses in Figure 3, it is obtained that the response of the filter has the form of an inverse high-pass filter in the range of interest. Therefore, the impedance will be implemented by a Cauer/Foster network, and will be equal to , while , with being an ohmic resistor with an arbitrary value. The resulting scheme is demonstrated in Figure 6, where the Cauer type-I network is utilized for implementing the impedance . The corresponding design equations are summarized in (30) as,where are the coefficients of the continued fraction expansion of the transfer function [38].



5. Simulation and Experimental Results
5.1. Simulation Results
5.2. Experimental Results
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
| AMS | Austria Mikro Systeme |
| CAMs | Configured Analog Modules |
| CFOA | Current Feedback Operational Amplifier |
| CMOS | Complimentary Metal-Oxide Semiconductor |
| ECG | Electrocardiogram |
| FO | Fractional-Order |
| FPAA | Field Programmable Analog Array |
| IC | Integrated Circuit |
| IFLF | Inverse-Follow-the-Leader-Feedback |
| LHP | Left Half-Plane |
| MOS | Metal-Oxide Semiconductor |
| NGD | Negative Group Delay |
| OTA | Operational Transconductance Amplifier |
| RF | Radio Frequency |
| RC | Resistor Capacitor |
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| Type of Filter | Bandwidth () | Max. GD () |
|---|---|---|
| inv. IO-LP | ||
| inv. PL-LP | ||
| IO-bilinear | ||
| PL-bilinear |
| Parameter | |||
|---|---|---|---|
| (S) | 87.07 | 50.45 | 40.20 |
| (S) | 73.29 | 54.38 | 46.74 |
| 1 | 1 | 1 | |
| 1.393 | 1.407 | 1.411 | |
| 1.996 | 1.999 | 2 | |
| (A) | 9.81 | 4.88 | 3.72 |
| (A) | 7.81 | 5.35 | 4.45 |
| Element | |||
|---|---|---|---|
| () | 4990 | 4990 | 4990 |
| () | 3570 | 4320 | 4750 |
| () | 1370 | 649 | 261 |
| (F) | 0.75 | 1.33 | 1.69 |
| (F) | 4.12 | 9.76 | 25.5 |
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Nako, J.; Psychalinos, C.; Elwakil, A.S.; Maundy, B.J. Power-Law Negative Group Delay Filters. Electronics 2024, 13, 522. https://doi.org/10.3390/electronics13030522
Nako J, Psychalinos C, Elwakil AS, Maundy BJ. Power-Law Negative Group Delay Filters. Electronics. 2024; 13(3):522. https://doi.org/10.3390/electronics13030522
Chicago/Turabian StyleNako, Julia, Costas Psychalinos, Ahmed S. Elwakil, and Brent J. Maundy. 2024. "Power-Law Negative Group Delay Filters" Electronics 13, no. 3: 522. https://doi.org/10.3390/electronics13030522
APA StyleNako, J., Psychalinos, C., Elwakil, A. S., & Maundy, B. J. (2024). Power-Law Negative Group Delay Filters. Electronics, 13(3), 522. https://doi.org/10.3390/electronics13030522

