A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications

Abstract

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP_1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection.

1. Introduction

The need for high data rates has pushed the widespread adoption of high-order modulation techniques, leading to increased complexity and power consumption of RF transceivers [1,2,3]. An energy-effective alternative is represented by the unlicensed 60 GHz spectrum (i.e., from 57 GHz to 64 GHz), which is suited for short-range wireless communications (due to the high atmospheric absorption) at Gbit/s data rates [4]. On the other hand, mm-wave ICs that have been traditionally implemented in BiCMOS technologies [5,6,7,8] can be fabricated by using nanometer CMOS [9,10,11,12], which has become a reference process for system-on-chip (SoC) integration [13]. Indeed, CMOS is crucial to reduce chip cost, power consumption, and area occupation even for mm-wave applications [14] despite several disadvantages with respect to BiCMOS (e.g., higher flicker noise corner, thinner back-end-of-line (BEOL) [15], lower transistor breakdown voltage, lower transconductance at a given current level).

The adoption of simple on–off keying (OOK) or amplitude-shift-keying (ASK) modulation schemes is widespread in mm-wave integrated transceivers [16,17,18,19,20,21,22]. Indeed, in OOK/ASK architectures, whose simplified block diagram is shown in Figure 1, the receiver (RX) exploits non-coherent demodulation and does not need a local oscillator (LO), while the transmitter (TX) does not require a phase-locked loop (PLL) to generate an accurate frequency for the RF carrier [17,23,24]. Specifically, the RX section needs a 60 GHz LNA capable of driving the demodulator with the correct signal level, while keeping the noise sufficiently low.

In the recent literature, mm-wave receivers largely adopt multi-stage amplifier architectures and single-ended topologies to enlarge the frequency bandwidth and reduce current consumption, respectively [23,24].

Although a multi-stage amplifier topology (i.e., three or more amplifier stages) could achieve a wider frequency bandwidth by using resonant matching networks properly tuned at different frequencies, such solutions considerably increase both power and silicon area consumption and degrade the linearity performance in comparison with a compact one-stage amplifier. Moreover, multi-stage amplifier layout is very complex and is highly sensitive to undesired oscillations due to RLC couplings between stages. Therefore, compact one-stage solutions are highly preferable if a proper design tradeoff between frequency bandwidth, gain, power consumption, and linearity is compliant with the application specs.

On the other hand, exploitation of single-ended solutions in a SoC device is very challenging due to poor immunity against common-mode interferences, compared to the more reliable differential architectures. Unfortunately, differential architectures require nearly double power consumption, especially for the LNA when conventional noise/matching design techniques are used [25]. Indeed, most of the LNA design approaches are mainly aimed at noise figure (NF) minimization in 50 Ohm input matching conditions. Unfortunately, they do not address actual problems, such as power consumption and electro-static discharge (ESD) protection, which are crucial in power-constrained mm-wave applications. On the other hand, CMOS integrated circuits are intrinsically vulnerable to ESD incidents and achieving ESD robustness is very challenging as electronic devices continue to shrink in size [26,27,28]. As a result, safeguarding radio frequency (RF) circuits requires a careful balance between circuit performance and robustness. Typically, poor RF performance results from forward power reflection when proper input impedance is not maintained, as could happen when an ESD protection is simply included. The design of on-chip ESD protection becomes increasingly difficult at mm-wave frequencies. Therefore, inductive devices have been proposed as a high-frequency ESD protection alternative to capacitive ones. Indeed, inductive ESD protection can be co-designed with the RF circuit’s matching network [29].

This paper presents a very compact single-stage pseudo-differential LNA designed for 60 GHz OOK receivers. A power-efficient design approach has been adopted to address very low current consumption with sub-1 V supply voltage with the best tradeoff between gain and frequency operating band. ESD protection has been obtained by putting an integrated transformer between the RF pads and the LNA differential inputs [30,31].

This paper is organized as follows. Section 2 reviews the main traditional design approaches for RF/mm-wave LNAs and proposes the adopted amplifier topology and the design methodology, also giving an insight into integrated inductive components. Simulation results using a 28 nm CMOS process are reported in Section 3, while the main conclusions are drawn in Section 4.

2. LNA Description

2.1. State-of-the-Art Design Strategies of RF/mm-Wave CMOS LNAs

The sensitivity of RF/mm-wave receivers is typically dominated by the LNA, especially by its first stage, which is directly connected to the antenna. Several tradeoffs between NF, gain, impedance matching, linearity, and power consumption are involved in the LNA design [25]. In the literature, four design optimization techniques have been proposed: classical noise matching (CNM) [32], simultaneous noise input matching (SNIM) [33], power-constrained noise optimization (PCNO) [34], and power-constrained simultaneous noise input matching (PCSNIM) [35]. Although the reference topology for the LNA is the common-source (CS) amplifier, the cascode topology, shown in Figure 2a, is widely adopted thanks to its large bandwidth, high gain, and especially high reverse isolation. In the following, LNA design optimization techniques are briefly discussed.

The CNM technique is used to achieve the lowest NF of the specified technology. However, it does not guarantee the input matching since the input impedance, Z_IN, is considerably different from the optimum noise impedance, Z_OPT, for both real and imaginary components. This drawback is overcome by the very popular SNIM technique. It is based on a proper choice of the CS transistor size (i.e., M₁ in Figure 2) and the inductive source degeneration, L_S, to set at the operating frequency both the real part of the optimum noise impedance, R_S,OPT, and the real part of the input impedance, Z_IN, equal to the antenna resistance, R_S, (i.e., 50 Ω/100 Ω for a single-ended/differential antenna), respectively, according to the following condition:

$$NF={NF}_{MIN}\mathrm{if}{R}_{S,OPT}=Re \left[Z_{IN}\right]=R_S$$

(1)

The fulfillment of (1) guarantees simultaneous noise and input matching since the imaginary part of Z_IN can be nullified by using a series gate inductance, L_G, as shown in Figure 2b. Thanks to the SNIM technique, the LNA is matched to the antenna and its NF is equal to the minimum noise figure, NF_MIN, at the same time, as stated by (1). Moreover, the NF_MIN can be further reduced by a proper setting of the M₁ gate-source voltage, V_GS1. It is worth noting that the required degeneration inductor value, L_S, decreases with the increasing of the operating frequency and is very low at mm-wave frequencies, thus not appreciably degrading the NF_MIN of the LNA.

Nevertheless, the SNIM approach is useless for low-power LNA design since the current consumption is not a free design parameter, but it is a result of the design procedure. For low-power LNAs, PCNO and PCSNIM techniques have been proposed. The former is aimed at achieving the lowest NF at a given (low) power consumption. However, achievable NF values are considerably higher than the NF_MIN provided by the technology. On the other hand, the PCSNIM technique provides a low-power design alternative. It exploits an additional design parameter, i.e., the capacitor, C_ex, connected in parallel to the CS gate-source capacitance, C_GS. The capacitor C_ex is properly set to achieve condition (1) at the given current consumption of the LNA. However, this approach suffers at higher operating frequencies. The capacitor C_ex degrades the effective cut-off frequency, f_T, thereby reducing the gain of the LNA. For these reasons, the PCSNIM technique can be hardly used at mm-wave frequencies.

In the design of RF/mm-wave LNAs, ESD protection cannot be neglected. On the other hand, ESD protection often produces performance degradation in terms of both input matching and NF, especially at mm-wave frequencies. Two methods, namely co-design and “play and play” design, exist for putting ESD protective features into practice. Large clamping components, such as diodes or grounded gate NMOS networks, frequently with a series resistor, which limits the current, can be added as a “plug and play” element for ESD protection in digital circuits. Unfortunately, these devices cannot be employed in an RF LNA due to their large RC parasitics, which highly affect both noise and input matching performance. On the other hand, the co-design method takes into account both the ESD components and the integrated circuit, thus recovering the flexibility required for cutting-edge circuit design. Employing inductors and transformers for co-design ESD protection has been proposed in the literature [36,37,38]. This allows for adequate ESD protection without compromising design flexibility. However, these solutions are quite space-consuming, which is undesirable in expensive nanoscale CMOS technology. To implement an ESD transformer without significant area penalty and prevent gate-oxide breakdown during an ESD incident, the ESD inductor, L_ESD; and the LNA gate inductor, L_g, are built by means of interleaved coils. Additionally, the transformer galvanic isolation greatly attenuates the risk of residual voltage overshoots at the input, thus further enhancing ESD protection threshold. The parasitics of the ESD transformer can be included in the LNA input matching network by using the co-design approach. Figure 3 depicts a cascode LNA with transformer-based ESD protection.

The impact of the input ESD transformer on the NF can be evaluated by means of an additional noise term, F_added [33], as reported in (2),

$$F_{added}={\displaystyle \frac{R_{PS}}{R_S}}+{\displaystyle \frac{R_{SS}}{{n^{2}R}_S}}$$

(2)

where R_PS and R_SS are the series resistances of the primary, L_ESD, and secondary, L_g, coils, respectively; n is the transformer turn ratio, i.e., $n=\sqrt{L_g/L_{ESD}};$ and R_S is the source resistance. It is evident from (2) that the square of turn ratio reduces the noise contribution of the transformer-based ESD protection network. Therefore, it is advantageous to have a higher turn ratio to minimize the noise. Additionally, the input matching constraint of the LNA should not deteriorate at the operating frequency. For this reason, the equivalent parallel resistor of the ESD inductor, R_P,ESD, as reported in (3), should be much higher than the source resistance R_S, which is determined by the antenna:

$$R_{P,ESD}=\omega Q_{ESD}{L}_{ESD}$$

(3)

where ω is the angular frequency and Q_ESD is quality factor of the ESD inductor, L_ESD. Therefore, the maximization of the quality factor of the transformer coil is required to reduce the NF degradation due to the ESD protection.

2.2. Power-Efficient SNIM with Source Impedance Transformation (PE-SNIM)

The main drawback of the SNIM technique, i.e., its poor suitability to low-power applications, can be overcome by applying the classical SNIM along with a proper source impedance transformation, namely power-efficient SNIM (PE-SNIM). In a traditional SNIM approach, condition (1) determines the W/L ratio of the CS transistor, M₁, and, hence, the LNA current consumption (i.e., drain current, I_D1), given optimum gate-source voltage, V_GS1, that minimizes the NF_MIN. However, the value of I_D1 required for SNIM can be significantly reduced if the source resistance, R_S, seen by the LNA is increased. This could be accomplished by using an additional input matching network. Since LNAs must include ESD protection, the ESD input transformer shown in Figure 3 can also be effectively exploited for the impedance transformation. To this aim, the turn ratio between primary and secondary windings is set to provide the required input impedance step-up transformation [39] without any additional component. For instance, with a 1:2 transformer ratio for an ideal transformer, an impedance transformation of 1:4 is obtained, which means a reduction in the required drain current, I_D1, by a factor of nearly four. Therefore, the application of the PE-SNIM to single-ended LNAs with transformer-based ESD protection allows a considerable reduction in current consumption by means of high-transformation-ratio mm-wave integrated transformers [40].

The PE-SNIM technique becomes mandatory when a differential configuration is adopted. Indeed, using the classical SNIM approach, the required value of the LNA input stage current is nearly doubled with respect to a single-ended approach, since each amplifier branch must be designed for an R_S,OPT equal to R_S/2. Since, differential-like architectures are highly desirable at mm-wave frequencies for their better robustness, the PE-SNIM is the answer to limit the LNA current consumption, as well as provide inherent input single-ended-to-differential conversion. The PE-SNIM technique has been used for the design of a single-stage pseudo-differential LNA for 60 GHz OOK receivers, as detailed in the following subsection.

2.3. PE-SNIM Design of the 60 GHz LNA

Several mm-wave CMOS LNAs use the single-ended architecture for lower power consumption and silicon area [41,42,43], but this choice does not guarantee enough robustness against common-mode noise coming from the substrate and/or voltage supply, while hardily facing the ESD issue. Moreover, very compact one- or two-stage LNAs are preferable to popular multi-stage topologies, being less sensitive to undesired oscillations in a complete receiver while achieving a higher 1 dB input compression point (IP_1dB). For these reasons, a very compact one-stage pseudo-differential 60 GHz LNA with transformer-based ESD protection is proposed. The LNA has been designed to be connected to a differential OOK detector according to the block diagram in Figure 1.

The LNA has been designed in a 28 nm bulk CMOS technology with eight metal layers. The process provides low-voltage threshold (LVT) 0.9 V CMOS transistors that are suited for low-power and high-frequency operation. The available BEOL includes two top copper metal layers of about 1 μm, which can be exploited for the implementation of mm-wave inductive components.

The LNA simplified schematic is shown in Figure 4. The amplifier is connected to a differential antenna (R_S = 100 Ω) and an OOK detector (here represented by an equivalent RC load) at its input and output, respectively. The LNA adopts a single pseudo-differential cascode stage with integrated ESD protection provided by transformer T_IN. The PE-SNIM technique has been adopted to reduce the current consumption, while guaranteeing simultaneous noise and impedance matching by means of inductive degeneration, L_S, and proper sizing of the W/L ratio of the M_1,2 pair. Specifically, transformer, T_IN, performs input impedance transformation (from R_S to 2R_S), thus allowing each LNA branch to be matched to R_S instead of R_S/2 by means of a small inductive degeneration, Ls (i.e., 15–25 pH). Thanks to the PE-SNIM technique, the designed LNA has a current consumption of a 50 Ω matched single-ended stage (i.e., I_D1,2 = 2.9 mA).

The LNA is loaded by a resonant LC network made up of a transformer, T_OUT, and capacitor, C_L, which is also used to directly connect the LNA to the differential input of the OOK detector according to the scheme in Figure 1. A resonant transformer is preferred to a load inductor to enable simple biasing through the center tap and optimum absorption of parasitics thanks to direct input/output connections, while avoiding series coupling capacitors that are critical at mm-wave frequencies.

2.4. Transformer Design

Integrated transformers are crucial for the design of the LNA, especially at mm-wave frequencies. An integrated transformer can be implemented by using four different topologies, i.e., tapped, interleaved, stacked, and interstacked [44,45,46,47,48]. The selection of the suited transformer topology is related to both the BEOL (i.e., thickness of the metals, intermetal oxide thickness, distance from the substrate, etc.) and circuit specifications. Moreover, ground shields are often included beneath the coils to reduce the substrate losses, but their effectiveness is poor at mm-wave frequencies [49,50].

As part of both the input matching and the ESD protection networks, T_IN is very critical, being responsible for noise matching by means of impedance transformation from its primary to secondary coil. To obtain the step-up ratio required for 100 Ω to 200 Ω transformation, the windings must be designed with a turn ratio, N, of about $\sqrt{2}$, which is geometrically difficult to obtain. To this aim, transformer T_IN adopts a simple one-turn interleaved topology, as shown in Figure 5a. Both primary and secondary coils exploit the upper metal M8, along with a small metal width, w, and large spacing, s, to maximize the self-resonance frequency (SRF) at high inductance values. The design rule manual (DRM) of the adopted 28 nm CMOS technology dictates a minimum width of 2.8 μm for both metal 8 and metal 9 to comply with an ESD current of about 1.3 A that is associated with the 2 kV human body model (HBM). Since a 4 µm metal width has been adopted to improve the transformer winding Q-factor, the design is fully compliant with ESD specifications in terms of current capability. For the sake of completeness, an HBM test has been also simulated. It has been carried out by connecting the LNA to the standard HBM consisting of a 100 pF capacitance with a series 1.5 kΩ resistance, which are the average body capacitance and skin resistance, respectively [51]. The LNA achieves the standard level of on-chip ESD protection of 2 kV [38], guaranteeing that the gate voltages of the input pair, M_1,2, are well below the breakdown voltage of 1 V. It is worth noting that in 2008, the ESD Industry Council proposed a lower HBM protection level from 2 kV to 1 kV for scaled CMOS technologies [52] and therefore achieving 2 kV HBM protection in a 28 nm CMOS technology is an excellent result.

The electromagnetic (EM) simulated inductance and Q-factor curves for both coils of transformer T_IN are depicted in Figure 6a,b. The inductances of the primary, L₁, and secondary, L₂, coils are 151 pH and 225 pH, respectively, with a magnetic coupling factor, k, of about 0.4. Both T_IN windings achieve a Q-factor of about 23 at 60 GHz. The step-up ratio of T_IN (i.e., N² = L₂/L₁) is nearly 1.5. The required impedance transformation of about 2 is obtained by setting the secondary winding resonance slightly higher than the primary one, thus exploiting the factor of (1/k) at the expense of slightly higher loss in the network [39]. On the other hand, the output transformer, T_OUT, adopts a stacked topology by using metal 8 and metal 7 for the primary and secondary windings, respectively, as shown in Figure 5b. The two coils have similar performance in terms of inductances and Q-factors thanks to the equal thicknesses of the adopted metal layers. The stacked configuration has been adopted to take advantage of better k (i.e., about 0.7), which allows achieving high enough values for the transformer characteristic resistance (TCR) and hence LNA gain [53].

Table 1. Geometrical/electrical parameters of integrated transformers.

Parameters	TIN	TOUT	Unit
Transformer topology	Interleaved	Stacked
Primary/secondary inner diameter (dIN)	50/68	40	µm
Metal width (w)/spacing (s)	4/5	3/-	µm
Number of turns (n)	1	1	-
Primary coil inductance @ 60 GHz	151	122	pH
Secondary coil inductance @ 60 GHz	225	122	pH
Primary coil Q-factor @ 60 GHz	22.7	18.7	-
Secondary coil Q-factor @ 60 GHz	23.1	18.5	-
Magnetic coupling factor (k) @ 60 GHz	0.41	0.72	-
Self-resonance frequency (SRF)	150	140	GHz

summarizes the main geometrical and electrical parameters of input and load transformers, which have been obtained by using EM simulations.

3. Simulation Results

The LNA performance has been evaluated by means of circuit simulations including the EM-extracted scattering parameters (S-parameters) of the integrated transformers, along with main parasitic effects due to the RF input pads and connections to transistors. Specifically, circuit and EM simulations were carried out using SPECTRE RF and Keysight Momentum MW, respectively. The design kit of the adopted technology provides an accurate model of CMOS transistors based on measurements up to 110 GHz, including all metal connections up to metal 3. Moreover, the reported results take into account extensive EM simulations of main RLC layout parasitics. Specifically, the most critical layout connections are the 60 GHz input path to MOS pair, M_1,2, and the ground reference for the source connection, which determine both LNA input matching and noise performance. For the sake of clarity, Figure 7 depicts the simplified layout floorplan related to the LNA input network including transformer T₁ and the metal plane for ground path.

The proposed LNA draws only 5.8 mA current from the 0.9 V supply voltage. Its input matching, S₁₁, is depicted in Figure 8. The S₁₁ is lower than −13 dB in a 7 GHz bandwidth around 60 GHz with a minimum of −19 dB at 60 GHz, thus demonstrating the effectiveness of the adopted transformer-based input matching network.

When the LNA is close to the equivalent load of the OOK detector (i.e., in the order of a few kilohms), it exhibits a voltage gain higher than 21 dB at 60 GHz with a 3-dB bandwidth, BW_3dB, of about 2 GHz, as shown in Figure 9. Figure 9 also shows the LNA noise figure, which attains a remarkable value of 6.3 dB at 60 GHz, including the loss due to the input transformer, T_IN. Such a performance confirms the soundness of the proposed PE-SNIM technique, with power consumption as low as 5.2 mW.

Moreover, thanks to its one-stage topology, the LNA also achieves excellent performance in terms of the input referred 1-dB compression point, IP_1dB, which is about −5 dBm, well above the typical maximum signals at the antenna, as shown in Figure 10.

Table 2. LNA performance and comparison with the state of the art.

Parameters	[21] (S)	[64] (S)	[65] (S)	[59] (P)	[66] (S)	[41] (S)	[60] (M)	[61] (M)	[62] (M)	[63] (S)	This Work (S)
No. stages/topology	6 CS	2 CAS	4 CS	2 CS	2 CAS	2 CAS	3 CAS	2 CAS	2 CAS	2 CAS	1 CAS
Differential (d) /Single-ended (s)	d	s	s	d	s	s	s	s	s	d	d
ESD protection HBM Level (kV)	NO	NO	NO	NO	NO	NO	6.5/1.5	>8	3	2	2
Frequency (GHz)	60	60	60	58	60	60	60	60	60	60	60
NF (dB)	4.9 (M)	3.5	4	4.4	4.9	3.5	8.6	5.3	8.6	6.9	6.3
Gain (dB)	24.5	13	13	22.7	18.1	6.7	20.4	17.5	10.2	19.3	21.4
BW3dB (GHz)	14 (53–67)	9 (55–64)	6 (55.2–61.2)	9 (54–63)	18.3 (49.8–68.1)	7 (57–64)	7 (55–62)	7 (54.5–61.5)	10 (55–65)	6 (56.8–62.8)	2 (59–61)
IP1dB (dBm)	−27 (M)	−17.8 (M)	−16 (M)	−16.1	−21.1 (M)	−22.4	−20	−20.63	−11	−14	−4.7
Voltage supply (V)	1.2	1	1	-	0.85	1.1	2.4	1.5	1	0.9	0.9
Current consumption (mA)	14	8.8	4.4	-	4.2	12	27	12	30	9.18	5.8
Power consumption (mW)	16.8	8.8	4.4	29.9	3.6	13.2	65	18	30	8.3	5.2
CMOS process	90 nm	65 nm	90 nm	40 nm	22 nm FD SOI	40 nm	130 nm	65 nm	65 nm	28 nm	28 nm
FoM1/FoM2	0.08/20	1.19/178	2.95/295	0.62/96	1.12/342	0.1/12	0.03/3.52	0.21/24.65	0.26/43.25	1.42/142.5	25.5/851
(S): simulations     (M): measurements     (P): post-layout simulations
[57] FoM1 = Gain [dB] ∙ Freq [GHz] ∙ IP1dB [mW]/(F − 1) ∙ PDC [mW];
[58] FoM2 = Gain [dB] ∙ IP1dB [mW] ∙ BW [MHz]/(F − 1) ∙ PDC [mW] (where F is the noise factor)

reports the main performance of the proposed 60 GHz LNA, while comparing it with other recently published works. In the last few years, different figures of merit (FoMs) have been proposed to compare RF/mm-wave LNAs [54,55,56,57,58]. The comparison reported in Table 2 adopts the FoMs defined in [57,58], which include all main LNA performance parameters (i.e., gain, noise, power consumption, frequency bandwidth, and linearity). Despite the transformer-based ESD protection, the proposed LNA overperforms all other works according to both adopted FoMs. Only [59] adopts a pseudo-differential topology, but with six times the power consumption. Moreover, the LNA exhibits a first-rate linearity thanks to its compact one-stage topology, while providing higher or comparable gain with the other works in Table 2. It is worth noting that, although the achieved NF is the highest reported, mainly due to the input transformer, it is still sufficient to keep the signal-to-noise ratio of the overall RX well above the level required for OOK demodulation. Table 2 also contains four papers [60,61,62,63] to compare the proposed amplifier with other LNAs with ESD protection. It is worth noting that achieving ESD protection is increasingly more difficult as the technology node scales due to the reduced breakdown voltage.

4. Conclusions

A compact 60 GHz LNA for short-range Gbit/s wireless communications has been presented. The amplifier adopts a single-stage pseudo-differential topology with integrated transformer-based ESD protection. An effective PE-SNIM technique has been exploited to reduce power consumption. The amplifier is highly linear thanks to the 1-stage topology, with an IP_1dB of −4.7 dBm. The LNA exhibits a sensitivity of at least −40 dBm and can drive an OOK detector with a 60 GHz 80 mVpp OOK modulated signal up to 1 Gbit/s, with an energy efficiency of about 5 pJ/bit. Thanks to the proposed LNA design, a 60 GHz OOK receiver can be implemented with an overall consumption lower than 15 mA. It is worth mentioning that the impact of process variations on the performance of the proposed one-stage LNA within the OOK receiver is mainly related to a bandwidth reduction of about 20% and therefore of the maximum data rate, which is due to the frequency shift of the resonance of input/output LC networks. On the other hand, a degradation of both gain and NF performance appears only for slow–slow (SS) corners, but it has an acceptable effect on the sensitivity of the receiver.