Millimeter-Wave GaN High-Power Amplifier MMIC Design Guideline Considering a Source via Effect

Abstract

A millimeter-wave (mmWave) gallium nitride (GaN) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) was implemented, considering a source via effect. In this paper, we introduce guidelines for designing GaN HPA MMICs, from device sizing to meeting high-power specifications, power matching considering source via effects, schematic design of three-stage amplifier structures, and electromagnetic (EM) simulation. Based on the results of load pull simulation and small-signal maximum stable gain (MSG) simulation, the GaN high-electron-mobility transistor (HEMT) size was selected to be 8 × 70 μm. However, since the source via model provided by the foundry was significantly different from the EM results, it was necessary to readjust the power matching considering this. Additionally, when selecting the source via size, the larger the size, the easier the matching, but since the layout of the peripheral bias circuit is not possible, a compromise was required considering the actual layout. To prevent in-band oscillation, an RC parallel circuit was added to the input matching circuit, and low-frequency oscillation was solved by adding a gate resistor on the PCB module. The proposed PA was fabricated with a commercial 0.1 μm GaN HEMT MMIC process. It exhibited 38.56 to 39.71 dBm output power (P_out), 14.2 to 16.7 dB linear gain, and 14.1% to 18.2% power-added efficiency (PAE) in the upper Ka band. The fabricated GaN power amplifier MMIC shows competitive P_out in the upper Ka band above 33 GHz.

1. Introduction

A gallium nitride (GaN) semiconductor is a material with a high energy bandgap compared with conventional silicon (Si) semiconductors. Therefore, it possesses a high breakdown voltage and excellent electron mobility characteristics, resulting in high power density at high frequencies. Additionally, it boasts resistance to high pressure and temperature, rapid signal conversion speed, and high efficiency [1]. These attributes have garnered it attention as a next-generation power semiconductor, and its commercialization is rapidly advancing, particularly in smartphone fast chargers, 5G/6G mobile communications, and electric vehicle power systems. According to a recent forecast by the market research firm Yole Development, the global GaN power semiconductor market is expected to grow from USD 185 million in 2022 to USD 2.035 billion by 2028, representing a compound annual growth rate (CAGR) of 49% [2].

GaN semiconductor devices, especially GaN high-electron-mobility transistor (HEMT) devices, known for their excellent electron mobility characteristics, have seen widespread adoption in high-frequency integrated circuits for transmitting and receiving. These circuits can operate stably at high frequencies and handle high power, meeting the increasing demands of radio and telecommunication applications. Active research in this field is ongoing [3,4,5]. In particular, GaN semiconductor devices are emerging as the sole high-frequency power semiconductors suitable for use in semiconductor-based solid-state power amplifiers (SSPAs), replacing the vacuum tube-type traveling wave tube amplifiers (TWTAs) traditionally used in military applications [6,7].

With advancements in semiconductor process technology, high-frequency circuits for wireless communication have been integrated and miniaturized using monolithic microwave-integrated circuits (MMICs). GaN HEMT MMICs have been widely studied as high-power, broadband power amplifiers due to their advantage of high power density at high frequencies [4,5,6].

Millimeter-wave (mmWave) high-power, high-efficiency GaN power amplifiers are in high demand for satellite communications and military applications. MmWave high-output power amplifiers have been applied to GaN HEMT MMICs, and output power (P_out) results as high as 40 W in the Ka band have been recently reported [8]. It was designed using undisclosed internal semiconductor processes from Japan and the U.S. and was based on parallel power combining of commonly used output-stage transistors. However, this has been limited to the lower Ka band (defined as 33 GHz or lower), and output power results of 10 W or more in the upper Ka band (defined as 33 GHz or higher) have been published in several papers [9,10,11,12,13]. Ref. [9] demonstrated over 10 W of P_out using GaN HEMTs with a power density of 5 W/mm at 35 GHz on SiC substrates, known for their excellent thermal conductivity. Ref. [10] also achieved 9 W of P_out and an outstanding power-added efficiency (PAE) up to 33% in the upper Ka band using SiC substrates. Ref. [12] attained more than 10 W of P_out in the 18–40 GHz wideband by utilizing a combination of distributed amplifier and reactive matching topology, which are two common wideband design techniques. These studies focused on high-power amplifiers (HPAs) implemented with GaN-on-SiC technology. Recently, GaN high-power amplifier (HPA) MMICs using GaN-on-Si technology, which can be fabricated on the same substrate as conventional integrated circuits and offer cost competitiveness, have also been actively studied [13].

In this work, we design and implement an mmWave high-power GaN power amplifier (PA) MMIC for future satellite communication applications. Additionally, as mentioned above, GaN-on-Si has significant potential and advantages, so we design our MMIC using this process. In particular, the upper Ka band, which has relatively few design examples among the Ka bands, is selected as the operating frequency, and the design process is systematically summarized.

Figure 1 illustrates the design process of the mmWave GaN PA MMIC in this study. Initially, the MMIC’s specifications are determined based on the intended application. For a power amplifier MMIC, typical specifications include saturation output power (P_sat), power-added efficiency (PAE), power gain, and chip size. Subsequently, load pull simulation of GaN HEMTs is conducted to determine the optimal transistor size that meets the specifications. Particularly at high frequencies, above 30 GHz, electromagnetic (EM) verification of the source via structure holds significant importance in the design of GaN HEMT power amplifiers. Given that load pull results are strongly influenced by the source via model at such frequencies, more accurate predictions based on EM are crucial. Once the optimal GaN HEMT size is determined through load pull simulation, the power stage and drive stage are designed to fulfill the input and output power requirements. This involves determining the number of stages needed for the total power amplifier. Subsequently, schematic-level MMIC design and layout are executed using the design kit provided by the foundry. To enhance the realism of simulation results, partial EM simulation is conducted during layout to validate the layout structure’s proximity to schematic simulation. Finally, a full EM simulation is performed on the entire layout to ensure satisfaction with specifications before tape-out.

This paper is organized as follows: In Section 2, the above-mentioned mmWave GaN PA MMIC design process will be described in detail in sequence and simulation results will be presented. In Section 3, the designed PA is fabricated using a commercial process and the measurement results are presented, followed by conclusions in Section 4.

2. Circuit Design

In this study, we set the goal of designing an MMIC with an average output power over 8 W in the upper Ka band. Additional specifications include a power gain of more than 10 dB and a PAE of more than 10%. The design of a Ka-band PA MMIC to meet these specifications is accomplished as follows.

2.1. Load Pull Simulation

The output power from a transistor depends on the load impedance. Load pull is an essential process in power amplifier design, where the output power or power efficiency of the transistor used is investigated as a function of the load impedance at a given operating frequency and bias. At low frequencies, load pull data can be obtained through measurement by connecting an impedance tuner to the transistor to be used. However, at high frequencies above millimeter waves, the equipment setup is difficult, and the measurement error is large. Therefore, it is common to perform load pull simulation using an accurate large-signal model.

RF power is proportional to RF current and RF voltage. Therefore, if the driving voltage remains constant, the larger the size of the transistor, the greater the output power. However, as the transistor size increases, so does the parasitic capacitance. This leads to increased mismatch between current and voltage swings at high frequencies, as well as higher DC power consumption. As the size increases beyond a certain point, the incremental gains in output power diminish, leading to a decline in efficiency. Additionally, surpassing a specific threshold in transistor size leads to a decrease in high-frequency linear gain due to parasitic capacitance. This necessitates higher input power in power amplifier design. Hence, selecting the optimal GaN HEMT size requires consideration of these factors.

In this design, GaN HEMT devices with a maximum available gain (MAG) or maximum stable gain (MSG) of at least 10 dB in the Ka band, prior to load pull analysis, are chosen as the primary candidates. Figure 2a,b show the simulated MAG and stability factor according to the size of GaN HEMTs. Depending on the gate fingers and gate widths provided by the foundry, the simulated GaN HEMT devices with the largest sizes while satisfying an MAG or MSG of more than 10 dB are 6 (hereafter gate finger) × 70 (hereafter gate width) μm, 6 × 100 μm, 8 × 70 μm, and 8 × 100 μm, as shown in Figure 2a. When compared with the same unit gate width, the device with six gate fingers had a higher MAG of about 2 dB compared to the device with eight gate fingers.

Load pull simulations were performed on these four transistors. First, we set the input impedance to 50 ohms and used the impedance tuner to vary the load impedance value to find the load impedance that produced the maximum output power, then performed a source pull on the input side to find the source impedance that produced the maximum output power again. Finally, with the optimal source impedance set, load pull was performed again to determine the final load impedance.

Figure 3a–d show the GaN HEMT load pull simulation results for different sizes, respectively. The drain voltage is set to 12 V and the gate voltage is set to −1 V, referring to the foundry-provided model guide document. The frequency is set to a single frequency in the Ka band and the input power is set to 25 dBm.

As shown in Figure 3a–d, the 8 × 70 μm GaN HEMT exhibited the highest PAE of about 38%, while the 8 × 100 μm device had the highest output power of about 33.4 dBm. The optimal load impedance values are 9 to 10 ohms for the 6 × 70 μm device and 5 to 6 ohms for the rest of the devices for the real part. The 8 × 100 μm GaN HEMT exhibits high output power, but its maximum PAE is approximately 32%, which is more than 4% lower than that of the other devices. Therefore, the 8 × 70 μm GaN HEMT, which offers the highest PAE and a modest 0.4 dB difference in output power, is selected as the unit cell transistor for the power amplifier.

2.2. Source via Effect Consideration

Because GaN HEMTs are highly self-heating due to their high power density, they often use ground-source via structures to dissipate the generated heat to the outside [14]. Figure 4 shows the GaN HEMT common source layout and the three-dimensional structure of the source via holes used in it. As shown in Figure 4, the source via hole is modeled as an inductance because it connects the source terminal to the ground with a hole about 100 μm thick, and the inductance value can vary with frequency, which needs to be verified by EM simulation. Larger inductance values reduce the maximum output power and maximum possible efficiency at high frequencies when performing load pull. To account for this, it is recommended to increase the width of the source via as much as possible, but the width should be adjusted appropriately so that it does not interfere with the layout of other circuits. In this design, a 200 µm wide ground via hole is used as the source via hole.

GaN HEMTs, characterized by high power density, often employ ground-source via structures to dissipate generated heat. Figure 4 illustrates the common source layout of GaN HEMTs along with the three-dimensional structure of the source via holes. These holes, approximately 100 µm thick, act as channels linking the source terminal to the ground and are represented as inductors in modeling. The inductance value is frequency-dependent, necessitating verification through EM simulation.

Higher inductance values may restrict maximum output power and efficiency at high frequencies during load pull. Therefore, widening the source via is recommended, ensuring it does not interfere with the layout of other circuits. In this design, a 200 µm wide ground via hole is utilized as the source via.

Figure 5 compares the design kit model of the ground via hole, provided by the foundry, with EM simulation results obtained from the same device layout. The EM verification reveals an additional phase increase of approximately 8 degrees in the upper Ka band. This corresponds to an inductance of about 15 pH at that frequency.

Figure 6a,b demonstrate the variation in load pull P_out and PAE depending on the source ground model. As shown in Figure 6a,b, the P_out and PAE progressively deteriorate as the source ground moves away from the ideal ground and closer to the EM data-based via-hole model that reflects the actual layout. Particularly in Figure 6a, a noticeable reduction in P_out, exceeding 1.3 dB, is observed when the source ground via-hole model given from the foundry design kit incorporates additional inductance consistent with EM simulation results. Consequently, the overall system budget to meet specifications must include allowances for the reduction in maximum P_out due to parasitic inductance introduced by the source via holes.

2.3. Unit Power Cell Schematic Design and System Budget Calculation

After determining the appropriate sizing of the GaN HEMT for the unit power cell based on the earlier load pull simulation results, the single-stage PA is designed using the practical design kit. Initially, for simplicity in design, the matching circuit can be conceptualized as an ideal passive element and later substituted with the actual passive element model from the design kit.

While the load impedance circuit remains consistent, the approach to implementing the input impedance matching circuit varies. To achieve a source impedance of 50 ohms on the Smith chart, two different structures can be utilized for the input matching circuit. Figure 7a,b illustrate the schematics for each structure: Figure 7a presents the input matching as a shunt L–series C–shunt L–series C structure, while Figure 7b depicts the input matching as a shunt C–series L structure. However, in this case, the stability at low frequencies is poor; a series R–C circuit is added with an additional dc block capacitor.

Figure 8a,b present a comparison of simulated S-parameters, P_out, and PAE based on different input matching structures. When using the design kit model with losses, the simulated P_out results indicate a reduction of over 1 dB compared to the load pull simulation. As depicted in Figure 8a,b, the simulation comparison reveals that the shunt C–series L structure exhibits broader S21 and P_out characteristics due to its single resonance structure and the incorporation of an R–C stabilization circuit. Conversely, the shunt L–series C–shunt L–series C structure demonstrates relatively narrower S21 and P_out characteristics owing to its double resonance, which distributes S21 across two frequencies. Increasing the stage number of the amplifier to achieve higher gain further reduces the bandwidth, so a unit cell design with a higher bandwidth is more favorable under the same conditions. Thus, the shunt C–series L structure is selected as the unit power cell design for this study.

Based on the unit power cell simulation results outlined above, the system budget is calculated, taking into account the maximum available input power and the minimum required output power. The entire power amplifier stage is then configured as shown in Figure 9. As shown in Figure 9, assuming the input power available is up to 25 dBm and the required minimum of 39 dBm, a minimum of three stages are required. The first stage focuses on achieving high gain with two unit power cells, the second stage focuses on driving the output power with four unit power cells, and the third stage focuses on achieving maximum output power through power combining with eight unit power cells.

2.4. MMIC Schematic Design

A three-stage power amplifier is designed based on the single power cell designed earlier and the calculated system budget. The input and output ports of each stage are designed to be 50 ohms, but the inter-stage matching can be optimized with proper tuning to account for the total chip size.

In the power stage design, to simplify the bias circuitry, we implement an output matching circuit for each power cell, tying them together in the primary and laying out the drain bias circuit to be common to all four power cells. This changes the output impedance matching circuit of power cells and puts a shunt capacitor in the middle of the inductive lines. Via holes are required to connect shunt capacitors to ground, which introduce parasitic inductances that are not negligible in the mmWaves. The schematic variation from the initial load-matching circuit to a load-matching circuit that takes into account the layout for parallel power combining and via-hole inductance is illustrated in Figure 10. In this work, the inductance of the via hole is extracted based on EM, and the admittance when connected to the shunt capacitor is calculated and compared with the admittance of the shunt capacitor and ideal ground structure, and the equivalent capacitance could be designed to have the same admittance value. Figure 11 shows the transformation of the admittance when the inductance due to via holes is taken into account, where C and C′ are the original shunt capacitance and the modified shunt capacitance, L is via-hole inductance, and ω is angular frequency.

$$Y=j\omega C=\frac{1}{\frac{1}{j\omega C^{\prime }}+j\omega L}=\frac{\omega C^{\prime }}{1-{\omega }^2{LC}^{\prime }}$$

(1)

$$C^{\prime }=\frac{C}{1+{\omega }^{2}LC}$$

(2)

From Equations (1) and (2), as the value of L is added, the value of C′ will be smaller than that of C. Therefore, the via-hole inductance can be extracted by EM and the proper shunt C value can be found. The ground via-hole size for shunt C for load matching is 50 μm, which is chosen considering the minimum separation distance from the source via hole of the neighboring transistors. In this case, the inductance value extracted from EM simulation is approximately 45 pH. Originally, the shunt capacitance is 150 fF assuming an ideal ground, but the shunt capacitance is reduced to 120 fF after considering the via-hole inductance. In this case, the simulated comparison of P_out for the parallel power combining of the four power cells between ideal ground and via-hole inductance in the load-matching circuit is shown in Figure 12. As shown in Figure 12, the output power is not reduced in the upper Ka band and the load-matching circuit is well converted.

Figure 13 shows the schematic of the complete power amplifier MMIC. The GaN HEMTs used in each stage are identical at 8 × 70 μm, and each stage is symmetrical on the upper and lower sides. The second and third stages are designed to bundle the gate bias lines and drain bias lines of the power cells for convenient bias supply. The line length is minimized to reduce the influence on the input–output matching as much as possible. However, the line thickness is designed considering the current allowance range for the drain bias line.

Figure 14a,b show the simulation results of the entire power amplifier MMIC designed at the schematic level. The bias condition is V_DD = 12 V and V_GG = −1.45 V. Figure 14a shows the small-signal S-parameter simulation results, showing S21 of approximately 16 to 19 dB at frequencies of the upper Ka band, while S11 and S22 are designed to obtain values below −15 dB, with S11 being frequency-shifted up to minimize gain reduction at high edge frequencies. Figure 14b shows the harmonic balance simulation result at a single frequency in the Ka band, showing a saturated P_out of about 40.7 dBm and a PAE of 25%.

2.5. MMIC Layout and EM Verification

After the schematic design, the MMIC layout for chip fabrication should be made to reflect the schematic, and EM verification is finally performed to validate the performance of the chip layout. As the layout progresses through the stages, partial EM simulations are performed to tune and optimize the layout similarly to the simulation results performed at the schematic level. Typically, EM simulation results may degrade due to coupling or radiation effects that are not accounted for in the schematic. Therefore, it is important to layout the design in a way that minimizes these issues. In addition, odd mode oscillation is an important consideration in the layout of power amplifier MMICs. When a power amplifier operates, large input and output signals are passed through the circuit, and if the power-combined power cells are not exactly symmetrical, the RF signal is directed to one side, which can damage transistors or cause them to fail. To prevent this odd mode oscillation from occurring, the layout must be exactly symmetrical to ensure that the RF signal is uniformly passed through each power cell, and large shunt resistors can be added to the gate or drain side of the transistor to block or absorb the oscillation if it occurs.

Figure 15a shows the final layout of the three-stage power amplifier MMIC. To achieve a compact chip size, the GaN HEMTs in the power stage are power-combined by sharing the source via ground. The top-to-bottom layout is symmetrical to prevent odd mode oscillations, and partial verification is performed with EM simulations. Finally, a full EM verification of the entire chip is performed. The EM tool used is Keysight’s ADS 2022 Momentum. Figure 15b shows the EM structure with the ports set up, except for the transistors, to perform the full EM simulation, and Figure 16a,b show the simulation results after full EM verification.

As shown in Figure 16a, the full EM-based simulation represents an S21 characteristic similar to the schematic level, with a narrower bandwidth and poorer S11 and S22 characteristics. Figure 16b presents the harmonic balance simulation results as a function of frequency, indicating an output power ranging from 39.3 to 41.4 dBm and a PAE between 17.4% and 24.6%.

3. Implementation and Measured Results

3.1. Implementation

The proposed PA is fabricated using a commercial 0.1 μm GaN HEMT MMIC process with a cut-off frequency (f_T) of 105 GHz and a maximum oscillation frequency (f_MAX) of 155 GHz. Figure 17 shows the chip photograph of the proposed PA. The fabricated MMICs are packaged for measurement and printed circuit board (PCB) modules are fabricated including packaged MMICs. GaN HEMT devices generate significant heat, underscoring the importance of die attachment and packaging technologies for effective heat dissipation. In this study, RF measurements are performed by high-power RF ground–signal–ground (G-S-G) probes, and the DC bias supply is designed to be supplied by DC lines on PCB modules rather than probe needles. This is due to the high output power, which results in large currents of several amperes.

Figure 18 shows the fabricated GaN MMIC module. The oscillation is caused by an unwanted loop inside the circuit, which causes the feedback signal to add up to the input signal, resulting in positive feedback. A simple but effective way to prevent this is to add a resistor inside the circuit. To mitigate degradation in RF performance, resistors are frequently employed in series or parallel with bias circuits, chosen for their minimal impact on RF signals. Particularly, in drain bias circuits, where a significant voltage drop occurs due to drain current, a resistor is typically connected in series with the gate bias circuit. In this study, series resistors are added into both the gate bias circuit within the MMIC and the DC power lines for the gate biases on the PCB to prevent oscillation. The used resistors are 30 ohms both within the MMIC and on the PCB module. The following measurements are taken with the fabricated GaN HEMT power amplifier MMIC module.

3.2. Measured Results

The measured S-parameter is shown in Figure 19. The bias condition is V_DD = 12 V and V_GG = −1.65 V. The total quiescent current is 1170 mA. As illustrated in Figure 16, the designed PA MMIC exhibits an unusual S21 response near approximately 10 GHz, raising concerns about oscillations. However, no significant oscillations were observed in the S-parameter measurements or spectrum measurements. Moreover, the measured stability factor exceeded 2.5 across the frequency range from 0.1 to 40 GHz. In Figure 19, the frequency with the highest S11 value is 12.7 GHz, which represents −0.484 dB, while S22 is −1.182 dB at the same frequency. The measured S22 shows −0.481 dB at 3.4 GHz. Although these are frequencies where oscillations are a concern, they are below 0 dB in the measured S-parameter. The measured S21 is 12.8 to 16.6 dB in the upper Ka band with a peak at 34.3 GHz. The measured S11 is −4.0 to −7.3 dB in the upper Ka band. The measured S22 is −8.4 to −17.9 dB in the upper Ka band. The small-signal S-parameter measurements show generally similar results to the simulations. But the measured S11 and S22 have poor input matching and a downward shift in output matching frequency compared to the simulation. This is thought to contribute to the sharp decay of S21 at high edge frequencies. It is also speculated that the self-heating effect caused by the large current during the measurement process reduced the overall S21.

Next, to examine the output power characteristics of the fabricated PA MMIC, we configured the large signal measurement setup as shown in Figure 20. Figure 21a,b illustrate the RF power measurement results of the fabricated PA MMIC as a function of input power and frequencies. The bias conditions during measurement are the same as the ones shown in Figure 19. To minimize the self-heating effect of the GaN HEMT MMIC, a pulsed signal with a duty cycle of 10% and a period of 1 ms is applied to the RF input. Figure 22a,b show output power spectrum screens when only DC bias is applied and when both DC bias and a 3 dBm RF signal at one operating frequency are applied. As mentioned above, we did not observe any large output signals at other frequencies that would have affected the measurement results, and the output power graph shows a typical slope in Figure 21a,b. The irregularity in the lines of Figure 21a,b in the middle is presumed to be due to measurement error. However, in the P_out-saturated region, they demonstrate a tendency to converge to a certain value without issues. As shown Figure 21a, the measured P_out is 38.5 to 39.7 dBm in the upper Ka band. As shown Figure 21b, the measured PAE at saturated P_out is 14.1% to 18.2%. The peak PAE is 19.5% when P_out is 39.45 dBm. At maximum P_out, the associated gain is approximately 11 to 13 dB. The 1 dB compression point (P_−1dB) is found to be approximately 34.5 to 39.4 dBm in the upper Ka band.

Next, third-order intermodulation distortion (IMD3) is investigated to evaluate the linearity of the fabricated PA MMIC. Unfortunately, we do not currently have a two-tone test setup that can measure IMD3 at millimeter waves, so we investigate IMD3 through full EM simulation results. Figure 23 shows IMD3 as a function of P_out for the designed PA MMIC. The spacing of the input two-tone RF signal is set to 100 MHz and the frequency range is the upper Ka band. As shown in Figure 23, the IMD3 is best when the P_out is near 28 dBm, and it deteriorates to −20 dBc or higher when the P_out increases to 36 dBm or more. It can be seen that IMD3 worsens as the frequency increases.

Table 1. Performance comparison of reported Ka-band high-power amplifier MMICs ¹.

Reference	Frequency (GHz)	Technology	Pout (dBm)	PAE (%)	SS Gain 2 (dB)	VDD (V)	Size (mm2)
[9]	34–36	0.15 μm GaN HEMT	40–41	27–30	25–27	24	9.5
[15]	28–34	0.1 μm GaN HEMT	37–40.5	12.5–35	19–28	12–13	15.75
[10]	29.5–36	0.15 μm GaN HEMT	38.5–40.8	24–35	25–33	22.5	13.4
[12]	18–40	0.15 μm GaN HEMT	40.2–42.5	15–27	20–25.5	20	8.96
[16]	27–34	0.1 μm GaN HEMT	37.8–39.6	20–30	20	15	15.75
[17]	26–35	0.1 μm GaN HEMT	39.1–40.3	26.5–39.5	20–25	15	11.4
[13]	37–43	0.1 μm GaN HEMT	39.8–41.8	19–22	23–33	12	10.08
This work	Upper Ka band	0.1 μm GaN HEMT	38.5–39.7	14.1–18.2	12.8–16.6	12	22.0

¹ Some data were estimated from the reported paper. ² Small-signal gain.

summarizes the performance of the reported Ka-band high-power amplifier MMICs.

Compared to other previously reported works, the small-signal gain of this work is much smaller, resulting in a poorer PAE. However, it shows an average P_out of over 39 dBm in the upper Ka band. In particular, among GaN HEMT PA MMICs with a drain operating voltage (V_DD) within 15 V, this work shows competitive P_out performance in the upper Ka band.

4. Conclusions

This work presents an mmWave GaN HEMT PA MMIC, achieving a P_out ranging from 38.5 dBm to 39.7 dBm and a PAE between 14.1% and 18.2% over the frequency range of the upper Ka band. The study offers essential insights into designing GaN HEMT power amplifier MMICs operating in the millimeter-wave band above 30 GHz. Transistor sizing should consider not only maximum P_out and PAE but also high-frequency small-signal gain. Additionally, accurate EM validation of the provided source via models is crucial to include realistic parasitic effects of grounded source vias into the unit power cell design. Inserting resistors in the gate bias circuit proves effective in preventing low-frequency oscillations. The proposed PA MMIC demonstrates an average output power of over 8 W in the upper Ka band. These design guidelines serve as valuable references for implementing mmWave high-power GaN HEMT power amplifiers, expected to find increased applications in the future.