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Article

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

1
School of Electronic Science & Engineering, Southeast University, Nanjing 210096, China
2
National ASIC Center, Southeast University, Nanjing 210096, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(2), 465; https://doi.org/10.3390/electronics12020465
Submission received: 30 November 2022 / Revised: 4 January 2023 / Accepted: 13 January 2023 / Published: 16 January 2023

Abstract

The performance of analog and RF circuits is widely affected by the interconnection parasitic in the circuit. With the progress of technology, interconnection parasitics plays a larger role in performance deterioration. To solve this problem, designers must repeat layout design and validation process. In order to achieve an upgrade in the design efficiency, in this paper, a Graph Neural Network (GNN)-based pre-layout parasitic parameter prediction method is proposed and applied to the design optimization of a 28 nm PLL. With the new method adopted, the frequency band overlap rate of the VCO is improved by 2.3 percents for an equal design effort. Similarly, the optimized CP is superior to the traditional method with a 15 ps mismatch time. These improvements are achieved under the premise of greatly saving the optimization iteration and verification costs.
Keywords: analog circuit; machine learning; graph neural network; RF circuit analog circuit; machine learning; graph neural network; RF circuit
Graphical Abstract

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MDPI and ACS Style

Li, C.; Hu, D.; Zhang, X. Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network. Electronics 2023, 12, 465. https://doi.org/10.3390/electronics12020465

AMA Style

Li C, Hu D, Zhang X. Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network. Electronics. 2023; 12(2):465. https://doi.org/10.3390/electronics12020465

Chicago/Turabian Style

Li, Chenfeng, Dezhong Hu, and Xiaoyan Zhang. 2023. "Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network" Electronics 12, no. 2: 465. https://doi.org/10.3390/electronics12020465

APA Style

Li, C., Hu, D., & Zhang, X. (2023). Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network. Electronics, 12(2), 465. https://doi.org/10.3390/electronics12020465

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