Low-Power Single Bitline Load Sense Amplifier for DRAM

Abstract

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

1. Introduction

The volatile memory of static random access memory (SRAM) and dynamic random access memory (DRAM) are widely used in computing systems [1,2,3,4]. Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22 nm node results in high leakage power consumption, performance degradation, and instability due to process variations [5,6]. Benefiting from vertical multi-gate devices (FinFETs) and 2T/3T1D types of DRAM, embedded DRAMs are candidates to substitute SRAM in very large-scale integrated (VLSI) circuits [7], due to the DRAM having higher densities and lower cell leakage current in sleep mode. There are different kinds of cell types of DRAM, like 1T1C, 2T, 3T1C, 3T1D, etc. Though other types of DRAM show advantages over 1T1C cell in read and write operations, the mostly used 1T1C cell has the smallest cell area, showing the best memory density compared to other DRAM cells [8]. With the significant growth in modern computing systems, DRAM has become a power/performance/energy bottleneck in data-intensive applications [9,10,11]. Power consumption is a major issue in low-power and portable devices. New types of DRAM, like 2T and 3T1D, have been analyzed and compared, the results show that the minimum-energy point can be reduced by increasing the length of write transistor/boosting write word-line/using high-threshold voltage write transistor methods [12]. Furthermore, the power management mechanism and downscaling method are useful to reduce the energy consumption of DRAM. A new refresh scheme of DRAM, which can refresh with its own refresh period without requiring the external support, shows efficacy in enhancing energy efficiency [13]. In particular, downscaling DRAM shows better performance, less power dissipation and less read/write delays [14]. However, this comes at the cost of decreasing performance or facing difficulties in the smaller footprint of the DRAM capacitor. The performance of a 1T1C DRAM cell is affected due to various leakage sources in the MOS transistor [7]. Leakage is a crucial issue in DRAM, which will bring about the probability of data loss from storage capacitor increase and deteriorate the retention time [15]. Furthermore, optimizing the circuit of the sense amplifier (SA) is an efficient and convenient method to reduce the overall energy consumption of DRAM during some particular operations [16,17].

As shown in Figure 1, a conventional sensing circuit of 1T1C DRAM is composed of an SA circuit, a precharge circuit, a write circuit, an isolation circuit and DRAM arrays [11,18]. In a typical SA circuit, the orange color part comprises two cross-coupled inverters, a PMOS and a NMOS transistor. The input and output nodes of the SA are attached to the BL and BLB bitlines, respectively. When either one is selected as a target bitline, the other one is accordingly selected as the reference bitline. The precharge circuit is comprised of three NMOS transistors controlled by the PRE signal. At each operation cycle, the bitlines are charged to VDD/2 before accessing the DRAM cells [19]. The bitline nodes at the IO interface can transfer the amplified voltage to the IO bus or be driven by the write drivers with the help of IO transistors. Isolation transistors are only placed in a folded array structure to isolate SAs from different arrays for reuse [20,21].

Based on the conventional sensing circuit, a low power single bitline write (SBW) sensing circuit with reconfigurable I/O interface was also proposed [22,23]. The block turns off one of the isolation transistors to form single bitline load (SBL) circuit when the SA or write driver tries to drive a reference bitline from VDD/2 to VDD [24]. The SBW circuit turns off the isolation transistors connected to the reference bitlines during whole read and write operation, with the limited applications in the open bitline array, which lacks isolation transistors [25]. Furthermore, the SBW circuit generates greater energy consumption and time delay than a conventional circuit in a consecutive precharge stage.

In this study, we analyzed the different SA working stages and the energy consumption of DRAM arrays during different read and write operations. Then, we built a single bitline load sense amplifier and simulated its performance. Furthermore, we propose two improved SBLSA circuits to overcome some drawbacks existent in SBL circuits. Simulations indicate that both circuits consume less energy than conventional circuits no matter whatever data they read or write.

2. Methods

2.1. The Energy Consumption at Different Working Stages

Using the Formula (1) to qualitatively describe power consumption at different working stages, the actual power consumption was carried out by the product of voltage and the time integral of the current from the circuit simulations.

$$\mathrm{W}=\mathrm{U}\times \Delta \mathrm{Q}=\mathrm{U}\times {\displaystyle {\int }_{\mathrm{T}1}^{\mathrm{T}2}\mathrm{I}\mathrm{d}\mathrm{t}}$$

(1)

2.1.1. Precharge Stage

Each reading and writing cycle begins with a precharge stage, where both the BL and BLB with load capacitance C_b are biased at VDD/2 by the precharge circuit, assuming the initial voltage of the bitlines is zero. Energy consumption in the precharge stage can be defined as (VDD²C_b)/2 [26]. As shown in Figure 2, the bitline voltage is recovered to VDD/2 over the whole cycle. As a result, when an array is consecutively accessed, the bitlines are precharged and equilibrated to VDD/2 to form a full swing voltage, and this process is defined as a consecutive precharge stage. Owing to the dynamic charge transfer between BL and BLB, the energy consumption in the consecutive precharge stage is measured by the time integral of the current.

2.1.2. Pre-Sense and Post-Sense Stage

When the word line (WL) signal is turned on, the charge sharing between storage capacitors and the BL leads to a voltage variation (ΔV). There is no energy consumption in the pre-sense stage. While in the post-sense stage, the sense amplifier senses and amplifies ΔV to VDD, i.e., charging the BL to VDD and discharging the BLB to ground [27]. Theoretically, the energy consumption is (VDD²C_b)/2 for both the logic 0 and 1 states.

2.1.3. IO Transition Stage

In the IO transition stage, the data stored in the DRAM cells are identified based on the voltage on the bitlines. When the IO transistors are turned on, the data stored in the cells can be read out or modified through read/write operations [28,29]. The situation that the write data are matched with the stored data (read ‘0’-write ‘0’ and read ‘1’-write ‘1’) is not considered in the read–modify–write operation, since the energy consumption is supplied by an external circuit. During the write operation (read ‘0’-write ‘1’), where the write driver charges the BL and the storage capacitor (C_s) to VDD, the energy consumption is calculated as VDD²(C_b+C_s). Similarly, for read ‘1’-write ‘0’, where the write driver charges the BLB to VDD, the energy consumption is VDD²C_b.

2.2. Analysis of the Single Bitline Load Sense Amplifier

In an SBW circuit, the reference bitline is isolated from the SA and the precharge circuit by reusing the existing isolation transistors to reduce energy consumption in Macro (Figure 3a) [22]. During the read process, the precharge stage charges the BL and BLB to VDD/2, forming ∆V in the pre-sense stage. But in the post-sense stage, the BL and BLB are isolated from the SA to save the energy of amplifying the BL/BLB from ∆V to VDD. And in rewriting stage, the data are written only through the BL. However, the isolated transistor needs an additional control signal. Considering the necessity of isolation transistors in bitline arrays, the SBW circuit is only applicable to folded bitline arrays. As shown in Figure 3b, we proposed a single bitline load sense amplifier (SBLSA) circuit with added isolated switches to analyze the energy consumption at different stages. The switches are used to isolate the SA from the reference bitline and the precharge circuit. Though energy consumption in the precharge stage is inevitable, the voltage supply from the SA is not required to charge the BLB to VDD, thereby (VDD²C_b)/2 can be reduced in the post-sense stage. Similarly, during a read ‘1’-write ‘0’ operation, there is no voltage supply requirement for charging the BLB capacitance C_b from the write driver, resulting in reduced VDD²C_b in the IO transition stage. The newly added switches can be controlled by the least significant bit (LSB) of the row address line. The LSB signal can be latched and the reference bitline can be disconnected from the SA by turning off switch1 or switch2. In this study, the BL and BLB are, respectively, considered as target bitlines when LRA (LSB of the row address) is logic 0 and 1.

As shown in Figure 4, whether the folded or open bitline array are selected, every row address can be decoded and mapped to certain wordlines (e.g., WL0, WL1, WL2 and WL3) and bitlines (BL, BLB). This method builds a mapping relationship between the wordlines and bitlines, that is, WL0 and WL2 are mapped to BL, and WL1 and WL3 are mapped to BLB.

In both read or write operations, different from the full swing voltage in a conventional circuit, the SBLSA circuit makes reference and target bitlines achieve half swing voltage, owing to this the BLB remains constant at VDD/2. Bitline voltage swings from 0 to VDD/2 are termed negative half swings, and bitline voltage swings from VDD/2 to VDD are termed positive half swings. Compared with the full swing voltage, the half swing voltage shows two disadvantages. On the one hand, the SBLSA circuit generates greater energy consumption than a conventional circuit in a consecutive precharge stage. As shown in Figure 5, the area (time integral of current), which represents the energy consumption, of A1 is less than that of A2 and A3. On the other hand, when the SBLSA circuit reads or writes ‘1’, it requires a longer time to precharge the target bitline from VDD to VDD/2, i.e., T3 is longer than T1 and T2. To solve these problems, we propose two SBLSA circuits, i.e., the redundant voltage discharged SBLSA (RVD-SBLSA) and the bit aware SBLSA (BA-SBLSA) circuits, which can balance the latency and energy consumption well.

2.3. Redundant Voltage Discharge Sense Amplifier

Figure 6a shows the RVD-SBLSA circuit, where switch1 is composed of transistors N4 and P4, and switch2 is composed of N5 and P5. Compared with a conventional circuit, the additional parts are displayed in blue. As shown in Figure 6b, the RVD-SBLSA circuit performs the same functions as the SBLSA circuit. At the beginning of the post-sense stage, the SAN signal is low and both bitlines are connected to nodes DQ and DQB. As the SAN signal turns high, the switches are controlled by the address line signals of LRA and NLRA.

After the IO transition stage, an additional stage is required for discharging the redundant bitline voltage greater than VDD/2 during the read ‘1’ operation. For this reason, two NMOS transistors (N6 and N7) are used to form two diodes in an RVD-SBLSA circuit, and the bitline voltage is clamped at VDD/2. Thus, VDD/2 can drive both bitlines in the consecutive precharge stage without energy consumption during read ‘1’ and read ‘0’-write ‘1’ operations. As seen from the waveforms of the bitline voltage during different stages (Figure 7), the latency of the discharge and consecutive precharge stages can still be shorter than that of the SBLSA at the consecutive precharge stage.

2.4. Bit Aware Sense Amplifier

To further solve the two disadvantages discussed in an SBLSA circuit during the read ‘1’ operation, a new solution was proposed, which uses a double-ended bitline load during read ‘1’, and using a single-ended bitline load in other cases. As shown in Figure 8a, the BA-SBLSA circuit comprises two switches, two logic control gates (GNOR1, GNOR2), and two auxiliary write-back transistors (N6, N7). Compared with a BA-SBLSA circuit, the additional parts of a BA-SBLSA circuit are shown in red. An LRA signal is capable of identifying the target and reference bitlines. In addition, DQ and DQB need to be identified in the SRAM cell. GNOR is a NOR gate (Figure 8b), where the two inputs are DQ/DQB and the LRA signal. GNOR is used to control the operation mode of the write-back operation. At the beginning of the post-sense stage, switch1 and switch2 are closed to amplify the DQ and DQB nodes to the corresponding voltage. Hence, the amplified DQ and DQB represent the data stored in the cell. When the LRA is low, the BL is the target bitline and BLB is the reference bitline, then P4 will be turned off when DQ is logic 0 and turned on when DQ is logic 1, respectively, while P5 keeps the target bitline connecting with the SA. It is vice versa when the LRA is high. And the signal waveforms are shown in Figure 8c.

Bit-Aware and Write-Back Logic

Considering switch1 (P4) and switch2 (P5) are not transmission gates, there is a threshold voltage loss during transmitting logic 1 and 0. The placement of the auxiliary write-back transistors, N6 and N7 coupled with P5 and P4, can form complementary transistors. In the post-sense stage, N5 and N4 are off, and the GNOR logic gate decides whether to turn P4 and P5 on or turn off. Cooperating with N6 and N7, the data can be written back to the bitline and the DRAM cell without voltage loss.

During the read or write ‘0’ operation, the write-back operation should ensure the reference bitline disconnects from the SA; while during the read or write ‘1’ operation, the reference bitline should connect with the SA, which is same as a conventional SA. The control logic design is as follows. As shown in Figure 9a, when ‘0’ is read, i.e., the DQ and DQB will be logic 0 and 1, the X1 transistor will be turned off to ensure the GNOR output does not affect the reference bitline. At the same time, the X2 transistor will be turned on to successfully transmit logic 0 using the NMOS. In another case of reading ‘1’, DQ and DQB are logic 1 and 0, respectively, and signal X1 is turned on to transmit logic 0. Considering that the complementary PMOS can transmit logic 1, it shows no effect whether the X1 is turned on or turned off. These results show that we can reuse the DQ and DQB value as the control signals for X1 and X2, respectively (Figure 9b).

Based on the logic and circuit design, the waveforms of bitline voltage at different stages are depicted in Figure 10. During the read ‘1’ and read ‘0’-write ‘1’ operations, the BL and BLB show full wing voltage, which resolves the problems of larger energy consumption and longer time in the consecutive precharge stage.

3. Results and Discussion

These circuits were simulated in a 65 nm CMOS process design kit at 1.2 V and 25 °C. The bitline capacitance is 100 fF, and the storage cell capacitance is 30 fF. As shown in Figure 11a, compared with that of a conventional SA circuit, all the SBW, RVD-SBLSA and BA-SBLSA circuits show much reduced energy consumption during read ‘0’ operations, where the consecutive precharge stage is predominant. During read ‘1’, read ‘0’-write ‘1’ and read ‘1’-write ‘0’ operations (Figure 11b–d), both the RVD-SBLSA and BA-SBLSA circuits still show reduced energy consumption, while the SBW circuit shows increased energy consumption in the read ‘1’ operation, which is one disadvantage of the positive half swing voltage. In the case of SBLSA circuits, in read ‘1’ and read ‘0’-write ‘1’ operations (Figure 11b,c), the RVD-SBLSA and BA-SBLSA circuits show reduced energy consumption mainly in the consecutive precharge stage, and the RVD-SBLSA exhibits the lowest energy consumption. This is because the two proposed structures, RVD-SBLSA, put the voltage of the target bitline to VDD/2 in the IO transmission stage, thus avoiding the huge energy consumption caused by the positive half swing voltage in the continuous pre-charging stage. The BA-SBLSA switches single/double bitline load mode using a logic judgment circuit, so as to balance low power consumption and low latency (Figure 12). Furthermore, the energy consumptions under different processes and temperatures show the same tendency (

Table 1. Comparison of the energy consumptions of four structures under different processes and temperatures.

Energy Consumption (fJ)
Operation	Read ‘0’			Read ‘1’			Read ‘0’-Write ‘1’			Read ‘1’-Write ‘0’
Process corner/ Temperature (°C)	FF/ −40	TT/ 25	SS/ 125	FF/ −40	TT/ 25	SS/ 125	FF/ −40	TT/ 25	SS/ 125	FF/ −40	TT/ 25	SS/ 125
Conventional	113.8	116.4	121.5	113.8	116.4	121.2	365.7	366.4	371.1	333.0	334.3	339.1
SBW	67.5	68.7	71.1	146.5	146.3	146.9	278.0	276.0	271.8	160.4	163.5	161.6
RVD-SBLSA (this work)	69.1	70.4	73.0	109.2	99.6	91.7	231.2	215.3	208.5	159.0	160.0	155.8
BA-SBLSA (this work)	70.1	70.8	73.1	109.1	113.8	120.0	242.2	242.1	245.7	217.6	219.4	222.5

). To compare with the state-of-the-art results of SA in DRAM, the power consumption, which is in accordance with references, only contains read ‘0’ and ‘1’ operations. The proposed two circuits show better performance with less power consumption at different process technologies (

Table 2. Feature summary and comparison to other works.

	BRV-SA [10] a	CSC-SA [19] a	*P1 [30]	Conventional SA b	SBW [14] b	RVD-SBLSA (This Work)	BA-SBLSA (This Work)
Process (nm)	65	28	180	65	65	65	65
VDD (V)	1.0	0.9	0.8	1.2	1.2	1.2	1.2
Power consumption (μW)	6.44	10.73	108.81	3.09	2.92	2.31	2.50

^a: from references; ^b: evaluation under 65 nm process.

).

As shown in Figure 12, the SBW circuit requires the longest time to drive the VDD to VDD/2 in the consecutive precharge stage. Compared to the conventional SA circuit, the latency of tRCD+tRP increased by 30.1% for the SBW circuit, 25.0% for the RVD-SBLSA circuit and 5.8% for the BA-SBLSA circuit. Considering the energy consumption and latency, the RVD-SBLSA circuit can give the best energy performance, and the BA-SBLSA circuit can give a better balance between them. Considering the area consumption, the layouts of conventional, RVD-SBLSA and BA-SBLSA circuits are shown in Figure 13. The areas of the RVD-SBLSA and BA-SBLSA circuits are 1.6 and 5.6 times larger, respectively, than a conventional circuit.

4. Conclusions

In conclusion, we have analyzed the working stages and energy consumption of DRAM arrays during different read and write operations through simulations. The SBW circuit consumes more energy than a conventional SA circuit during read ‘1’ operations and needs a longer precharge latency for the target bitline. The RVD-SBLSA circuit achieves significantly reduced energy consumption by adding two discharge transistors with a discharge stage. The BA-SBLSA circuit improves latency through a write-back structure without additional timing control. Both RVD-SBLSA and BA-SBLSA circuits realize reduced energy consumption in any read and write operations. The stimulations show that the RVD-SBLSA circuit generates the lowest energy consumption and the BA-SBLSA circuit provides a better balance between energy consumption and latency. The areas of the RVD-SBLSA and BA-SBLSA circuits are 1.6 and 5.6 times larger than conventional circuits, respectively. Due to the possibility that parasitic capacitance may affect the charge sharing, the performance of RVD-SBLSA and BA-SBLSA circuits may deteriorate. In future works, detailed post-simulation and the chip performance should be measured and compared to give a more in-depth study. These results provide a new method for reducing energy consumption in DRAM arrays and these circuits show huge potential in very large-scale integrated circuits.