Anomalous PBTI Effects in N-Type Super Junction under High Gate Voltage Stress

Abstract

In this work, an anomalous thick oxide-degradation phenomenon in n-type 650-V class super-junction VDMOS transistors is investigated. An unexpected threshold voltage (V_t) decrease was observed with high positive bias temperature instability stress, and the saturation current (I_Dsat) increases with the stress time. Repeatable and reproducible behaviors have been achieved from multiple devices under test. Based on simulation and experimental results, it is found that the high-energy electrons (caused by high positive gate voltage) in the n-type region at the bottom of the gate oxide layer (top of the N-pillar) are injected into the gate oxide. The high-energy electrons generate electron-hole pairs during the transport to the anode, leaving holes in the gate oxide layer, and thus decreased V_t and increased I_Dsat. Finally, C-V measurement is also carried out which further confirms the above analysis.

1. Introduction

Super junction (SJ) introduces the PN junction into the conventional “resistive” voltage-resistant layer, turning it into a “junction voltage-resistant layer”. This qualitative change breaks through the “silicon limit” trade-off between the specific on-resistance and withstand voltage of traditional power devices. A thinner drift region and higher doping concentration can achieve lower on-resistance, but the breakdown voltage will decrease accordingly. Super-junction MOSFETs replace the conventional high-resistance with alternating P-pillars and N-pillars in the drift layer. The fixed positive and negative charges left in the depletion region can be mutually depleted when the two-pillar regions are charge-balanced. Therefore, the ionized impurity charge in the drift region does not affect the vertical withstand voltage; so, the pillar region can be doped with a higher concentration under the same withstand voltage [1,2,3].

Nevertheless, SJ devices are usually handled the under extreme condition of higher voltage and heavier current. Such an implementation scenario further highlights the significance of reliability of SJ devices which, however, has rarely been reported. Generally, SJ devices share similar structure as N-type MOSFET at the top, leading to MOS device-based reliability issues. As an important indicator of gate oxide degradation, bias temperature instability (BTI) is critical to the reliability of MOS devices. BTI is typically manifested by the threshold voltage (V_t) shift due to the charge trapping at Si/SiO₂ interface which can occur based on Fowler–Nordheim tunneling of the carriers under an external electric field [4,5,6,7,8,9,10,11,12]. Conventionally, V_t of pMOS device shifts to the negative direction after negative BTI (NBTI) stress, and I_Dsat decreases, while under the action of positive BTI (PBTI) stress, nMOS device’s V_t shifts to the positive direction, and I_Dsat decreases [13,14,15].

In this study, a 650-V class SJ device is designed and fabricated to study the BTI performance under high gate voltage stress. As compared to the conventional nMOS devices, all devices under test (DUTs) exhibit anomalous and opposite shift behavior in both V_t and I_Dsat. Based on simulation and experimental analysis, the degradation mechanism is proposed, and C-V measurement is further performed further supporting the analysis.

2. Result and Discussion

2.1. Device Structure

Figure 1a shows the structure diagram of the device cell. In the body area of each cell, the P-pillar and N-pillar are aligned alternately. The main feature size and doping concentration of the device are also demonstrated in Figure 1b. For testing convenience, the device is packaged using TO-220 as depicted in Figure 1c. The thickness of the gate oxide layer is 100 nm, with thickness inhomogeneity below 5%.

Figure 2 shows the fundamental electrical performance of the device studied in this work. As shown in Figure 2a with the blocking characteristics, I_D rises abruptly with 700 V bias which suggests that the withstand voltage performance of the device meets the design expectations. Capacitance characteristic is shown in Figure 2b, where C_iss is the input capacitor, Coss is the output capacitor, and C_rss is the reverse transfer capacitor. It is observed that these capacitances are V_D-dependent, with typical values of C_iss = 1819 pF, C_oss = 54.35 pF, and C_rss = 2.14 pF when V_D is 200 V. Transmission characteristic curve (I_D-V_D curve) is demonstrated in Figure 2c, with ~170 mῼ on-resistance (V_GS = 10 V, I_D = 7.3 A). Performance comparison between the fabricated structure with other reported devices is shown in

Table 1. Comparison of the performance of the fabricated device with similar devices.

Ref.	BV	Ron
[16]	680 V	15.5 mΩ·cm2
[17]	730 V	23 mΩ·cm2
[18]	650 V	24.7 mΩ·cm2
[19]	650 V	17 mΩ·cm2
[20]	750 V	24.6 mΩ·cm2
Proposed	700 V	17.5 mΩ·cm2

, which shows that the structure fabricated in this work has higher breakdown voltage and relatively lower on-resistance.

The full structure of the 650-V SJ device designed in this work is schematically shown in Figure 2d. The device structure is divided into cell and terminal regions (with only one cell illustrated in the figure). The terminal region is composed of alternating P- and N-pillars and field plates. The terminal region is designed to sustain the transverse electric potential from the edge-drift region of the devices, ensuring that the edge will not break down in advance. It is noted that this 650-V class SJ is fabricated by deep trench etching and epitaxial growth manufacture process. A trench with a certain aspect ratio is formed by etching, followed by P-type silicon epitaxial growth filling the trench and surface planarization. An n-type layer was formed at the top of N-pillars to further reduce the on-resistance.

2.2. Measurement Results and Analysis

Figure 3a,b shows the I_D-V_G and I_D-V_D curves obtained after different stress time using the stress condition of V_G = 75 V and V_DS = 0 V. Here, the stress voltage of 75 V is much higher than the operation voltage under normal conditions, and this is based on the consideration of extreme cases with driving circuit chip failure. Under such circumstances, the high voltage from the drain terminal leaks to the gate, and the voltage between the gate and source rises to a much higher value.

From Figure 3a,b, a clear shift towards negative direction is observed in V_t, and I_Dsat increases with longer stress time. The increase in I_Dsat is actually due to the decrease in threshold voltage in the initial stage of stress. It is noted that a similar trend has been obtained from multiple devices in this study. Such behavior is opposite to the performance of traditional MOSFET devices under the PBTI stress, as well as previous studies on the PBTI effect of VDMOS devices [13,14]. Figure 3c shows the change in gate current with increasing stress time. IGSS shows a relatively rapid increase in the first ~500 s stress followed by a slower decrease with longer stress time. It is worth mentioning that there are some discontinuities in the I_GSS curve at 700 s, which may be caused by the error of the test system (such as jitter).

Figure 3d summarizes and compares the threshold voltage and saturation current degradation behaviors under different temperatures of 300 K, 350 K, and 400 K. It is observed that high temperature can accelerate the degradation of the threshold voltage of the device at the initial stage of stress. When the stress time is greater than 500 s, the degradation level is basically the same, indicating that the effect of stress on device performance is gradually saturated. It is worth mentioning that initial and final I-V characteristics were measured at room and stress temperatures, but all other interim measurements were performed only at stress temperature in order to minimize the recovery effects.

Threshold voltage shifts under different gate voltage stresses are further studied. As shown in Figure 4, under lower forward voltages of 70 V (Figure 4a) and 72.5 V (Figure 4b), the I_D-V_G curves show the same shift trend. Specifically, with a 70-V forward voltage stress, negligible shifting is observed in the transfer curve with different stress time. As compared to the 75-V gate voltage stress shown in Figure 3a, a higher stress voltage level introduces a more significant V_t degradation. It is also observed that the device properties did not recover after prolonged standing after the stress, indicating that the degradation caused by stress is irreversible.

2.3. Mechanism Explanation

We first characterize the electric field distribution by using Sentaurus TCAD tools, which is shown in Figure 5a. The electric fields along the AA’ and BB’ (indicated in Figure 5a) are shown in Figure 5b,c, respectively. It is observed that under high positive gate voltage stress, the electric field in the N-type region under the gate oxide layer is sufficiently high, and hot electrons are generated which can easily be injected into the gate oxide layer.

Compared with traditional N-type MOS devices, the bottom of the gate oxide layer of an SJ device is mainly an N-type region. During the fabrication process, the doping concentration of the N-type region at the bottom of the gate oxide layer is generally higher than that of the N-pillar region in order to reduce the on-resistance of the device. To further study the mechanism of degradation, the I_D-V_G sweep in the forward and reverse directions are measured with 75-V stress voltage and different stress time. As depicted in Figure 6a, no hysteresis is observed between the forward and reverse curves for all the tested stress times, indicating no extra movable charges inside the gate oxide layer, and no fixed charges are generated under high gate stress voltage.

Figure 6b schematically shows the generation and transport of the carriers in the SJ cell. Under the application of a large electric field, the high gate voltage causes generation of more high-energy electrons in the N-type region at the top of the N-pillar. With high forward voltage, a large number of high-energy electrons is injected into the gate oxide. These high-energy electrons reach the anode under the electric field in the oxide layer and obtain a certain kinetic energy. At the same time, some of the high-energy electrons collide during the movement to generate electron-hole pairs. Most electrons reach the anode under the application of electric field. However, defects exist in SiO₂, such as silicon dangling bonds and micropores, which can evolve into adsorption centers trapping holes. This process is equivalent to injection of holes into the oxide layer, resulting in a shift in V_t, and an increase in I_Dsat. The degradation mechanism is related to hot carriers and tunneling instead of the hot holes. This is because the stress condition is the high positive gate voltage, and the electric field is preventing holes injecting into the gate oxide layer. In addition, the energy required for hole tunneling is larger, and the P-type region (hole-generating region) at the bottom of the gate is smaller than the N-type region (electron-generating region).

We have also tested the change in gate current when increasing V_G from 0 V to 75 V. During V_G ramping, the gate current is maintained below 500 pA and slowly increases, reaching 1.5 nA at 75 V finally. Considering the fact that there is no carrier inside the gate oxide layer, avalanche carriers cannot be generated by themselves, and the avalanche carriers that tunnel into the gate oxide are mainly generated at the bottom of the gate oxide. To further verify the degradation mechanism, C-V measurement is performed. Figure 7a–c shows the C-V curves obtained at 100-kHz frequency under PBTI stress with voltage of 70 V, 72.5 V, and 75 V. Under all stress conditions, the devices show a clear left shift in the C-V curves, which indicates extra positive charge generation in the gate oxide above the channel region. The C-V measurement result is consistent with the above analysis. At a higher gate voltage, more positive charges generated inside the oxide, the drift phenomenon is more obvious.

At the same time, it was found that in the process of stress, additional interface states are generated at the bottom of the gate oxide layer of the device, which are mainly caused by defects or surface states generated at the interface during the process of electron tunneling to the gate oxide layer. Such defects can lead to the bumps observed in the C-V curves as shown in Figure 7. A similar phenomenon is also observed when scanning the C-V curve under higher frequency of 1 MHz, suggesting that the resulting interface state can respond to at least 1-MHz frequency.

3. Conclusions

A 650-V class SJ MOSFET device is designed and fabricated. Anomalous V_t decrease behavior is observed with PBTI stress, and an increase in I_Dsat with the stress time is presented. Experimental and theoretical analyses have been performed seeking the mechanism, and it is concluded that the high-energy electrons caused by high positive gate voltage in the N-type region at the bottom of the gate oxide layer (top of the N-pillar) are injected into the gate oxide. The high-energy electrons generate electron-hole pairs in the process of moving to the anode. The electrons reach the anode and the holes remain in the gate oxide layer. As a result, the threshold voltage decreases and the saturation current increases. Such behavior and underlying principles are further verified and confirmed by C-V measurements. Our results can be instructive in future optimization of advanced power device design and engineering.