ParityCheckCRC Concatenated Polar Codes SSCFlip Decoder
Abstract
:1. Introduction
 We extend the work of [24] for simplified successive cancellation decoding and propose a PCCRCSSCFlip that exploits the role of the distributed parity checks to detect the incorrectly estimated erroneous bit at the early stages in the SSCFlip decoding and corrects that bit. The proposed technique minimizes the average decoding complexity and latency by halting the decoding process with early detection.
 We introduce an errorprone flipping list by incorporating the indices that are more suspected to be in an error [19] and the first bit of each Rate1 node [11]. The proposed algorithm recalls the paritybit and narrows down the search space whenever an error is detected. Once an error is detected by a parity bit, the proposed technique considers the bits of FL preceding that parity bit.
 In addition, the proposed PCCRCSSCFlip can correct two erroneous bits. It flips the first erroneous decision generated by the initial SC decoding, while the second erroneous decision is flipped in the decoding trajectory determined by the previous flips. This algorithm can be easily employed for more than two erroneous decisions. Although the multierroneous decision flipping algorithm improves the BLER performance of SCFlip decoding, it results in high computational complexity. The PCCRCSSCFlip immediately terminates the corresponding process with the error detection that minimizing the average decoding complexity and latency of the SCFlip.
2. Preliminaries
2.1. Polar Codes and SC Decoding
2.2. Simplified Successive Cancellation (SSC) Decoding
2.3. Successive Cancellation Flip (SCFlip) Decoding
2.4. OracleAssisted Successive Cancellation (OASC) Decoding
3. Proposed Scheme
3.1. Construction of FL
3.2. ParityCheckCRCConcatenated Polar Encoder
3.3. ParityCheckCRCAided SSCFlip Decoding
 Initialize the local and global parameters such as the loop control variable (j), information set indices ($\mathcal{A}$), parity bit indices ($\mathcal{P}$), the maximum number of flipping attempts ($\mathcal{T}$), and the number of flips ($\alpha $).
 Algorithm 1 begins decoding with standard SC decoding and obtains the estimated information bits $\left({\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}\right)$ in line 2. Verify the estimated message $\left({\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}\right)$ through the CRC procedure and check the remainder (r) in lines 3 and 4, respectively. If r is zero, break and return $\left({\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}\right)$. Otherwise, call Algorithm 2 (Calculate_Parity(.)) in line 7.
 (Calculate_Parity(.)) initializes the local parameters and calculates the parity bits ${w}_{pk}$ in line 4 by iterating through the paritycheck vector K. Compare the computed parity ${w}_{pk}$ with the corresponding ${u}_{pk}$ in line 5 and set the $parity\text{\_}flag$ value. Return the index ${\left\{i\right\}}_{i={p}_{k}}$ and $parity\text{\_}flag$ value to the calling script.
 Algorithm 1 decides the errorprone bit in line 10 and calls Algorithm 3 (ET_SSCFlip(.)) in line 11 to flip the errorprone bit. The ET_SSCFlip(.) flips and computes the estimated information bit in line 4. The function $h\left(\right)open="("\; close=")">L({\widehat{y}}_{i},i,e$ in Algorithm 3 is used to decide the hard decision through (8).
 The ET_SSCFlip(.) calls Algorithm 2 in line 6 to verify the parity bit. It checks the flag value in line 7 and terminates early once the flag value is zero, and returns to calling script.
 Algorithm 1 checks the returned flag value in line 12. If the flag value is true in line 12, it passes estimated $\left({\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}\right)$ through the CRC procedure and check r in line 14 to verify the estimated message. If r is zero, break. Otherwise, perform the next flipping attempt in lines 9–18.
 Algorithm 4 is used to flip two erroneous decisions. The flipping mechanism for the first incorrectly estimated bit follows the steps of Algorithm 1 in lines 8–17. It further performs the nested ith ($2\le i\le \alpha $) flip in the new trajectory obtained from the previous flips in lines 20–23.$$h\left(\right)open="("\; close=")">L\left({\widehat{y}}_{i}\right),i,e$$
Algorithm 1 Single bit flipping PCCRCSSCFlip Algorithm 
Input: $ll{r}_{1}^{\mathcal{N}}$, $\mathcal{A}$, $\mathcal{P}$, $\mathcal{T}$, $\alpha =1$ Output: ${\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}$

Algorithm 2 Calculate_Parity(${\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}},\mathcal{A},\mathcal{P}$) 

Algorithm 3 ET_SSCFlip($ll{r}_{1}^{N},\mathcal{A},\mathcal{P},e$) 

Algorithm 4 Two bits flipping PCCRCSSCFlip Algorithm 
Input: $ll{r}_{1}^{N}$, $\mathcal{A}$, $\mathcal{P}$ ,$\alpha =2$ Output: ${\left\{{\widehat{u}}_{i}\right\}}_{i\in \mathcal{A}}$

4. Simulation Results
4.1. Early Stopping Performance and Decoding Latency
4.2. Average Computational Complexity
4.3. Block Error Rate (BLER) Performance
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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${\mathit{E}}_{\mathit{b}}/{\mathit{N}}_{0}$ (dB)  K Parity Bits  

1st  2nd  3rd  4th  5th  6th  7th  8th  
0.2  43%  18%  16%  13%  5%  1%  1%  3% 
0.4  43%  16%  14%  12%  6%  2%  2%  5% 
0.6  41%  15%  15%  10%  9%  4%  1%  5% 
0.8  35%  12%  14%  17%  10%  4%  1%  7% 
1  35%  18%  11%  13%  12%  4%  1%  6% 
1.2  30%  20%  16%  13%  10%  5%  2%  4% 
1.4  28%  17%  13%  16%  12%  7%  1%  6% 
1.6  24%  14%  15%  16%  10%  9%  1%  11% 
1.8  23%  14%  11%  17%  15%  8%  2%  10% 
2  20%  15%  9%  17%  14%  10%  2%  13% 
Decoding Algorithms  ${\mathit{E}}_{\mathit{b}}/{\mathit{N}}_{0}$ (dB)  

1  1.2  1.4  1.6  1.8  2  
SCFlip  46,057  33,160  17395  11,256  9210  6141 
Improved SCFlip  27,634  23,540  15,557  10,849  8188  5526 
PCCRCSCFlip  9211  8410  5607  4005  3043  2082 
Decoding Methods  SCFlip [9]  SCFano ($\Delta $ = 1) [31]  SCFano ($\Delta $ = 5) [31]  Improved SCFlip [10]  DSCFlip [20]  PCSCFlip [24]  PCCRCSSCFlip  

Required ${\mathit{E}}_{\mathit{b}}/{\mathit{N}}_{\mathbf{0}}$ * (dB)  2.7  2.5  2.9  2.6  2.6  2.6  2.6  
Complexity ($\mathbf{\times}{\mathbf{10}}^{\mathbf{4}}$)  LLR compute.  3.072  4.096  2.048  2.8672  3.072  2.015  1.766 
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Jan, Q.; Hussain, S.; Furqan, M.; Pan, Z.; Liu, N.; You, X. ParityCheckCRC Concatenated Polar Codes SSCFlip Decoder. Electronics 2022, 11, 3839. https://doi.org/10.3390/electronics11233839
Jan Q, Hussain S, Furqan M, Pan Z, Liu N, You X. ParityCheckCRC Concatenated Polar Codes SSCFlip Decoder. Electronics. 2022; 11(23):3839. https://doi.org/10.3390/electronics11233839
Chicago/Turabian StyleJan, Qasim, Shahid Hussain, Muhammad Furqan, Zhiwen Pan, Nan Liu, and Xiaohu You. 2022. "ParityCheckCRC Concatenated Polar Codes SSCFlip Decoder" Electronics 11, no. 23: 3839. https://doi.org/10.3390/electronics11233839