A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer
Abstract
:1. Introduction
2. Overall Architecture
3. Circuit Implementation
3.1. Split CDAC
3.2. Input PGA
3.3. RV-Buffer
4. Measurement Results
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Supply Voltage | 1.2 V | Output Swing | 1.8 Vpp.diff |
Common mode Output Voltage | 0.6 V | DC Current | 6.78 mA |
DC Gain | 77 dB | GBW | 1.95 GHz |
Phase Margin | 50° | IRN | 1.52 nV/√Hz |
This Work | [6] | [7] | [22] | [23] | |
---|---|---|---|---|---|
Architecture | PGA + ADC + RV-Buffer | PGA + ADC | PGA + ADC | ADC | ADC |
Technology | 65 nm | 65 nm | 0.18 μm | 0.18 μm | 0.18 μm |
Supply Voltage (V) | 1.2/2.5 * | 1.2 | 1.8 | 1.2 | 1.2 |
PowerADC (mW) | 0.8 | 0.26 | 22.2 | 0.736 | 4.734 |
PowerPGA (mW) | 8.1 | 0.16 | 5.9 | / | / |
Gain Range (dB) | 0~18 | −6, 0, 6 | −3~0 | / | / |
Resolution (bits) | 12 | 10 | 12 | 10 | 12 |
Sampling Frequency (MS/s) | 50 | 40 | 50 | 40 | 50 |
Input Range for ADC (Vpp) | 1.8 | 0.88 | 1.5 | 1 | 1.4 |
ENOBpeak | 8.16 | 9 | 10 | 9.13 | 10.4 |
SNRpeak | 50.9 | / | / | 56.7 | 64.3 |
SFDRpeak | 62.35 | 72 | 73.1 | 65.8 | 74.7 |
FoMADC (fJ/conv.-step) ** | 55.9 | 21.7 *** | 433.6 | 32.84 *** | 70.6 *** |
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Xu, Z.; Hu, B.; Wu, T.; Yao, Y.; Chen, Y.; Ren, J.; Ma, S. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics 2022, 11, 1841. https://doi.org/10.3390/electronics11121841
Xu Z, Hu B, Wu T, Yao Y, Chen Y, Ren J, Ma S. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics. 2022; 11(12):1841. https://doi.org/10.3390/electronics11121841
Chicago/Turabian StyleXu, Zhuofan, Biao Hu, Tianxiang Wu, Yuting Yao, Yong Chen, Junyan Ren, and Shunli Ma. 2022. "A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer" Electronics 11, no. 12: 1841. https://doi.org/10.3390/electronics11121841
APA StyleXu, Z., Hu, B., Wu, T., Yao, Y., Chen, Y., Ren, J., & Ma, S. (2022). A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer. Electronics, 11(12), 1841. https://doi.org/10.3390/electronics11121841